Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.93 98.99 96.40 100.00 98.08 98.36 99.91 93.77


Total tests in report: 915
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
45.53 45.53 46.97 46.97 30.36 30.36 53.19 53.19 98.08 98.08 53.67 53.67 33.71 33.71 2.70 2.70 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.2163672319
68.63 23.10 72.76 25.79 66.59 36.23 86.56 33.37 98.08 0.00 76.19 22.52 58.15 24.44 22.07 19.37 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.3289839334
78.34 9.71 86.53 13.77 77.80 11.21 93.17 6.61 98.08 0.00 87.47 11.28 75.00 16.85 30.32 8.26 /workspace/coverage/default/23.sysrst_ctrl_combo_detect.3277742894
84.05 5.71 86.96 0.43 80.61 2.81 94.31 1.14 98.08 0.00 88.30 0.84 75.94 0.94 64.12 33.80 /workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.3781071294
88.25 4.20 92.88 5.92 85.28 4.67 94.31 0.00 98.08 0.00 93.53 5.22 89.14 13.20 64.54 0.42 /workspace/coverage/default/0.sysrst_ctrl_feature_disable.3198449835
91.02 2.77 95.38 2.50 88.12 2.84 95.22 0.91 98.08 0.00 94.99 1.46 93.16 4.03 72.22 7.68 /workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.2286874151
92.71 1.68 97.26 1.88 89.46 1.34 97.04 1.82 98.08 0.00 96.21 1.22 95.22 2.06 75.70 3.48 /workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.1746979540
93.55 0.84 97.50 0.24 92.99 3.53 97.04 0.00 98.08 0.00 96.69 0.49 96.07 0.84 76.48 0.78 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.730486388
94.28 0.73 97.86 0.36 93.37 0.38 98.41 1.37 98.08 0.00 96.90 0.21 96.63 0.56 78.71 2.23 /workspace/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.4073137093
94.79 0.51 98.09 0.23 93.66 0.29 98.41 0.00 98.08 0.00 97.18 0.28 97.28 0.66 80.84 2.13 /workspace/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.3122330248
95.14 0.35 98.21 0.12 93.99 0.33 98.63 0.23 98.08 0.00 97.32 0.14 97.66 0.37 82.09 1.25 /workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.21196975
95.45 0.31 98.21 0.00 94.87 0.88 99.09 0.46 98.08 0.00 97.35 0.03 97.66 0.00 82.87 0.78 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.703448575
95.73 0.28 98.21 0.00 94.87 0.00 99.09 0.00 98.08 0.00 97.35 0.00 97.66 0.00 84.84 1.97 /workspace/coverage/default/10.sysrst_ctrl_combo_detect.497131973
95.97 0.24 98.23 0.02 95.02 0.14 99.09 0.00 98.08 0.00 97.39 0.03 97.85 0.19 86.14 1.30 /workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.3721763084
96.12 0.15 98.23 0.00 95.02 0.00 99.09 0.00 98.08 0.00 97.39 0.00 97.85 0.00 87.18 1.04 /workspace/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.2689995580
96.25 0.13 98.23 0.00 95.04 0.02 99.77 0.68 98.08 0.00 97.39 0.00 97.94 0.09 87.28 0.10 /workspace/coverage/default/1.sysrst_ctrl_sec_cm.1782204955
96.38 0.13 98.23 0.00 95.04 0.00 100.00 0.23 98.08 0.00 97.39 0.00 97.94 0.00 87.95 0.67 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.1997247499
96.50 0.13 98.23 0.00 95.04 0.00 100.00 0.00 98.08 0.00 97.39 0.00 97.94 0.00 88.84 0.88 /workspace/coverage/default/42.sysrst_ctrl_combo_detect.11153578
96.62 0.12 98.23 0.00 95.04 0.00 100.00 0.00 98.08 0.00 97.39 0.00 97.94 0.00 89.67 0.83 /workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.267571157
96.73 0.11 98.32 0.09 95.09 0.05 100.00 0.00 98.08 0.00 97.49 0.10 98.13 0.19 89.98 0.31 /workspace/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.1592729402
96.83 0.10 98.42 0.10 95.16 0.07 100.00 0.00 98.08 0.00 97.60 0.10 98.41 0.28 90.13 0.16 /workspace/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.2705606965
96.93 0.10 98.51 0.09 95.30 0.14 100.00 0.00 98.08 0.00 97.70 0.10 98.78 0.37 90.13 0.00 /workspace/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.2464626602
97.01 0.08 98.59 0.09 95.40 0.10 100.00 0.00 98.08 0.00 97.81 0.10 99.06 0.28 90.13 0.00 /workspace/coverage/default/6.sysrst_ctrl_stress_all.1595438587
97.09 0.08 98.68 0.09 95.47 0.07 100.00 0.00 98.08 0.00 97.91 0.10 99.25 0.19 90.24 0.10 /workspace/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.2703290688
97.17 0.08 98.72 0.03 95.85 0.38 100.00 0.00 98.08 0.00 97.98 0.07 99.25 0.00 90.29 0.05 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.4070693303
97.24 0.07 98.72 0.00 95.85 0.00 100.00 0.00 98.08 0.00 97.98 0.00 99.25 0.00 90.81 0.52 /workspace/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.385195831
97.30 0.06 98.78 0.07 95.92 0.07 100.00 0.00 98.08 0.00 98.05 0.07 99.44 0.19 90.81 0.00 /workspace/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.1344944315
97.35 0.05 98.82 0.03 95.97 0.05 100.00 0.00 98.08 0.00 98.09 0.03 99.63 0.19 90.86 0.05 /workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.2556458623
97.40 0.05 98.82 0.00 95.99 0.02 100.00 0.00 98.08 0.00 98.09 0.00 99.63 0.00 91.17 0.31 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.3212773439
97.44 0.05 98.82 0.00 96.02 0.02 100.00 0.00 98.08 0.00 98.09 0.00 99.72 0.09 91.38 0.21 /workspace/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.1536944036
97.49 0.04 98.82 0.00 96.02 0.00 100.00 0.00 98.08 0.00 98.09 0.00 99.72 0.00 91.69 0.31 /workspace/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.3645223403
97.53 0.04 98.82 0.00 96.02 0.00 100.00 0.00 98.08 0.00 98.09 0.00 99.72 0.00 92.00 0.31 /workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.2196894715
97.56 0.03 98.82 0.00 96.02 0.00 100.00 0.00 98.08 0.00 98.09 0.00 99.72 0.00 92.21 0.21 /workspace/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.3047377054
97.59 0.03 98.82 0.00 96.02 0.00 100.00 0.00 98.08 0.00 98.09 0.00 99.72 0.00 92.42 0.21 /workspace/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.2893764316
97.62 0.03 98.82 0.00 96.02 0.00 100.00 0.00 98.08 0.00 98.09 0.00 99.72 0.00 92.63 0.21 /workspace/coverage/default/43.sysrst_ctrl_combo_detect.1126646366
97.65 0.03 98.82 0.00 96.21 0.19 100.00 0.00 98.08 0.00 98.09 0.00 99.72 0.00 92.63 0.00 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.2876698007
97.67 0.03 98.85 0.03 96.23 0.02 100.00 0.00 98.08 0.00 98.12 0.03 99.81 0.09 92.63 0.00 /workspace/coverage/default/37.sysrst_ctrl_auto_blk_key_output.2739151615
97.70 0.03 98.89 0.03 96.26 0.02 100.00 0.00 98.08 0.00 98.16 0.03 99.91 0.09 92.63 0.00 /workspace/coverage/default/48.sysrst_ctrl_stress_all.1177351796
97.72 0.02 98.89 0.00 96.26 0.00 100.00 0.00 98.08 0.00 98.16 0.00 99.91 0.00 92.78 0.16 /workspace/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.2238672260
97.74 0.01 98.92 0.03 96.26 0.00 100.00 0.00 98.08 0.00 98.22 0.07 99.91 0.00 92.78 0.00 /workspace/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.2653278639
97.75 0.01 98.92 0.00 96.26 0.00 100.00 0.00 98.08 0.00 98.22 0.00 99.91 0.00 92.89 0.10 /workspace/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.2637210209
97.77 0.01 98.92 0.00 96.26 0.00 100.00 0.00 98.08 0.00 98.22 0.00 99.91 0.00 92.99 0.10 /workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.1528144771
97.78 0.01 98.92 0.00 96.26 0.00 100.00 0.00 98.08 0.00 98.22 0.00 99.91 0.00 93.09 0.10 /workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.3793432694
97.80 0.01 98.92 0.00 96.26 0.00 100.00 0.00 98.08 0.00 98.22 0.00 99.91 0.00 93.20 0.10 /workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.4027599704
97.81 0.01 98.94 0.02 96.26 0.00 100.00 0.00 98.08 0.00 98.26 0.03 99.91 0.00 93.20 0.00 /workspace/coverage/default/15.sysrst_ctrl_edge_detect.1657133485
97.81 0.01 98.96 0.02 96.26 0.00 100.00 0.00 98.08 0.00 98.29 0.03 99.91 0.00 93.20 0.00 /workspace/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.557878274
97.82 0.01 98.98 0.02 96.26 0.00 100.00 0.00 98.08 0.00 98.33 0.03 99.91 0.00 93.20 0.00 /workspace/coverage/default/20.sysrst_ctrl_edge_detect.2965020181
97.83 0.01 98.99 0.02 96.26 0.00 100.00 0.00 98.08 0.00 98.36 0.03 99.91 0.00 93.20 0.00 /workspace/coverage/default/22.sysrst_ctrl_edge_detect.4264165828
97.84 0.01 98.99 0.00 96.26 0.00 100.00 0.00 98.08 0.00 98.36 0.00 99.91 0.00 93.25 0.05 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.3307116814
97.84 0.01 98.99 0.00 96.26 0.00 100.00 0.00 98.08 0.00 98.36 0.00 99.91 0.00 93.30 0.05 /workspace/coverage/default/10.sysrst_ctrl_stress_all.3961955352
97.85 0.01 98.99 0.00 96.26 0.00 100.00 0.00 98.08 0.00 98.36 0.00 99.91 0.00 93.35 0.05 /workspace/coverage/default/13.sysrst_ctrl_combo_detect.871642696
97.86 0.01 98.99 0.00 96.26 0.00 100.00 0.00 98.08 0.00 98.36 0.00 99.91 0.00 93.41 0.05 /workspace/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.2529224127
97.86 0.01 98.99 0.00 96.26 0.00 100.00 0.00 98.08 0.00 98.36 0.00 99.91 0.00 93.46 0.05 /workspace/coverage/default/28.sysrst_ctrl_combo_detect.562475415
97.87 0.01 98.99 0.00 96.26 0.00 100.00 0.00 98.08 0.00 98.36 0.00 99.91 0.00 93.51 0.05 /workspace/coverage/default/36.sysrst_ctrl_combo_detect.1666868017
97.88 0.01 98.99 0.00 96.26 0.00 100.00 0.00 98.08 0.00 98.36 0.00 99.91 0.00 93.56 0.05 /workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.740508734
97.89 0.01 98.99 0.00 96.26 0.00 100.00 0.00 98.08 0.00 98.36 0.00 99.91 0.00 93.61 0.05 /workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.854165284
97.89 0.01 98.99 0.00 96.26 0.00 100.00 0.00 98.08 0.00 98.36 0.00 99.91 0.00 93.67 0.05 /workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.640329141
97.90 0.01 98.99 0.00 96.26 0.00 100.00 0.00 98.08 0.00 98.36 0.00 99.91 0.00 93.72 0.05 /workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.1129624524
97.91 0.01 98.99 0.00 96.26 0.00 100.00 0.00 98.08 0.00 98.36 0.00 99.91 0.00 93.77 0.05 /workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.53749875
97.92 0.01 98.99 0.00 96.30 0.05 100.00 0.00 98.08 0.00 98.36 0.00 99.91 0.00 93.77 0.00 /workspace/coverage/default/1.sysrst_ctrl_feature_disable.2201357794
97.92 0.01 98.99 0.00 96.35 0.05 100.00 0.00 98.08 0.00 98.36 0.00 99.91 0.00 93.77 0.00 /workspace/coverage/default/10.sysrst_ctrl_alert_test.4233876579
97.93 0.01 98.99 0.00 96.37 0.02 100.00 0.00 98.08 0.00 98.36 0.00 99.91 0.00 93.77 0.00 /workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.2029708844

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.2605172918
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.1118023856
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.1035519455
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.1209168808
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.4064318232
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.825845685
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.332104896
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.2093894623
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.2379371339
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.731546944
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.3807643215
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.3065652971
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.1487689506
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.2083297044
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.1546232887
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.2661639905
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.363186819
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.2521236628
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.433181848
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.1362286781
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.2855830451
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.2868449666
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.1175301884
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.2537298788
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.1181434772
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.2809933129
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.3299953868
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.3180670516
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.1268061663
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.2273343261
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.710538414
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.1172167845
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.3274063504
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.3046028005
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.4207932760
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.1835690572
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.618281458
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.3863435867
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.3353127545
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.2618500634
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.4055278917
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.2213067119
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.2683026707
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.710107665
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.187216903
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.1028634779
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.3239431126
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.3624372789
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.3441602101
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.687152185
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.1981349960
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.1108123015
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.410269523
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.1522576989
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.2209806896
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.3786780142
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.16876359
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.2957902566
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.2415888922
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.670100750
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.669221084
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.2545991474
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.894861695
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.216526244
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.3544829273
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.1106188800
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.203696908
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.165305780
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.1206137401
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.1418649396
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.2579854750
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.2578636348
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.1307161172
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.3683043526
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.926824287
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.790901267
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.3557205783
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.2814065823
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.2931305129
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.1404116131
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.2580950319
/workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.2358108540
/workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.940345808
/workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.2143652838
/workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.4170083785
/workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.2753624584
/workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.2375947557
/workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.3782573648
/workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.1776376576
/workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.4136889073
/workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.1203770736
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.140480899
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.696814831
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.3170180427
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.2831466155
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/workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.1169233669
/workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.1188289580
/workspace/coverage/default/42.sysrst_ctrl_edge_detect.2523972246
/workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.2227894516
/workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.1685620967
/workspace/coverage/default/42.sysrst_ctrl_pin_access_test.1599027019
/workspace/coverage/default/42.sysrst_ctrl_pin_override_test.188767996
/workspace/coverage/default/42.sysrst_ctrl_smoke.91700716
/workspace/coverage/default/42.sysrst_ctrl_stress_all.864188859
/workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.2907522077
/workspace/coverage/default/43.sysrst_ctrl_alert_test.4193329644
/workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.130276823
/workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.3431264253
/workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.2633377663
/workspace/coverage/default/43.sysrst_ctrl_edge_detect.4074510711
/workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.1844944367
/workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.1090084495
/workspace/coverage/default/43.sysrst_ctrl_pin_access_test.3453588519
/workspace/coverage/default/43.sysrst_ctrl_pin_override_test.2137788856
/workspace/coverage/default/43.sysrst_ctrl_smoke.224929875
/workspace/coverage/default/43.sysrst_ctrl_stress_all.3666828111
/workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.503667361
/workspace/coverage/default/44.sysrst_ctrl_alert_test.4218252297
/workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.621403624
/workspace/coverage/default/44.sysrst_ctrl_combo_detect.2569108147
/workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.1911394713
/workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.1136403354
/workspace/coverage/default/44.sysrst_ctrl_edge_detect.1010741112
/workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.2123845683
/workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.3004444268
/workspace/coverage/default/44.sysrst_ctrl_pin_access_test.3888047714
/workspace/coverage/default/44.sysrst_ctrl_pin_override_test.2949727314
/workspace/coverage/default/44.sysrst_ctrl_smoke.519184828
/workspace/coverage/default/44.sysrst_ctrl_stress_all.1784764108
/workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.1458676147
/workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.1612852536
/workspace/coverage/default/45.sysrst_ctrl_alert_test.3577400983
/workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.1304862925
/workspace/coverage/default/45.sysrst_ctrl_combo_detect.498800021
/workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.3400302162
/workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.1345090951
/workspace/coverage/default/45.sysrst_ctrl_edge_detect.3147621080
/workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.314761569
/workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.709526378
/workspace/coverage/default/45.sysrst_ctrl_pin_access_test.174840843
/workspace/coverage/default/45.sysrst_ctrl_pin_override_test.571009799
/workspace/coverage/default/45.sysrst_ctrl_smoke.103846841
/workspace/coverage/default/45.sysrst_ctrl_stress_all.4219254586
/workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.2384361666
/workspace/coverage/default/46.sysrst_ctrl_alert_test.1799905735
/workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.3189532255
/workspace/coverage/default/46.sysrst_ctrl_combo_detect.175954213
/workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.1757319579
/workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.454129990
/workspace/coverage/default/46.sysrst_ctrl_edge_detect.3185361171
/workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.1833391183
/workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.1879183654
/workspace/coverage/default/46.sysrst_ctrl_pin_access_test.3278469059
/workspace/coverage/default/46.sysrst_ctrl_pin_override_test.2845943494
/workspace/coverage/default/46.sysrst_ctrl_smoke.722052424
/workspace/coverage/default/46.sysrst_ctrl_stress_all.2041991526
/workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.1330136462
/workspace/coverage/default/47.sysrst_ctrl_alert_test.3295887952
/workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.790808245
/workspace/coverage/default/47.sysrst_ctrl_combo_detect.2858549747
/workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.174333246
/workspace/coverage/default/47.sysrst_ctrl_edge_detect.3301575538
/workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.4032278780
/workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.186204904
/workspace/coverage/default/47.sysrst_ctrl_pin_access_test.3165837415
/workspace/coverage/default/47.sysrst_ctrl_pin_override_test.4224635892
/workspace/coverage/default/47.sysrst_ctrl_smoke.3004532764
/workspace/coverage/default/47.sysrst_ctrl_stress_all.157508743
/workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.1545417483
/workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.3296611725
/workspace/coverage/default/48.sysrst_ctrl_alert_test.2445597957
/workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.2270062850
/workspace/coverage/default/48.sysrst_ctrl_combo_detect.1479833187
/workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.3204866722
/workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.3657301087
/workspace/coverage/default/48.sysrst_ctrl_edge_detect.66025528
/workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.293540931
/workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.432265834
/workspace/coverage/default/48.sysrst_ctrl_pin_access_test.3654858572
/workspace/coverage/default/48.sysrst_ctrl_pin_override_test.1872691883
/workspace/coverage/default/48.sysrst_ctrl_smoke.152806871
/workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.813265617
/workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.2646752998
/workspace/coverage/default/49.sysrst_ctrl_alert_test.3270991592
/workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.4127017680
/workspace/coverage/default/49.sysrst_ctrl_combo_detect.877887469
/workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.802225960
/workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.3689612015
/workspace/coverage/default/49.sysrst_ctrl_edge_detect.3067852465
/workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.3828967529
/workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.2899154704
/workspace/coverage/default/49.sysrst_ctrl_pin_access_test.3513261229
/workspace/coverage/default/49.sysrst_ctrl_pin_override_test.59756138
/workspace/coverage/default/49.sysrst_ctrl_smoke.1824780640
/workspace/coverage/default/49.sysrst_ctrl_stress_all.2936602005
/workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.1216737913
/workspace/coverage/default/5.sysrst_ctrl_alert_test.1398122579
/workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.2906360683
/workspace/coverage/default/5.sysrst_ctrl_combo_detect.2186194249
/workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.2115144143
/workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.1216409755
/workspace/coverage/default/5.sysrst_ctrl_edge_detect.953580915
/workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.4065242667
/workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.2650668405
/workspace/coverage/default/5.sysrst_ctrl_pin_access_test.3315658126
/workspace/coverage/default/5.sysrst_ctrl_pin_override_test.3066299282
/workspace/coverage/default/5.sysrst_ctrl_smoke.2941406000
/workspace/coverage/default/5.sysrst_ctrl_stress_all.1039982482
/workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.3348993303
/workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.3320245385
/workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.920946175
/workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.303192675
/workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.3344529836
/workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.1536960208
/workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.3358539908
/workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.1513291431
/workspace/coverage/default/6.sysrst_ctrl_alert_test.3743495483
/workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.1859235434
/workspace/coverage/default/6.sysrst_ctrl_combo_detect.857556525
/workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.2118425395
/workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.870835831
/workspace/coverage/default/6.sysrst_ctrl_edge_detect.157566050
/workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.1331296011
/workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.1017712712
/workspace/coverage/default/6.sysrst_ctrl_pin_access_test.1578992156
/workspace/coverage/default/6.sysrst_ctrl_pin_override_test.1024311742
/workspace/coverage/default/6.sysrst_ctrl_smoke.2515383019
/workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.2633203723
/workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.877493894
/workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.433496094
/workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.901910123
/workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.2694478098
/workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.312974139
/workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.261828739
/workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.3197960518
/workspace/coverage/default/7.sysrst_ctrl_alert_test.2620098496
/workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.2845506704
/workspace/coverage/default/7.sysrst_ctrl_combo_detect.1777764247
/workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.2481796032
/workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.859555630
/workspace/coverage/default/7.sysrst_ctrl_edge_detect.3378144403
/workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.1608244529
/workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.325385174
/workspace/coverage/default/7.sysrst_ctrl_pin_access_test.1180431107
/workspace/coverage/default/7.sysrst_ctrl_pin_override_test.1556595554
/workspace/coverage/default/7.sysrst_ctrl_smoke.388152097
/workspace/coverage/default/7.sysrst_ctrl_stress_all.1971898516
/workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.1465377846
/workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.325904758
/workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.887787535
/workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.368734803
/workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.578678767
/workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.927650994
/workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.3562227499
/workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.3641698044
/workspace/coverage/default/8.sysrst_ctrl_alert_test.2141778349
/workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.1102598848
/workspace/coverage/default/8.sysrst_ctrl_combo_detect.3623763067
/workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.196941899
/workspace/coverage/default/8.sysrst_ctrl_edge_detect.2250013037
/workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.4150702435
/workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.3584459340
/workspace/coverage/default/8.sysrst_ctrl_pin_access_test.964588002
/workspace/coverage/default/8.sysrst_ctrl_pin_override_test.1308888703
/workspace/coverage/default/8.sysrst_ctrl_smoke.376502171
/workspace/coverage/default/8.sysrst_ctrl_stress_all.292043830
/workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.824213598
/workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.3579374347
/workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.2724043897
/workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.1021166655
/workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.2301758486
/workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.3599693112
/workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.400024657
/workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.182411796
/workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.1216151435
/workspace/coverage/default/9.sysrst_ctrl_alert_test.1830315248
/workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.1171651376
/workspace/coverage/default/9.sysrst_ctrl_combo_detect.1482888362
/workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.1911099209
/workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.1077347733
/workspace/coverage/default/9.sysrst_ctrl_edge_detect.2015064515
/workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.3912376100
/workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.1823219197
/workspace/coverage/default/9.sysrst_ctrl_pin_access_test.2438790907
/workspace/coverage/default/9.sysrst_ctrl_pin_override_test.3111174500
/workspace/coverage/default/9.sysrst_ctrl_smoke.3677857134
/workspace/coverage/default/9.sysrst_ctrl_stress_all.3701805220
/workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.4123465988
/workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.3658622715
/workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.1494521043
/workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.3027030953
/workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.3293496857
/workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.323983549
/workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.59886496
/workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.1447905343



Total test records in report: 915
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T6 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.2163672319 Feb 07 12:33:44 PM PST 24 Feb 07 12:33:51 PM PST 24 2012741932 ps
T7 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.2809933129 Feb 07 12:33:41 PM PST 24 Feb 07 12:33:48 PM PST 24 2012874504 ps
T8 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.2876698007 Feb 07 12:33:51 PM PST 24 Feb 07 12:33:59 PM PST 24 2021024790 ps
T1 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.1035519455 Feb 07 12:33:22 PM PST 24 Feb 07 12:33:41 PM PST 24 4025128063 ps
T25 /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.4136889073 Feb 07 12:34:00 PM PST 24 Feb 07 12:34:08 PM PST 24 2009795379 ps
T26 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.1997247499 Feb 07 12:33:28 PM PST 24 Feb 07 12:33:39 PM PST 24 2011744922 ps
T27 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.1700118120 Feb 07 12:33:41 PM PST 24 Feb 07 12:33:45 PM PST 24 2042093311 ps
T28 /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.2029862677 Feb 07 12:34:12 PM PST 24 Feb 07 12:34:16 PM PST 24 2041390741 ps
T29 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.2527341477 Feb 07 12:33:30 PM PST 24 Feb 07 12:33:41 PM PST 24 2079008037 ps
T30 /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.1733151165 Feb 07 12:34:12 PM PST 24 Feb 07 12:34:20 PM PST 24 2011786291 ps
T2 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.730486388 Feb 07 12:33:40 PM PST 24 Feb 07 12:33:45 PM PST 24 2078184803 ps
T3 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.3289839334 Feb 07 12:34:02 PM PST 24 Feb 07 12:34:36 PM PST 24 42888777661 ps
T31 /workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.797458828 Feb 07 12:34:15 PM PST 24 Feb 07 12:34:23 PM PST 24 2010302466 ps
T43 /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.3716132080 Feb 07 12:34:10 PM PST 24 Feb 07 12:34:13 PM PST 24 2086670072 ps
T44 /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.1203770736 Feb 07 12:34:00 PM PST 24 Feb 07 12:34:07 PM PST 24 2012369295 ps
T9 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.3963642225 Feb 07 12:33:42 PM PST 24 Feb 07 12:35:02 PM PST 24 42389565630 ps
T4 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.2855830451 Feb 07 12:33:42 PM PST 24 Feb 07 12:34:06 PM PST 24 4805604002 ps
T45 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.1362286781 Feb 07 12:33:41 PM PST 24 Feb 07 12:33:44 PM PST 24 2039805995 ps
T46 /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.1210284748 Feb 07 12:34:10 PM PST 24 Feb 07 12:34:13 PM PST 24 2048816414 ps
T47 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.703448575 Feb 07 12:34:04 PM PST 24 Feb 07 12:34:09 PM PST 24 2186367259 ps
T10 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.103796633 Feb 07 12:33:39 PM PST 24 Feb 07 12:33:44 PM PST 24 2090317785 ps
T371 /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.1565717306 Feb 07 12:34:09 PM PST 24 Feb 07 12:34:12 PM PST 24 2042806224 ps
T5 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.4070693303 Feb 07 12:33:46 PM PST 24 Feb 07 12:33:52 PM PST 24 5203131888 ps
T67 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.3807643215 Feb 07 12:33:35 PM PST 24 Feb 07 12:34:02 PM PST 24 36238634811 ps
T11 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.1311306553 Feb 07 12:33:40 PM PST 24 Feb 07 12:33:48 PM PST 24 5281654957 ps
T12 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.2814065823 Feb 07 12:33:36 PM PST 24 Feb 07 12:33:41 PM PST 24 2091271912 ps
T68 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.3170180427 Feb 07 12:33:37 PM PST 24 Feb 07 12:33:44 PM PST 24 4024224836 ps
T13 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.3754586653 Feb 07 12:33:53 PM PST 24 Feb 07 12:34:10 PM PST 24 5916525150 ps
T372 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.670100750 Feb 07 12:33:52 PM PST 24 Feb 07 12:33:55 PM PST 24 2027831652 ps
T14 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.3305447515 Feb 07 12:33:30 PM PST 24 Feb 07 12:33:36 PM PST 24 2088937118 ps
T39 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.926824287 Feb 07 12:33:46 PM PST 24 Feb 07 12:33:56 PM PST 24 2507325575 ps
T40 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.2123651114 Feb 07 12:33:44 PM PST 24 Feb 07 12:33:47 PM PST 24 2083088807 ps
T41 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.3299953868 Feb 07 12:33:43 PM PST 24 Feb 07 12:33:49 PM PST 24 5518546343 ps
T373 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.1693612440 Feb 07 12:33:40 PM PST 24 Feb 07 12:33:47 PM PST 24 2011708986 ps
T42 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.3212773439 Feb 07 12:33:46 PM PST 24 Feb 07 12:34:20 PM PST 24 42847762702 ps
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