Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
891 |
1 |
|
|
T36 |
10 |
|
T74 |
8 |
|
T84 |
13 |
| auto[1] |
869 |
1 |
|
|
T36 |
10 |
|
T74 |
12 |
|
T84 |
7 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
878 |
1 |
|
|
T36 |
8 |
|
T74 |
7 |
|
T84 |
15 |
| auto[1] |
882 |
1 |
|
|
T36 |
12 |
|
T74 |
13 |
|
T84 |
5 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
915 |
1 |
|
|
T36 |
9 |
|
T74 |
8 |
|
T84 |
9 |
| auto[1] |
845 |
1 |
|
|
T36 |
11 |
|
T74 |
12 |
|
T84 |
11 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
909 |
1 |
|
|
T36 |
10 |
|
T74 |
13 |
|
T84 |
7 |
| auto[1] |
851 |
1 |
|
|
T36 |
10 |
|
T74 |
7 |
|
T84 |
13 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
882 |
1 |
|
|
T36 |
12 |
|
T74 |
8 |
|
T84 |
9 |
| auto[1] |
878 |
1 |
|
|
T36 |
8 |
|
T74 |
12 |
|
T84 |
11 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
854 |
1 |
|
|
T36 |
9 |
|
T74 |
14 |
|
T84 |
10 |
| auto[1] |
906 |
1 |
|
|
T36 |
11 |
|
T74 |
6 |
|
T84 |
10 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
891 |
1 |
|
|
T36 |
7 |
|
T74 |
10 |
|
T84 |
12 |
| auto[1] |
869 |
1 |
|
|
T36 |
13 |
|
T74 |
10 |
|
T84 |
8 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
901 |
1 |
|
|
T36 |
11 |
|
T74 |
8 |
|
T84 |
4 |
| auto[1] |
859 |
1 |
|
|
T36 |
9 |
|
T74 |
12 |
|
T84 |
16 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
888 |
1 |
|
|
T36 |
7 |
|
T74 |
11 |
|
T84 |
14 |
| auto[1] |
872 |
1 |
|
|
T36 |
13 |
|
T74 |
9 |
|
T84 |
6 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
851 |
1 |
|
|
T36 |
9 |
|
T74 |
11 |
|
T84 |
7 |
| auto[1] |
909 |
1 |
|
|
T36 |
11 |
|
T74 |
9 |
|
T84 |
13 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
893 |
1 |
|
|
T36 |
11 |
|
T74 |
13 |
|
T84 |
12 |
| auto[1] |
867 |
1 |
|
|
T36 |
9 |
|
T74 |
7 |
|
T84 |
8 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
883 |
1 |
|
|
T36 |
10 |
|
T74 |
12 |
|
T84 |
12 |
| auto[1] |
877 |
1 |
|
|
T36 |
10 |
|
T74 |
8 |
|
T84 |
8 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
866 |
1 |
|
|
T36 |
12 |
|
T74 |
12 |
|
T84 |
9 |
| auto[1] |
894 |
1 |
|
|
T36 |
8 |
|
T74 |
8 |
|
T84 |
11 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
878 |
1 |
|
|
T36 |
8 |
|
T74 |
7 |
|
T84 |
15 |
| auto[1] |
882 |
1 |
|
|
T36 |
12 |
|
T74 |
13 |
|
T84 |
5 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
916 |
1 |
|
|
T36 |
15 |
|
T74 |
12 |
|
T84 |
9 |
| auto[1] |
844 |
1 |
|
|
T36 |
5 |
|
T74 |
8 |
|
T84 |
11 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
844 |
1 |
|
|
T36 |
8 |
|
T74 |
11 |
|
T84 |
11 |
| auto[1] |
916 |
1 |
|
|
T36 |
12 |
|
T74 |
9 |
|
T84 |
9 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
885 |
1 |
|
|
T36 |
10 |
|
T74 |
12 |
|
T84 |
9 |
| auto[1] |
875 |
1 |
|
|
T36 |
10 |
|
T74 |
8 |
|
T84 |
11 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
855 |
1 |
|
|
T36 |
7 |
|
T74 |
12 |
|
T84 |
10 |
| auto[1] |
905 |
1 |
|
|
T36 |
13 |
|
T74 |
8 |
|
T84 |
10 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
892 |
1 |
|
|
T36 |
7 |
|
T74 |
10 |
|
T84 |
10 |
| auto[1] |
868 |
1 |
|
|
T36 |
13 |
|
T74 |
10 |
|
T84 |
10 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
866 |
1 |
|
|
T36 |
11 |
|
T74 |
12 |
|
T84 |
12 |
| auto[1] |
894 |
1 |
|
|
T36 |
9 |
|
T74 |
8 |
|
T84 |
8 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
893 |
1 |
|
|
T36 |
11 |
|
T74 |
11 |
|
T84 |
9 |
| auto[1] |
867 |
1 |
|
|
T36 |
9 |
|
T74 |
9 |
|
T84 |
11 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
871 |
1 |
|
|
T36 |
10 |
|
T74 |
11 |
|
T84 |
8 |
| auto[1] |
889 |
1 |
|
|
T36 |
10 |
|
T74 |
9 |
|
T84 |
12 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
875 |
1 |
|
|
T36 |
10 |
|
T74 |
11 |
|
T84 |
13 |
| auto[1] |
885 |
1 |
|
|
T36 |
10 |
|
T74 |
9 |
|
T84 |
7 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
883 |
1 |
|
|
T36 |
10 |
|
T74 |
12 |
|
T84 |
12 |
| auto[1] |
877 |
1 |
|
|
T36 |
10 |
|
T74 |
8 |
|
T84 |
8 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
473 |
1 |
|
|
T36 |
8 |
|
T74 |
5 |
|
T84 |
3 |
| auto[0] |
auto[1] |
443 |
1 |
|
|
T36 |
7 |
|
T74 |
7 |
|
T84 |
6 |
| auto[1] |
auto[0] |
442 |
1 |
|
|
T36 |
1 |
|
T74 |
3 |
|
T84 |
6 |
| auto[1] |
auto[1] |
402 |
1 |
|
|
T36 |
4 |
|
T74 |
5 |
|
T84 |
5 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
434 |
1 |
|
|
T36 |
5 |
|
T74 |
7 |
|
T84 |
3 |
| auto[0] |
auto[1] |
410 |
1 |
|
|
T36 |
3 |
|
T74 |
4 |
|
T84 |
8 |
| auto[1] |
auto[0] |
475 |
1 |
|
|
T36 |
5 |
|
T74 |
6 |
|
T84 |
4 |
| auto[1] |
auto[1] |
441 |
1 |
|
|
T36 |
7 |
|
T74 |
3 |
|
T84 |
5 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
423 |
1 |
|
|
T36 |
5 |
|
T74 |
4 |
|
T84 |
3 |
| auto[0] |
auto[1] |
462 |
1 |
|
|
T36 |
5 |
|
T74 |
8 |
|
T84 |
6 |
| auto[1] |
auto[0] |
459 |
1 |
|
|
T36 |
7 |
|
T74 |
4 |
|
T84 |
6 |
| auto[1] |
auto[1] |
416 |
1 |
|
|
T36 |
3 |
|
T74 |
4 |
|
T84 |
5 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
394 |
1 |
|
|
T36 |
2 |
|
T74 |
7 |
|
T84 |
4 |
| auto[0] |
auto[1] |
461 |
1 |
|
|
T36 |
5 |
|
T74 |
5 |
|
T84 |
6 |
| auto[1] |
auto[0] |
460 |
1 |
|
|
T36 |
7 |
|
T74 |
7 |
|
T84 |
6 |
| auto[1] |
auto[1] |
445 |
1 |
|
|
T36 |
6 |
|
T74 |
1 |
|
T84 |
4 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
474 |
1 |
|
|
T36 |
3 |
|
T74 |
4 |
|
T84 |
6 |
| auto[0] |
auto[1] |
418 |
1 |
|
|
T36 |
4 |
|
T74 |
6 |
|
T84 |
4 |
| auto[1] |
auto[0] |
417 |
1 |
|
|
T36 |
4 |
|
T74 |
6 |
|
T84 |
6 |
| auto[1] |
auto[1] |
451 |
1 |
|
|
T36 |
9 |
|
T74 |
4 |
|
T84 |
4 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
466 |
1 |
|
|
T36 |
7 |
|
T74 |
4 |
|
T84 |
3 |
| auto[0] |
auto[1] |
400 |
1 |
|
|
T36 |
4 |
|
T74 |
8 |
|
T84 |
9 |
| auto[1] |
auto[0] |
435 |
1 |
|
|
T36 |
4 |
|
T74 |
4 |
|
T84 |
1 |
| auto[1] |
auto[1] |
459 |
1 |
|
|
T36 |
5 |
|
T74 |
4 |
|
T84 |
7 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
418 |
1 |
|
|
T36 |
4 |
|
T74 |
6 |
|
T84 |
2 |
| auto[0] |
auto[1] |
453 |
1 |
|
|
T36 |
6 |
|
T74 |
5 |
|
T84 |
6 |
| auto[1] |
auto[0] |
433 |
1 |
|
|
T36 |
5 |
|
T74 |
5 |
|
T84 |
5 |
| auto[1] |
auto[1] |
456 |
1 |
|
|
T36 |
5 |
|
T74 |
4 |
|
T84 |
7 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
441 |
1 |
|
|
T36 |
5 |
|
T74 |
7 |
|
T84 |
7 |
| auto[0] |
auto[1] |
434 |
1 |
|
|
T36 |
5 |
|
T74 |
4 |
|
T84 |
6 |
| auto[1] |
auto[0] |
452 |
1 |
|
|
T36 |
6 |
|
T74 |
6 |
|
T84 |
5 |
| auto[1] |
auto[1] |
433 |
1 |
|
|
T36 |
4 |
|
T74 |
3 |
|
T84 |
2 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
436 |
1 |
|
|
T36 |
5 |
|
T74 |
5 |
|
T84 |
7 |
| auto[0] |
auto[1] |
430 |
1 |
|
|
T36 |
7 |
|
T74 |
7 |
|
T84 |
2 |
| auto[1] |
auto[0] |
455 |
1 |
|
|
T36 |
5 |
|
T74 |
3 |
|
T84 |
6 |
| auto[1] |
auto[1] |
439 |
1 |
|
|
T36 |
3 |
|
T74 |
5 |
|
T84 |
5 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
878 |
1 |
|
|
T36 |
8 |
|
T74 |
7 |
|
T84 |
15 |
| auto[1] |
auto[1] |
882 |
1 |
|
|
T36 |
12 |
|
T74 |
13 |
|
T84 |
5 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
443 |
1 |
|
|
T36 |
4 |
|
T74 |
7 |
|
T84 |
6 |
| auto[0] |
auto[1] |
450 |
1 |
|
|
T36 |
7 |
|
T74 |
4 |
|
T84 |
3 |
| auto[1] |
auto[0] |
445 |
1 |
|
|
T36 |
3 |
|
T74 |
4 |
|
T84 |
8 |
| auto[1] |
auto[1] |
422 |
1 |
|
|
T36 |
6 |
|
T74 |
5 |
|
T84 |
3 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
883 |
1 |
|
|
T36 |
10 |
|
T74 |
12 |
|
T84 |
12 |
| auto[1] |
auto[1] |
877 |
1 |
|
|
T36 |
10 |
|
T74 |
8 |
|
T84 |
8 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
102 |
1 |
|
|
T77 |
7 |
|
T101 |
9 |
|
T79 |
11 |
| auto[1] |
98 |
1 |
|
|
T77 |
13 |
|
T101 |
11 |
|
T79 |
9 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
104 |
1 |
|
|
T77 |
10 |
|
T101 |
12 |
|
T79 |
11 |
| auto[1] |
96 |
1 |
|
|
T77 |
10 |
|
T101 |
8 |
|
T79 |
9 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
99 |
1 |
|
|
T77 |
7 |
|
T101 |
4 |
|
T79 |
11 |
| auto[1] |
101 |
1 |
|
|
T77 |
13 |
|
T101 |
16 |
|
T79 |
9 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
109 |
1 |
|
|
T77 |
10 |
|
T101 |
7 |
|
T79 |
12 |
| auto[1] |
91 |
1 |
|
|
T77 |
10 |
|
T101 |
13 |
|
T79 |
8 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
99 |
1 |
|
|
T77 |
12 |
|
T101 |
8 |
|
T79 |
9 |
| auto[1] |
101 |
1 |
|
|
T77 |
8 |
|
T101 |
12 |
|
T79 |
11 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
90 |
1 |
|
|
T77 |
11 |
|
T101 |
9 |
|
T79 |
10 |
| auto[1] |
110 |
1 |
|
|
T77 |
9 |
|
T101 |
11 |
|
T79 |
10 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
111 |
1 |
|
|
T77 |
9 |
|
T101 |
12 |
|
T79 |
10 |
| auto[1] |
89 |
1 |
|
|
T77 |
11 |
|
T101 |
8 |
|
T79 |
10 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
94 |
1 |
|
|
T77 |
11 |
|
T101 |
7 |
|
T79 |
8 |
| auto[1] |
106 |
1 |
|
|
T77 |
9 |
|
T101 |
13 |
|
T79 |
12 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
104 |
1 |
|
|
T77 |
7 |
|
T101 |
11 |
|
T79 |
5 |
| auto[1] |
96 |
1 |
|
|
T77 |
13 |
|
T101 |
9 |
|
T79 |
15 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
110 |
1 |
|
|
T77 |
9 |
|
T101 |
13 |
|
T79 |
8 |
| auto[1] |
90 |
1 |
|
|
T77 |
11 |
|
T101 |
7 |
|
T79 |
12 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
98 |
1 |
|
|
T77 |
8 |
|
T101 |
8 |
|
T79 |
13 |
| auto[1] |
102 |
1 |
|
|
T77 |
12 |
|
T101 |
12 |
|
T79 |
7 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
97 |
1 |
|
|
T77 |
10 |
|
T101 |
9 |
|
T79 |
10 |
| auto[1] |
103 |
1 |
|
|
T77 |
10 |
|
T101 |
11 |
|
T79 |
10 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
97 |
1 |
|
|
T77 |
12 |
|
T101 |
11 |
|
T79 |
7 |
| auto[1] |
103 |
1 |
|
|
T77 |
8 |
|
T101 |
9 |
|
T79 |
13 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
104 |
1 |
|
|
T77 |
10 |
|
T101 |
12 |
|
T79 |
11 |
| auto[1] |
96 |
1 |
|
|
T77 |
10 |
|
T101 |
8 |
|
T79 |
9 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
103 |
1 |
|
|
T77 |
10 |
|
T101 |
9 |
|
T79 |
14 |
| auto[1] |
97 |
1 |
|
|
T77 |
10 |
|
T101 |
11 |
|
T79 |
6 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
93 |
1 |
|
|
T77 |
11 |
|
T101 |
8 |
|
T79 |
13 |
| auto[1] |
107 |
1 |
|
|
T77 |
9 |
|
T101 |
12 |
|
T79 |
7 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
99 |
1 |
|
|
T77 |
12 |
|
T101 |
9 |
|
T79 |
9 |
| auto[1] |
101 |
1 |
|
|
T77 |
8 |
|
T101 |
11 |
|
T79 |
11 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
108 |
1 |
|
|
T77 |
11 |
|
T101 |
8 |
|
T79 |
8 |
| auto[1] |
92 |
1 |
|
|
T77 |
9 |
|
T101 |
12 |
|
T79 |
12 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
104 |
1 |
|
|
T77 |
11 |
|
T101 |
8 |
|
T79 |
14 |
| auto[1] |
96 |
1 |
|
|
T77 |
9 |
|
T101 |
12 |
|
T79 |
6 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
107 |
1 |
|
|
T77 |
9 |
|
T101 |
9 |
|
T79 |
10 |
| auto[1] |
93 |
1 |
|
|
T77 |
11 |
|
T101 |
11 |
|
T79 |
10 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
101 |
1 |
|
|
T77 |
11 |
|
T101 |
12 |
|
T79 |
10 |
| auto[1] |
99 |
1 |
|
|
T77 |
9 |
|
T101 |
8 |
|
T79 |
10 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
104 |
1 |
|
|
T77 |
7 |
|
T101 |
10 |
|
T79 |
11 |
| auto[1] |
96 |
1 |
|
|
T77 |
13 |
|
T101 |
10 |
|
T79 |
9 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
90 |
1 |
|
|
T77 |
12 |
|
T101 |
7 |
|
T79 |
12 |
| auto[1] |
110 |
1 |
|
|
T77 |
8 |
|
T101 |
13 |
|
T79 |
8 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
97 |
1 |
|
|
T77 |
10 |
|
T101 |
9 |
|
T79 |
10 |
| auto[1] |
103 |
1 |
|
|
T77 |
10 |
|
T101 |
11 |
|
T79 |
10 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
51 |
1 |
|
|
T77 |
2 |
|
T101 |
3 |
|
T79 |
8 |
| auto[0] |
auto[1] |
52 |
1 |
|
|
T77 |
8 |
|
T101 |
6 |
|
T79 |
6 |
| auto[1] |
auto[0] |
48 |
1 |
|
|
T77 |
5 |
|
T101 |
1 |
|
T79 |
3 |
| auto[1] |
auto[1] |
49 |
1 |
|
|
T77 |
5 |
|
T101 |
10 |
|
T79 |
3 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
51 |
1 |
|
|
T77 |
4 |
|
T101 |
4 |
|
T79 |
8 |
| auto[0] |
auto[1] |
42 |
1 |
|
|
T77 |
7 |
|
T101 |
4 |
|
T79 |
5 |
| auto[1] |
auto[0] |
58 |
1 |
|
|
T77 |
6 |
|
T101 |
3 |
|
T79 |
4 |
| auto[1] |
auto[1] |
49 |
1 |
|
|
T77 |
3 |
|
T101 |
9 |
|
T79 |
3 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
46 |
1 |
|
|
T77 |
6 |
|
T101 |
3 |
|
T79 |
5 |
| auto[0] |
auto[1] |
53 |
1 |
|
|
T77 |
6 |
|
T101 |
6 |
|
T79 |
4 |
| auto[1] |
auto[0] |
53 |
1 |
|
|
T77 |
6 |
|
T101 |
5 |
|
T79 |
4 |
| auto[1] |
auto[1] |
48 |
1 |
|
|
T77 |
2 |
|
T101 |
6 |
|
T79 |
7 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
46 |
1 |
|
|
T77 |
5 |
|
T101 |
3 |
|
T79 |
5 |
| auto[0] |
auto[1] |
62 |
1 |
|
|
T77 |
6 |
|
T101 |
5 |
|
T79 |
3 |
| auto[1] |
auto[0] |
44 |
1 |
|
|
T77 |
6 |
|
T101 |
6 |
|
T79 |
5 |
| auto[1] |
auto[1] |
48 |
1 |
|
|
T77 |
3 |
|
T101 |
6 |
|
T79 |
7 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
58 |
1 |
|
|
T77 |
5 |
|
T101 |
7 |
|
T79 |
8 |
| auto[0] |
auto[1] |
46 |
1 |
|
|
T77 |
6 |
|
T101 |
1 |
|
T79 |
6 |
| auto[1] |
auto[0] |
53 |
1 |
|
|
T77 |
4 |
|
T101 |
5 |
|
T79 |
2 |
| auto[1] |
auto[1] |
43 |
1 |
|
|
T77 |
5 |
|
T101 |
7 |
|
T79 |
4 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
51 |
1 |
|
|
T77 |
5 |
|
T101 |
5 |
|
T79 |
5 |
| auto[0] |
auto[1] |
56 |
1 |
|
|
T77 |
4 |
|
T101 |
4 |
|
T79 |
5 |
| auto[1] |
auto[0] |
43 |
1 |
|
|
T77 |
6 |
|
T101 |
2 |
|
T79 |
3 |
| auto[1] |
auto[1] |
50 |
1 |
|
|
T77 |
5 |
|
T101 |
9 |
|
T79 |
7 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
56 |
1 |
|
|
T77 |
3 |
|
T101 |
7 |
|
T79 |
6 |
| auto[0] |
auto[1] |
48 |
1 |
|
|
T77 |
4 |
|
T101 |
3 |
|
T79 |
5 |
| auto[1] |
auto[0] |
54 |
1 |
|
|
T77 |
6 |
|
T101 |
6 |
|
T79 |
2 |
| auto[1] |
auto[1] |
42 |
1 |
|
|
T77 |
7 |
|
T101 |
4 |
|
T79 |
7 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
43 |
1 |
|
|
T77 |
5 |
|
T101 |
3 |
|
T79 |
9 |
| auto[0] |
auto[1] |
47 |
1 |
|
|
T77 |
7 |
|
T101 |
4 |
|
T79 |
3 |
| auto[1] |
auto[0] |
55 |
1 |
|
|
T77 |
3 |
|
T101 |
5 |
|
T79 |
4 |
| auto[1] |
auto[1] |
55 |
1 |
|
|
T77 |
5 |
|
T101 |
8 |
|
T79 |
4 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
48 |
1 |
|
|
T77 |
3 |
|
T101 |
6 |
|
T79 |
5 |
| auto[0] |
auto[1] |
49 |
1 |
|
|
T77 |
9 |
|
T101 |
5 |
|
T79 |
2 |
| auto[1] |
auto[0] |
54 |
1 |
|
|
T77 |
4 |
|
T101 |
3 |
|
T79 |
6 |
| auto[1] |
auto[1] |
49 |
1 |
|
|
T77 |
4 |
|
T101 |
6 |
|
T79 |
7 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
104 |
1 |
|
|
T77 |
10 |
|
T101 |
12 |
|
T79 |
11 |
| auto[1] |
auto[1] |
96 |
1 |
|
|
T77 |
10 |
|
T101 |
8 |
|
T79 |
9 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
46 |
1 |
|
|
T77 |
5 |
|
T101 |
4 |
|
T79 |
1 |
| auto[0] |
auto[1] |
55 |
1 |
|
|
T77 |
6 |
|
T101 |
8 |
|
T79 |
9 |
| auto[1] |
auto[0] |
58 |
1 |
|
|
T77 |
2 |
|
T101 |
7 |
|
T79 |
4 |
| auto[1] |
auto[1] |
41 |
1 |
|
|
T77 |
7 |
|
T101 |
1 |
|
T79 |
6 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
97 |
1 |
|
|
T77 |
10 |
|
T101 |
9 |
|
T79 |
10 |
| auto[1] |
auto[1] |
103 |
1 |
|
|
T77 |
10 |
|
T101 |
11 |
|
T79 |
10 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
51 |
1 |
|
|
T77 |
7 |
|
T101 |
12 |
|
T91 |
10 |
| auto[1] |
49 |
1 |
|
|
T77 |
13 |
|
T101 |
8 |
|
T91 |
10 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
56 |
1 |
|
|
T77 |
13 |
|
T101 |
12 |
|
T91 |
12 |
| auto[1] |
44 |
1 |
|
|
T77 |
7 |
|
T101 |
8 |
|
T91 |
8 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
53 |
1 |
|
|
T77 |
11 |
|
T101 |
9 |
|
T91 |
11 |
| auto[1] |
47 |
1 |
|
|
T77 |
9 |
|
T101 |
11 |
|
T91 |
9 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
45 |
1 |
|
|
T77 |
14 |
|
T101 |
10 |
|
T91 |
6 |
| auto[1] |
55 |
1 |
|
|
T77 |
6 |
|
T101 |
10 |
|
T91 |
14 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
40 |
1 |
|
|
T77 |
9 |
|
T101 |
8 |
|
T91 |
7 |
| auto[1] |
60 |
1 |
|
|
T77 |
11 |
|
T101 |
12 |
|
T91 |
13 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
56 |
1 |
|
|
T77 |
11 |
|
T101 |
12 |
|
T91 |
11 |
| auto[1] |
44 |
1 |
|
|
T77 |
9 |
|
T101 |
8 |
|
T91 |
9 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
62 |
1 |
|
|
T77 |
8 |
|
T101 |
13 |
|
T91 |
13 |
| auto[1] |
38 |
1 |
|
|
T77 |
12 |
|
T101 |
7 |
|
T91 |
7 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
54 |
1 |
|
|
T77 |
10 |
|
T101 |
10 |
|
T91 |
10 |
| auto[1] |
46 |
1 |
|
|
T77 |
10 |
|
T101 |
10 |
|
T91 |
10 |