Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.12	95.12	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	95.12	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.12	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	4	58	93.55

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	4	27	87.10	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1819

1

T5

5

T3

4

T4

3

auto[1]

700

1

T5

4

T3

8

T4

8

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1972

1

T3

12

T4

8

T48

58

auto[1]

547

1

T5

9

T4

3

T48

26

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1959

1

T5

4

T4

6

T48

84

auto[1]

560

1

T5

5

T3

12

T4

5

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1916

1

T3

7

T4

11

T48

37

auto[1]

603

1

T5

9

T3

5

T48

47

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2349

1

T5

9

T3

12

T4

11

auto[1]

170

1

T48

40

T6

3

T13

1

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2253

1

T5

9

T3

12

T4

11

auto[1]

266

1

T48

31

T6

7

T68

6

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2252

1

T5

9

T3

12

T4

11

auto[1]

267

1

T48

30

T17

10

T263

1

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2328

1

T5

9

T3

12

T4

11

auto[1]

191

1

T6

10

T56

1

T17

5

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2267

1

T5

9

T3

12

T4

11

auto[1]

252

1

T48

10

T6

16

T13

7

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1956

1

T5

4

T3

8

T4

8

auto[1]

563

1

T5

5

T3

4

T4

3

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	4	27	87.10	4
Automatically Generated Cross Bins	31	4	27	87.10	4
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	854	1			T5	5		T3	12		T4	11
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	24	1			T352	3		T367	1		T368	4
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	120	1			T6	13		T13	6		T266	8
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	18	1			T48	5		T13	1		T369	6
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	49	1			T56	1		T68	7		T263	3
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	1	1			T370	1		-	-		-	-
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	15	1			T68	5		T264	2		T170	2
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	6	1			T6	3		T369	2		T371	1
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	55	1			T17	5		T263	1		T372	2
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	30	1			T48	6		T264	5		T267	1
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	20	1			T265	1		T267	1		T240	9
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	45	1			T17	3		T153	8		T373	3
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	6	1			T17	2		T264	2		T374	2
auto[0]	auto[1]	auto[1]	auto[1]	auto[1]	1	1			T362	1		-	-		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	71	1			T48	8		T350	1		T368	26
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	18	1			T265	5		T375	3		T126	3
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	20	1			T68	6		T127	4		T376	1
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	4	1			T241	2		T377	2		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	22	1			T6	7		T263	2		T77	3
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	1	1			T264	1		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	8	1			T361	3		T378	1		T374	4
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	42	1			T153	4		T240	22		T243	6
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	7	1			T48	5		T355	2		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	4	1			T369	1		T355	1		T379	1
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	7	1			T240	7		-	-		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[1]	6	1			T362	2		T368	4		-	-
auto[1]	auto[1]	auto[1]	auto[1]	auto[0]	2	1			T380	2		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

159

1

T4

6

T13

6

T17

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

87

1

T264

1

T345

7

T105

7

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

65

1

T347

12

T170

7

T89

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

128

1

T48

13

T12

7

T17

5

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

69

1

T279

6

T381

12

T367

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

63

1

T98

7

T277

3

T279

8

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

30

1

T269

1

T346

2

T372

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

115

1

T6

20

T49

12

T68

6

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

72

1

T3

4

T4

2

T187

7

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

55

1

T276

7

T175

7

T304

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

32

1

T3

3

T345

1

T346

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

44

1

T3

4

T344

5

T350

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

32

1

T12

1

T50

2

T278

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

13

1

T49

2

T50

4

T349

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

2

1

T3

1

T382

1

-

-

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

84

1

T48

5

T98

14

T369

8

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

70

1

T265

1

T170

3

T373

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

40

1

T17

2

T264

2

T200

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

36

1

T346

5

T279

2

T348

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

40

1

T264

5

T380

4

T124

8

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

31

1

T82

1

T267

1

T153

6

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

16

1

T48

6

T304

1

T383

5

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

29

1

T5

4

T276

3

T101

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

49

1

T6

3

T13

1

T68

7

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

22

1

T12

1

T49

4

T68

5

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

29

1

T4

3

T98

6

T263

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

6

1

T56

1

T276

1

T176

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

9

1

T344

1

T360

1

T367

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

12

1

T187

3

T266

4

T107

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

15

1

T5

1

T344

1

T346

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

2

1

T49

1

T384

1

-

-

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded