Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1084

1

T1

11

T25

10

T8

18

auto[1]

1116

1

T1

9

T25

10

T8

22

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

516

1

T1

4

T25

3

T8

9

from_0to1

512

1

T1

5

T25

3

T8

10

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1129

1

T1

12

T25

12

T8

18

auto[1]

1071

1

T1

8

T25

8

T8

22

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1033

1

T1

9

T25

11

T8

17

auto[1]

1167

1

T1

11

T25

9

T8

23

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

61

1

T1

1

T8

1

T64

1

auto[0]

from_1to0

auto[0]

auto[1]

65

1

T1

1

T8

1

T66

1

auto[0]

from_1to0

auto[1]

auto[0]

63

1

T8

1

T64

2

T18

2

auto[0]

from_1to0

auto[1]

auto[1]

69

1

T8

1

T18

1

T136

1

auto[0]

from_0to1

auto[0]

auto[0]

59

1

T1

1

T25

1

T8

1

auto[0]

from_0to1

auto[0]

auto[1]

73

1

T1

2

T18

2

T19

2

auto[0]

from_0to1

auto[1]

auto[0]

54

1

T25

1

T8

1

T64

1

auto[0]

from_0to1

auto[1]

auto[1]

68

1

T1

1

T8

2

T66

1

auto[1]

from_1to0

auto[0]

auto[0]

58

1

T274

2

T120

1

T220

1

auto[1]

from_1to0

auto[0]

auto[1]

79

1

T1

2

T25

3

T8

2

auto[1]

from_1to0

auto[1]

auto[0]

64

1

T8

2

T66

1

T19

1

auto[1]

from_1to0

auto[1]

auto[1]

57

1

T8

1

T136

1

T49

1

auto[1]

from_0to1

auto[0]

auto[0]

76

1

T8

2

T66

1

T18

1

auto[1]

from_0to1

auto[0]

auto[1]

61

1

T8

4

T64

1

T19

1

auto[1]

from_0to1

auto[1]

auto[0]

52

1

T1

1

T18

2

T49

1

auto[1]

from_0to1

auto[1]

auto[1]

69

1

T25

1

T64

2

T274

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1093

1

T1

9

T25

9

T8

20

auto[1]

1107

1

T1

11

T25

11

T8

20

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

530

1

T1

6

T25

5

T8

10

from_0to1

525

1

T1

6

T25

5

T8

9

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1089

1

T1

13

T25

11

T8

20

auto[1]

1111

1

T1

7

T25

9

T8

20

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1125

1

T1

7

T25

13

T8

24

auto[1]

1075

1

T1

13

T25

7

T8

16

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

58

1

T1

1

T8

1

T64

1

auto[0]

from_1to0

auto[0]

auto[1]

66

1

T25

1

T66

1

T18

1

auto[0]

from_1to0

auto[1]

auto[0]

67

1

T1

1

T25

1

T8

2

auto[0]

from_1to0

auto[1]

auto[1]

74

1

T8

1

T64

2

T18

1

auto[0]

from_0to1

auto[0]

auto[0]

64

1

T1

1

T8

1

T64

1

auto[0]

from_0to1

auto[0]

auto[1]

65

1

T1

1

T8

3

T18

1

auto[0]

from_0to1

auto[1]

auto[0]

68

1

T25

3

T8

1

T66

1

auto[0]

from_0to1

auto[1]

auto[1]

66

1

T1

1

T8

1

T136

1

auto[1]

from_1to0

auto[0]

auto[0]

65

1

T1

1

T25

2

T8

1

auto[1]

from_1to0

auto[0]

auto[1]

57

1

T1

2

T25

1

T8

1

auto[1]

from_1to0

auto[1]

auto[0]

75

1

T1

1

T8

2

T18

1

auto[1]

from_1to0

auto[1]

auto[1]

68

1

T8

2

T64

1

T66

1

auto[1]

from_0to1

auto[0]

auto[0]

71

1

T25

2

T8

2

T19

1

auto[1]

from_0to1

auto[0]

auto[1]

64

1

T1

1

T8

1

T64

2

auto[1]

from_0to1

auto[1]

auto[0]

60

1

T64

1

T66

1

T18

1

auto[1]

from_0to1

auto[1]

auto[1]

67

1

T1

2

T64

2

T66

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1094

1

T1

10

T25

9

T8

16

auto[1]

1106

1

T1

10

T25

11

T8

24

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

531

1

T1

6

T25

6

T8

11

from_0to1

529

1

T1

5

T25

7

T8

12

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1175

1

T1

12

T25

9

T8

17

auto[1]

1025

1

T1

8

T25

11

T8

23

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1138

1

T1

9

T25

7

T8

21

auto[1]

1062

1

T1

11

T25

13

T8

19

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

73

1

T1

1

T66

1

T19

2

auto[0]

from_1to0

auto[0]

auto[1]

66

1

T8

1

T64

1

T18

1

auto[0]

from_1to0

auto[1]

auto[0]

68

1

T1

1

T8

3

T19

1

auto[0]

from_1to0

auto[1]

auto[1]

61

1

T25

1

T8

1

T64

1

auto[0]

from_0to1

auto[0]

auto[0]

80

1

T25

1

T64

1

T66

1

auto[0]

from_0to1

auto[0]

auto[1]

87

1

T1

1

T25

1

T8

1

auto[0]

from_0to1

auto[1]

auto[0]

60

1

T1

2

T8

1

T64

1

auto[0]

from_0to1

auto[1]

auto[1]

50

1

T25

1

T8

1

T64

1

auto[1]

from_1to0

auto[0]

auto[0]

76

1

T1

1

T25

1

T8

2

auto[1]

from_1to0

auto[0]

auto[1]

65

1

T1

2

T25

1

T8

1

auto[1]

from_1to0

auto[1]

auto[0]

66

1

T25

1

T8

2

T64

2

auto[1]

from_1to0

auto[1]

auto[1]

56

1

T1

1

T25

2

T8

1

auto[1]

from_0to1

auto[0]

auto[0]

67

1

T25

1

T8

3

T66

1

auto[1]

from_0to1

auto[0]

auto[1]

53

1

T8

1

T66

1

T136

1

auto[1]

from_0to1

auto[1]

auto[0]

67

1

T8

3

T66

1

T19

1

auto[1]

from_0to1

auto[1]

auto[1]

65

1

T1

2

T25

3

T8

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1124

1

T1

9

T25

11

T8

27

auto[1]

1076

1

T1

11

T25

9

T8

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

545

1

T1

5

T25

5

T8

11

from_0to1

550

1

T1

5

T25

5

T8

11

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1143

1

T1

6

T25

10

T8

18

auto[1]

1057

1

T1

14

T25

10

T8

22

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1120

1

T1

13

T25

9

T8

17

auto[1]

1080

1

T1

7

T25

11

T8

23

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

75

1

T1

1

T64

2

T120

2

auto[0]

from_1to0

auto[0]

auto[1]

71

1

T66

2

T18

1

T19

1

auto[0]

from_1to0

auto[1]

auto[0]

66

1

T25

2

T8

2

T64

1

auto[0]

from_1to0

auto[1]

auto[1]

66

1

T25

1

T8

4

T18

1

auto[0]

from_0to1

auto[0]

auto[0]

74

1

T1

1

T8

2

T66

1

auto[0]

from_0to1

auto[0]

auto[1]

72

1

T25

2

T8

4

T136

1

auto[0]

from_0to1

auto[1]

auto[0]

67

1

T25

1

T8

1

T64

2

auto[0]

from_0to1

auto[1]

auto[1]

73

1

T1

2

T8

2

T66

1

auto[1]

from_1to0

auto[0]

auto[0]

70

1

T1

2

T8

1

T64

2

auto[1]

from_1to0

auto[0]

auto[1]

78

1

T25

2

T8

1

T64

1

auto[1]

from_1to0

auto[1]

auto[0]

57

1

T1

2

T8

2

T219

1

auto[1]

from_1to0

auto[1]

auto[1]

62

1

T8

1

T136

2

T49

1

auto[1]

from_0to1

auto[0]

auto[0]

68

1

T1

1

T64

1

T18

2

auto[1]

from_0to1

auto[0]

auto[1]

70

1

T1

1

T25

1

T8

1

auto[1]

from_0to1

auto[1]

auto[0]

65

1

T25

1

T8

1

T64

2

auto[1]

from_0to1

auto[1]

auto[1]

61

1

T66

2

T274

1

T120

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1060

1

T1

8

T25

12

T8

24

auto[1]

1140

1

T1

12

T25

8

T8

16

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

530

1

T1

6

T25

4

T8

12

from_0to1

535

1

T1

5

T25

4

T8

11

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1084

1

T1

9

T25

9

T8

13

auto[1]

1116

1

T1

11

T25

11

T8

27

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1097

1

T1

8

T25

12

T8

15

auto[1]

1103

1

T1

12

T25

8

T8

25

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

60

1

T25

2

T8

2

T19

2

auto[0]

from_1to0

auto[0]

auto[1]

66

1

T66

2

T18

1

T49

2

auto[0]

from_1to0

auto[1]

auto[0]

67

1

T1

1

T8

1

T64

1

auto[0]

from_1to0

auto[1]

auto[1]

64

1

T1

1

T25

1

T8

3

auto[0]

from_0to1

auto[0]

auto[0]

62

1

T1

1

T25

2

T18

1

auto[0]

from_0to1

auto[0]

auto[1]

71

1

T25

1

T8

2

T19

3

auto[0]

from_0to1

auto[1]

auto[0]

67

1

T8

1

T64

1

T66

1

auto[0]

from_0to1

auto[1]

auto[1]

49

1

T1

1

T8

3

T64

2

auto[1]

from_1to0

auto[0]

auto[0]

66

1

T1

1

T25

1

T8

1

auto[1]

from_1to0

auto[0]

auto[1]

72

1

T1

2

T8

2

T64

2

auto[1]

from_1to0

auto[1]

auto[0]

67

1

T1

1

T8

2

T18

2

auto[1]

from_1to0

auto[1]

auto[1]

68

1

T8

1

T274

1

T120

1

auto[1]

from_0to1

auto[0]

auto[0]

77

1

T25

1

T8

1

T66

1

auto[1]

from_0to1

auto[0]

auto[1]

71

1

T8

1

T19

1

T136

1

auto[1]

from_0to1

auto[1]

auto[0]

75

1

T1

1

T18

1

T136

1

auto[1]

from_0to1

auto[1]

auto[1]

63

1

T1

2

T8

3

T49

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1108

1

T1

12

T25

9

T8

26

auto[1]

1092

1

T1

8

T25

11

T8

14

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

535

1

T1

5

T25

5

T8

7

from_0to1

546

1

T1

5

T25

4

T8

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1061

1

T1

11

T25

11

T8

20

auto[1]

1139

1

T1

9

T25

9

T8

20

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1163

1

T1

9

T25

9

T8

25

auto[1]

1037

1

T1

11

T25

11

T8

15

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

69

1

T1

2

T8

1

T49

1

auto[0]

from_1to0

auto[0]

auto[1]

65

1

T1

1

T25

1

T8

1

auto[0]

from_1to0

auto[1]

auto[0]

62

1

T25

2

T136

1

T49

1

auto[0]

from_1to0

auto[1]

auto[1]

64

1

T8

1

T64

2

T66

1

auto[0]

from_0to1

auto[0]

auto[0]

61

1

T1

1

T8

2

T64

2

auto[0]

from_0to1

auto[0]

auto[1]

64

1

T25

1

T8

1

T66

1

auto[0]

from_0to1

auto[1]

auto[0]

74

1

T8

2

T64

1

T66

1

auto[0]

from_0to1

auto[1]

auto[1]

61

1

T1

2

T8

2

T136

1

auto[1]

from_1to0

auto[0]

auto[0]

63

1

T1

1

T8

3

T66

1

auto[1]

from_1to0

auto[0]

auto[1]

70

1

T25

1

T64

2

T18

1

auto[1]

from_1to0

auto[1]

auto[0]

79

1

T1

1

T25

1

T8

1

auto[1]

from_1to0

auto[1]

auto[1]

63

1

T64

2

T66

3

T18

1

auto[1]

from_0to1

auto[0]

auto[0]

74

1

T18

1

T19

2

T136

2

auto[1]

from_0to1

auto[0]

auto[1]

63

1

T1

2

T64

2

T66

2

auto[1]

from_0to1

auto[1]

auto[0]

73

1

T25

1

T64

1

T18

2

auto[1]

from_0to1

auto[1]

auto[1]

76

1

T25

2

T64

1

T18

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1110

1

T1

16

T25

13

T8

19

auto[1]

1090

1

T1

4

T25

7

T8

21

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

517

1

T1

6

T25

4

T8

10

from_0to1

520

1

T1

6

T25

4

T8

10

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1071

1

T1

9

T25

12

T8

14

auto[1]

1129

1

T1

11

T25

8

T8

26

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1121

1

T1

10

T25

8

T8

20

auto[1]

1079

1

T1

10

T25

12

T8

20

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

59

1

T8

1

T18

1

T120

1

auto[0]

from_1to0

auto[0]

auto[1]

57

1

T1

1

T25

1

T64

2

auto[0]

from_1to0

auto[1]

auto[0]

71

1

T1

1

T8

1

T66

1

auto[0]

from_1to0

auto[1]

auto[1]

62

1

T1

2

T25

1

T8

2

auto[0]

from_0to1

auto[0]

auto[0]

62

1

T25

1

T8

1

T64

2

auto[0]

from_0to1

auto[0]

auto[1]

66

1

T1

1

T8

1

T136

1

auto[0]

from_0to1

auto[1]

auto[0]

61

1

T1

1

T25

1

T8

1

auto[0]

from_0to1

auto[1]

auto[1]

69

1

T1

2

T25

1

T8

1

auto[1]

from_1to0

auto[0]

auto[0]

64

1

T1

1

T8

1

T66

1

auto[1]

from_1to0

auto[0]

auto[1]

60

1

T25

2

T18

1

T19

2

auto[1]

from_1to0

auto[1]

auto[0]

76

1

T1

1

T8

4

T64

1

auto[1]

from_1to0

auto[1]

auto[1]

68

1

T8

1

T64

1

T66

1

auto[1]

from_0to1

auto[0]

auto[0]

62

1

T1

1

T25

1

T8

2

auto[1]

from_0to1

auto[0]

auto[1]

63

1

T1

1

T8

1

T64

1

auto[1]

from_0to1

auto[1]

auto[0]

69

1

T8

1

T66

1

T18

2

auto[1]

from_0to1

auto[1]

auto[1]

68

1

T8

2

T18

1

T49

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1097

1

T1

13

T25

11

T8

18

auto[1]

1103

1

T1

7

T25

9

T8

22

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

508

1

T1

6

T25

5

T8

6

from_0to1

520

1

T1

5

T25

6

T8

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1096

1

T1

12

T25

11

T8

25

auto[1]

1104

1

T1

8

T25

9

T8

15

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1068

1

T1

11

T25

9

T8

20

auto[1]

1132

1

T1

9

T25

11

T8

20

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

52

1

T1

1

T120

1

T182

1

auto[0]

from_1to0

auto[0]

auto[1]

80

1

T1

2

T8

1

T64

1

auto[0]

from_1to0

auto[1]

auto[0]

72

1

T1

1

T25

1

T8

2

auto[0]

from_1to0

auto[1]

auto[1]

69

1

T1

1

T25

1

T66

1

auto[0]

from_0to1

auto[0]

auto[0]

60

1

T1

2

T8

3

T64

1

auto[0]

from_0to1

auto[0]

auto[1]

57

1

T8

1

T18

1

T19

1

auto[0]

from_0to1

auto[1]

auto[0]

63

1

T1

1

T66

1

T136

1

auto[0]

from_0to1

auto[1]

auto[1]

75

1

T25

2

T8

1

T64

2

auto[1]

from_1to0

auto[0]

auto[0]

65

1

T1

1

T25

1

T8

2

auto[1]

from_1to0

auto[0]

auto[1]

55

1

T25

1

T66

1

T19

1

auto[1]

from_1to0

auto[1]

auto[0]

55

1

T8

1

T64

2

T66

1

auto[1]

from_1to0

auto[1]

auto[1]

60

1

T25

1

T18

1

T136

1

auto[1]

from_0to1

auto[0]

auto[0]

63

1

T25

2

T8

2

T66

1

auto[1]

from_0to1

auto[0]

auto[1]

60

1

T1

1

T25

1

T136

1

auto[1]

from_0to1

auto[1]

auto[0]

72

1

T1

1

T25

1

T18

1

auto[1]

from_0to1

auto[1]

auto[1]

70

1

T66

1

T18

2

T19

2