Group : sysrst_ctrl_env_pkg::sysrst_ctrl_wakeup_event_obj::sysrst_ctrl_wkup_event_cg
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Group : sysrst_ctrl_env_pkg::sysrst_ctrl_wakeup_event_obj::sysrst_ctrl_wkup_event_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
57.58 57.58 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
sysrst_ctrl_wkup_event_cg 57.58 1 100 1 64 64




Group Instance : sysrst_ctrl_wkup_event_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
57.58 1 100 1 64 64




Summary for Group Instance sysrst_ctrl_wkup_event_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 23 14 9 39.13


Variables for Group Instance sysrst_ctrl_wkup_event_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_h2l_pwrb 2 0 2 100.00 100 1 1 2
cp_h_ac_present 2 0 2 100.00 100 1 1 2
cp_interrupt_gen 2 0 2 100.00 100 1 1 2
cp_l2h_lid_open 2 0 2 100.00 100 1 1 2
cp_wakeup_sts 2 0 2 100.00 100 1 1 2


Crosses for Group Instance sysrst_ctrl_wkup_event_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cross_wkup_sts 23 14 9 39.13 100 1 1 0


Summary for Variable cp_h2l_pwrb

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_h2l_pwrb

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 932 1 T1 9 T24 3 T46 4
auto[1] 785 1 T1 12 T24 1 T25 1



Summary for Variable cp_h_ac_present

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_h_ac_present

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1003 1 T1 11 T24 3 T46 5
auto[1] 714 1 T1 10 T24 1 T25 1



Summary for Variable cp_interrupt_gen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_interrupt_gen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1655 1 T1 21 T24 4 T25 1
auto[1] 62 1 T18 2 T22 3 T36 1



Summary for Variable cp_l2h_lid_open

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_l2h_lid_open

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1007 1 T1 13 T24 3 T46 2
auto[1] 710 1 T1 8 T24 1 T25 1



Summary for Variable cp_wakeup_sts

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_wakeup_sts

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1637 1 T1 21 T24 4 T25 1
auto[1] 80 1 T7 1 T18 3 T19 1



Summary for Cross cross_wkup_sts

Samples crossed: cp_wakeup_sts cp_h2l_pwrb cp_l2h_lid_open cp_h_ac_present cp_interrupt_gen
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 23 14 9 39.13 14
Automatically Generated Cross Bins 23 14 9 39.13 14
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cross_wkup_sts

Element holes
cp_wakeup_stscp_h2l_pwrbcp_l2h_lid_opencp_h_ac_presentcp_interrupt_genCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [auto[0]] * * * -- -- 8
[auto[1]] [auto[1]] [auto[0]] [auto[1]] * -- -- 2
[auto[1]] [auto[1]] [auto[1]] * * -- -- 4


Covered bins
cp_wakeup_stscp_h2l_pwrbcp_l2h_lid_opencp_h_ac_presentcp_interrupt_genCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 364 1 T1 3 T24 2 T61 1
auto[0] auto[0] auto[0] auto[1] auto[0] 174 1 T1 4 T24 1 T61 1
auto[0] auto[0] auto[1] auto[0] auto[0] 181 1 T1 1 T46 3 T30 2
auto[0] auto[0] auto[1] auto[1] auto[0] 199 1 T1 1 T46 1 T61 1
auto[0] auto[1] auto[0] auto[0] auto[0] 219 1 T1 4 T46 2 T61 1
auto[0] auto[1] auto[0] auto[1] auto[0] 159 1 T1 2 T7 1 T8 2
auto[0] auto[1] auto[1] auto[0] auto[0] 153 1 T1 3 T24 1 T8 3
auto[0] auto[1] auto[1] auto[1] auto[0] 167 1 T1 3 T25 1 T61 1
auto[1] auto[1] auto[0] auto[0] auto[1] 41 1 T18 2 T22 2 T36 1


User Defined Cross Bins for cross_wkup_sts

Excluded/Illegal bins
NAMECOUNTSTATUS
invalid0 0 Excluded
invalid1 0 Excluded

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