Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	163056	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

132394

1

T5

249

T1

210

T2

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	151509	1			T5	387		T1	273		T2	15
values[0x0]	70895	1			T5	32		T1	85		T2	4
values[0x1]	73046	1			T5	43		T1	71		T2	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	131350	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

164100

1

T5

307

T1

251

T2

12

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1074	1			T3	4		T27	3		T48	8
valid_sources[0x01]	1205	1			T23	1		T3	4		T27	2
valid_sources[0x02]	1502	1			T1	2		T23	1		T3	2
valid_sources[0x03]	1138	1			T3	1		T27	5		T48	17
valid_sources[0x04]	883	1			T3	1		T4	1		T27	1
valid_sources[0x05]	1378	1			T1	11		T3	2		T4	2
valid_sources[0x06]	858	1			T1	28		T3	2		T4	4
valid_sources[0x07]	1095	1			T4	5		T27	4		T48	19
valid_sources[0x08]	1536	1			T26	1		T27	5		T8	7
valid_sources[0x09]	1158	1			T1	10		T3	12		T4	3
valid_sources[0x0a]	961	1			T1	8		T24	1		T4	3
valid_sources[0x0b]	1900	1			T24	1		T27	4		T56	3
valid_sources[0x0c]	1012	1			T23	1		T4	2		T27	6
valid_sources[0x0d]	965	1			T1	4		T4	1		T27	1
valid_sources[0x0e]	1036	1			T3	4		T4	2		T27	4
valid_sources[0x0f]	996	1			T4	1		T27	3		T48	8
valid_sources[0x10]	1051	1			T4	1		T27	4		T29	32
valid_sources[0x11]	1109	1			T3	5		T4	2		T27	1
valid_sources[0x12]	1229	1			T4	2		T27	1		T48	5
valid_sources[0x13]	933	1			T3	6		T24	3		T27	5
valid_sources[0x14]	1814	1			T27	4		T48	5		T56	6
valid_sources[0x15]	1068	1			T1	14		T3	1		T4	2
valid_sources[0x16]	831	1			T3	1		T4	2		T27	1
valid_sources[0x17]	1012	1			T3	1		T4	3		T27	4
valid_sources[0x18]	1050	1			T1	5		T4	1		T27	6
valid_sources[0x19]	1037	1			T1	1		T4	1		T27	2
valid_sources[0x1a]	1032	1			T3	3		T24	4		T4	1
valid_sources[0x1b]	1115	1			T23	1		T4	2		T27	4
valid_sources[0x1c]	999	1			T1	5		T3	1		T27	3
valid_sources[0x1d]	1218	1			T23	1		T3	1		T27	2
valid_sources[0x1e]	1018	1			T3	1		T4	9		T27	7
valid_sources[0x1f]	955	1			T1	5		T3	2		T4	1
valid_sources[0x20]	1628	1			T3	4		T4	2		T27	4
valid_sources[0x21]	925	1			T4	2		T27	2		T48	6
valid_sources[0x22]	1077	1			T1	1		T3	1		T24	1
valid_sources[0x23]	1131	1			T3	3		T4	2		T27	2
valid_sources[0x24]	830	1			T3	3		T4	2		T27	3
valid_sources[0x25]	982	1			T3	2		T4	1		T27	2
valid_sources[0x26]	995	1			T3	1		T27	1		T48	12
valid_sources[0x27]	2000	1			T24	2		T4	4		T27	4
valid_sources[0x28]	936	1			T1	9		T3	3		T27	3
valid_sources[0x29]	1473	1			T1	2		T3	2		T27	2
valid_sources[0x2a]	1241	1			T4	1		T27	2		T56	3
valid_sources[0x2b]	944	1			T4	2		T27	2		T48	4
valid_sources[0x2c]	1286	1			T27	5		T48	1		T56	7
valid_sources[0x2d]	1194	1			T3	1		T4	2		T27	4
valid_sources[0x2e]	1031	1			T4	1		T27	4		T48	1
valid_sources[0x2f]	1090	1			T4	3		T27	2		T48	8
valid_sources[0x30]	970	1			T1	2		T3	2		T4	1
valid_sources[0x31]	954	1			T3	7		T4	2		T48	1
valid_sources[0x32]	864	1			T3	2		T4	2		T27	4
valid_sources[0x33]	967	1			T1	1		T3	5		T24	2
valid_sources[0x34]	920	1			T3	1		T4	1		T27	3
valid_sources[0x35]	2140	1			T3	1		T4	2		T27	5
valid_sources[0x36]	1257	1			T4	5		T27	7		T48	9
valid_sources[0x37]	1094	1			T27	5		T48	8		T8	3
valid_sources[0x38]	1024	1			T3	1		T4	2		T27	3
valid_sources[0x39]	940	1			T1	1		T3	1		T4	2
valid_sources[0x3a]	993	1			T1	1		T27	3		T48	5
valid_sources[0x3b]	1077	1			T4	2		T27	9		T48	4
valid_sources[0x3c]	989	1			T3	2		T27	2		T48	15
valid_sources[0x3d]	1005	1			T4	4		T48	6		T56	2
valid_sources[0x3e]	938	1			T1	2		T24	1		T4	1
valid_sources[0x3f]	1191	1			T23	1		T3	2		T4	1
valid_sources[0x40]	941	1			T3	2		T4	1		T27	4
valid_sources[0x41]	1147	1			T1	9		T3	1		T27	3
valid_sources[0x42]	948	1			T3	4		T4	1		T27	3
valid_sources[0x43]	935	1			T3	3		T4	3		T27	1
valid_sources[0x44]	1061	1			T3	2		T4	4		T27	3
valid_sources[0x45]	1195	1			T3	3		T4	6		T27	1
valid_sources[0x46]	1101	1			T4	1		T27	3		T48	8
valid_sources[0x47]	861	1			T3	2		T4	3		T27	3
valid_sources[0x48]	1131	1			T4	2		T27	6		T56	8
valid_sources[0x49]	1020	1			T3	5		T24	1		T27	8
valid_sources[0x4a]	1106	1			T3	4		T4	1		T27	2
valid_sources[0x4b]	1096	1			T3	1		T27	1		T48	11
valid_sources[0x4c]	895	1			T1	9		T3	3		T27	5
valid_sources[0x4d]	872	1			T3	1		T4	1		T26	11
valid_sources[0x4e]	1048	1			T4	2		T27	8		T48	11
valid_sources[0x4f]	897	1			T4	1		T27	2		T56	3
valid_sources[0x50]	921	1			T1	2		T3	5		T27	4
valid_sources[0x51]	1010	1			T3	3		T4	3		T27	2
valid_sources[0x52]	890	1			T3	6		T4	3		T27	3
valid_sources[0x53]	1922	1			T3	1		T4	2		T27	2
valid_sources[0x54]	1498	1			T3	3		T27	6		T8	1
valid_sources[0x55]	851	1			T24	8		T4	4		T27	3
valid_sources[0x56]	1176	1			T2	1		T3	1		T4	3
valid_sources[0x57]	2282	1			T3	1		T4	3		T27	2
valid_sources[0x58]	1228	1			T1	5		T3	1		T27	6
valid_sources[0x59]	1289	1			T4	3		T27	1		T48	8
valid_sources[0x5a]	1018	1			T3	4		T4	1		T27	1
valid_sources[0x5b]	971	1			T4	3		T27	4		T48	3
valid_sources[0x5c]	1191	1			T2	1		T3	2		T4	2
valid_sources[0x5d]	1358	1			T1	9		T4	1		T27	3
valid_sources[0x5e]	1181	1			T1	5		T3	3		T27	4
valid_sources[0x5f]	940	1			T2	3		T3	10		T4	2
valid_sources[0x60]	1785	1			T3	5		T4	2		T27	2
valid_sources[0x61]	1178	1			T1	3		T3	1		T4	2
valid_sources[0x62]	993	1			T3	3		T4	1		T27	1
valid_sources[0x63]	1118	1			T2	1		T4	2		T27	7
valid_sources[0x64]	967	1			T3	4		T4	3		T27	1
valid_sources[0x65]	2315	1			T23	1		T4	3		T48	2
valid_sources[0x66]	876	1			T27	6		T48	9		T56	1
valid_sources[0x67]	1181	1			T3	1		T4	2		T27	2
valid_sources[0x68]	1014	1			T4	2		T27	2		T48	12
valid_sources[0x69]	965	1			T27	2		T48	1		T8	1
valid_sources[0x6a]	1195	1			T1	5		T3	6		T4	1
valid_sources[0x6b]	2309	1			T4	3		T27	2		T48	7
valid_sources[0x6c]	1046	1			T3	1		T4	1		T27	2
valid_sources[0x6d]	1073	1			T4	1		T27	3		T48	5
valid_sources[0x6e]	981	1			T3	11		T24	4		T27	1
valid_sources[0x6f]	1142	1			T3	9		T27	1		T48	8
valid_sources[0x70]	968	1			T3	3		T4	2		T27	3
valid_sources[0x71]	947	1			T2	2		T3	2		T4	4
valid_sources[0x72]	1061	1			T3	1		T24	1		T27	1
valid_sources[0x73]	1837	1			T3	1		T4	4		T27	5
valid_sources[0x74]	838	1			T3	3		T4	1		T27	5
valid_sources[0x75]	1092	1			T3	1		T4	2		T27	1
valid_sources[0x76]	1222	1			T27	2		T48	15		T8	4
valid_sources[0x77]	958	1			T1	3		T3	6		T4	3
valid_sources[0x78]	1058	1			T3	2		T24	1		T4	3
valid_sources[0x79]	1044	1			T3	3		T24	1		T4	2
valid_sources[0x7a]	1601	1			T1	7		T3	6		T4	2
valid_sources[0x7b]	948	1			T3	2		T4	2		T27	4
valid_sources[0x7c]	1040	1			T3	7		T4	3		T27	2
valid_sources[0x7d]	1119	1			T4	2		T27	1		T48	12
valid_sources[0x7e]	998	1			T3	3		T4	1		T27	2
valid_sources[0x7f]	912	1			T1	4		T4	1		T27	6
valid_sources[0x80]	1051	1			T4	3		T27	7		T48	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

69632

1

T5

206

T1

143

T2

4

values[0x0]

all_enables

biggest_size

36028

1

T5

19

T1

40

T2

2

values[0x1]

all_enables

biggest_size

26734

1

T5

24

T1

27

T2

1