Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T5,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T10,T14,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T10,T14,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T10,T14,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T14,T15
1	0	Covered	T5,T1,T2
1	1	Covered	T10,T14,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T14,T21
0	1	Covered	T185,T186
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T14,T21
0	1	Covered	T10,T21,T187
1	0	Covered	T14

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T14,T21
1	-	Covered	T10,T21,T187

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T14,T21
DetectSt	168	Covered	T10,T14,T21
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T10,T14,T21

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T14,T21
DebounceSt->IdleSt	163	Covered	T83
DetectSt->IdleSt	186	Covered	T185,T186
DetectSt->StableSt	191	Covered	T10,T14,T21
IdleSt->DebounceSt	148	Covered	T10,T14,T21
StableSt->IdleSt	206	Covered	T10,T14,T21

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T14,T21
0	1	Covered	T10,T14,T21
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T14,T21
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T14,T21
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T83
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T14,T21
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T14,T21
DetectSt	-	-	-	-	1	-	-	Covered	T185,T186
DetectSt	-	-	-	-	0	1	-	Covered	T10,T14,T21
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T14,T21
StableSt	-	-	-	-	-	-	0	Covered	T10,T14,T21
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6011137	113	0	0
CntIncr_A	6011137	35338	0	0
CntNoWrap_A	6011137	5357778	0	0
DetectStDropOut_A	6011137	2	0	0
DetectedOut_A	6011137	15563	0	0
DetectedPulseOut_A	6011137	54	0	0
DisabledIdleSt_A	6011137	4950612	0	0
DisabledNoDetection_A	6011137	4952862	0	0
EnterDebounceSt_A	6011137	57	0	0
EnterDetectSt_A	6011137	56	0	0
EnterStableSt_A	6011137	54	0	0
PulseIsPulse_A	6011137	54	0	0
StayInStableSt	6011137	15484	0	0
gen_high_level_sva.HighLevelEvent_A	6011137	5360213	0	0
gen_not_sticky_sva.StableStDropOut_A	6011137	28	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	113	0	0
T10	834	2	0	0
T11	511	0	0	0
T12	22960	0	0	0
T14	0	2	0	0
T21	0	2	0	0
T35	633	0	0	0
T45	625	0	0	0
T51	0	2	0	0
T52	0	2	0	0
T53	0	4	0	0
T62	493	0	0	0
T64	502	0	0	0
T65	524	0	0	0
T132	0	2	0	0
T167	0	2	0	0
T187	0	2	0	0
T188	0	2	0	0
T189	605	0	0	0
T190	428	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	35338	0	0
T10	834	74	0	0
T11	511	0	0	0
T12	22960	0	0	0
T14	0	35	0	0
T21	0	86	0	0
T35	633	0	0	0
T45	625	0	0	0
T51	0	74	0	0
T52	0	20	0	0
T53	0	94	0	0
T62	493	0	0	0
T64	502	0	0	0
T65	524	0	0	0
T132	0	22053	0	0
T167	0	97	0	0
T187	0	53	0	0
T188	0	64	0	0
T189	605	0	0	0
T190	428	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5357778	0	0
T1	6250	2449	0	0
T2	751	350	0	0
T3	18039	17591	0	0
T4	10366	9952	0	0
T5	15041	14612	0	0
T23	408	7	0	0
T24	493	92	0	0
T25	1305	103	0	0
T26	777	376	0	0
T27	10053	9652	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	2	0	0
T74	1563	0	0	0
T185	688	1	0	0
T186	0	1	0	0
T191	2850	0	0	0
T192	5316	0	0	0
T193	25749	0	0	0
T194	672	0	0	0
T195	2130	0	0	0
T196	1653	0	0	0
T197	419	0	0	0
T198	503	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	15563	0	0
T10	834	64	0	0
T11	511	0	0	0
T12	22960	0	0	0
T14	0	11	0	0
T21	0	43	0	0
T35	633	0	0	0
T45	625	0	0	0
T51	0	143	0	0
T52	0	40	0	0
T53	0	202	0	0
T62	493	0	0	0
T64	502	0	0	0
T65	524	0	0	0
T132	0	39	0	0
T167	0	41	0	0
T187	0	26	0	0
T188	0	219	0	0
T189	605	0	0	0
T190	428	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	54	0	0
T10	834	1	0	0
T11	511	0	0	0
T12	22960	0	0	0
T14	0	1	0	0
T21	0	1	0	0
T35	633	0	0	0
T45	625	0	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	2	0	0
T62	493	0	0	0
T64	502	0	0	0
T65	524	0	0	0
T132	0	1	0	0
T167	0	1	0	0
T187	0	1	0	0
T188	0	1	0	0
T189	605	0	0	0
T190	428	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	4950612	0	0
T1	6250	2449	0	0
T2	751	350	0	0
T3	18039	17591	0	0
T4	10366	9952	0	0
T5	15041	14612	0	0
T23	408	7	0	0
T24	493	92	0	0
T25	1305	103	0	0
T26	777	376	0	0
T27	10053	9652	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	4952862	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	57	0	0
T10	834	1	0	0
T11	511	0	0	0
T12	22960	0	0	0
T14	0	1	0	0
T21	0	1	0	0
T35	633	0	0	0
T45	625	0	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	2	0	0
T62	493	0	0	0
T64	502	0	0	0
T65	524	0	0	0
T132	0	1	0	0
T167	0	1	0	0
T187	0	1	0	0
T188	0	1	0	0
T189	605	0	0	0
T190	428	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	56	0	0
T10	834	1	0	0
T11	511	0	0	0
T12	22960	0	0	0
T14	0	1	0	0
T21	0	1	0	0
T35	633	0	0	0
T45	625	0	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	2	0	0
T62	493	0	0	0
T64	502	0	0	0
T65	524	0	0	0
T132	0	1	0	0
T167	0	1	0	0
T187	0	1	0	0
T188	0	1	0	0
T189	605	0	0	0
T190	428	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	54	0	0
T10	834	1	0	0
T11	511	0	0	0
T12	22960	0	0	0
T14	0	1	0	0
T21	0	1	0	0
T35	633	0	0	0
T45	625	0	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	2	0	0
T62	493	0	0	0
T64	502	0	0	0
T65	524	0	0	0
T132	0	1	0	0
T167	0	1	0	0
T187	0	1	0	0
T188	0	1	0	0
T189	605	0	0	0
T190	428	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	54	0	0
T10	834	1	0	0
T11	511	0	0	0
T12	22960	0	0	0
T14	0	1	0	0
T21	0	1	0	0
T35	633	0	0	0
T45	625	0	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	2	0	0
T62	493	0	0	0
T64	502	0	0	0
T65	524	0	0	0
T132	0	1	0	0
T167	0	1	0	0
T187	0	1	0	0
T188	0	1	0	0
T189	605	0	0	0
T190	428	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	15484	0	0
T10	834	63	0	0
T11	511	0	0	0
T12	22960	0	0	0
T14	0	10	0	0
T21	0	42	0	0
T35	633	0	0	0
T45	625	0	0	0
T51	0	141	0	0
T52	0	38	0	0
T53	0	199	0	0
T62	493	0	0	0
T64	502	0	0	0
T65	524	0	0	0
T132	0	37	0	0
T167	0	39	0	0
T187	0	25	0	0
T188	0	217	0	0
T189	605	0	0	0
T190	428	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5360213	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	28	0	0
T10	834	1	0	0
T11	511	0	0	0
T12	22960	0	0	0
T21	0	1	0	0
T35	633	0	0	0
T45	625	0	0	0
T53	0	1	0	0
T54	0	1	0	0
T62	493	0	0	0
T64	502	0	0	0
T65	524	0	0	0
T93	0	1	0	0
T158	0	1	0	0
T159	0	1	0	0
T178	0	1	0	0
T187	0	1	0	0
T189	605	0	0	0
T190	428	0	0	0
T199	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T5,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T8,T10,T14

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T8,T10,T14

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T8,T10,T14

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T10,T14
1	0	Covered	T5,T1,T2
1	1	Covered	T8,T10,T14

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T10,T14
0	1	Covered	T87,T89
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T10,T14
0	1	Covered	T8,T10,T51
1	0	Covered	T14

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T10,T14
1	-	Covered	T8,T10,T51

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T10,T14
DetectSt	168	Covered	T8,T10,T14
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T8,T10,T14

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T10,T14
DebounceSt->IdleSt	163	Covered	T21,T132,T199
DetectSt->IdleSt	186	Covered	T87,T89
DetectSt->StableSt	191	Covered	T8,T10,T14
IdleSt->DebounceSt	148	Covered	T8,T10,T14
StableSt->IdleSt	206	Covered	T8,T10,T14

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T10,T14
0	1	Covered	T8,T10,T14
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T10,T14
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T10,T14
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T83
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T10,T14
DebounceSt	-	0	1	0	-	-	-	Covered	T21,T132,T199
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T10,T14
DetectSt	-	-	-	-	1	-	-	Covered	T87,T89
DetectSt	-	-	-	-	0	1	-	Covered	T8,T10,T14
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T10,T14
StableSt	-	-	-	-	-	-	0	Covered	T8,T10,T14
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6011137	154	0	0
CntIncr_A	6011137	78754	0	0
CntNoWrap_A	6011137	5357737	0	0
DetectStDropOut_A	6011137	2	0	0
DetectedOut_A	6011137	78631	0	0
DetectedPulseOut_A	6011137	72	0	0
DisabledIdleSt_A	6011137	5134267	0	0
DisabledNoDetection_A	6011137	5136527	0	0
EnterDebounceSt_A	6011137	80	0	0
EnterDetectSt_A	6011137	74	0	0
EnterStableSt_A	6011137	72	0	0
PulseIsPulse_A	6011137	72	0	0
StayInStableSt	6011137	78528	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6011137	3134	0	0
gen_low_level_sva.LowLevelEvent_A	6011137	5360213	0	0
gen_not_sticky_sva.StableStDropOut_A	6011137	40	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	154	0	0
T8	10018	2	0	0
T9	508	0	0	0
T10	834	4	0	0
T11	511	0	0	0
T14	0	2	0	0
T20	0	2	0	0
T21	0	3	0	0
T31	4411	0	0	0
T32	505	0	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T45	625	0	0	0
T51	0	2	0	0
T52	0	2	0	0
T55	0	2	0	0
T132	0	3	0	0
T164	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	78754	0	0
T8	10018	75	0	0
T9	508	0	0	0
T10	834	148	0	0
T11	511	0	0	0
T14	0	35	0	0
T20	0	28	0	0
T21	0	172	0	0
T31	4411	0	0	0
T32	505	0	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T45	625	0	0	0
T51	0	74	0	0
T52	0	20	0	0
T55	0	48	0	0
T132	0	22075	0	0
T164	0	61	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5357737	0	0
T1	6250	2449	0	0
T2	751	350	0	0
T3	18039	17591	0	0
T4	10366	9952	0	0
T5	15041	14612	0	0
T23	408	7	0	0
T24	493	92	0	0
T25	1305	103	0	0
T26	777	376	0	0
T27	10053	9652	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	2	0	0
T87	862	1	0	0
T88	153696	0	0	0
T89	0	1	0	0
T155	491	0	0	0
T169	426	0	0	0
T170	13127	0	0	0
T171	651	0	0	0
T172	805	0	0	0
T173	423	0	0	0
T174	523	0	0	0
T175	21072	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	78631	0	0
T8	10018	23	0	0
T9	508	0	0	0
T10	834	136	0	0
T11	511	0	0	0
T14	0	11	0	0
T20	0	81	0	0
T21	0	176	0	0
T31	4411	0	0	0
T32	505	0	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T45	625	0	0	0
T51	0	40	0	0
T52	0	11	0	0
T55	0	45	0	0
T132	0	66	0	0
T164	0	100	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	72	0	0
T8	10018	1	0	0
T9	508	0	0	0
T10	834	2	0	0
T11	511	0	0	0
T14	0	1	0	0
T20	0	1	0	0
T21	0	1	0	0
T31	4411	0	0	0
T32	505	0	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T45	625	0	0	0
T51	0	1	0	0
T52	0	1	0	0
T55	0	1	0	0
T132	0	1	0	0
T164	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5134267	0	0
T1	6250	2449	0	0
T2	751	350	0	0
T3	18039	17591	0	0
T4	10366	9952	0	0
T5	15041	14612	0	0
T23	408	7	0	0
T24	493	92	0	0
T25	1305	103	0	0
T26	777	376	0	0
T27	10053	9652	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5136527	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	80	0	0
T8	10018	1	0	0
T9	508	0	0	0
T10	834	2	0	0
T11	511	0	0	0
T14	0	1	0	0
T20	0	1	0	0
T21	0	2	0	0
T31	4411	0	0	0
T32	505	0	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T45	625	0	0	0
T51	0	1	0	0
T52	0	1	0	0
T55	0	1	0	0
T132	0	2	0	0
T164	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	74	0	0
T8	10018	1	0	0
T9	508	0	0	0
T10	834	2	0	0
T11	511	0	0	0
T14	0	1	0	0
T20	0	1	0	0
T21	0	1	0	0
T31	4411	0	0	0
T32	505	0	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T45	625	0	0	0
T51	0	1	0	0
T52	0	1	0	0
T55	0	1	0	0
T132	0	1	0	0
T164	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	72	0	0
T8	10018	1	0	0
T9	508	0	0	0
T10	834	2	0	0
T11	511	0	0	0
T14	0	1	0	0
T20	0	1	0	0
T21	0	1	0	0
T31	4411	0	0	0
T32	505	0	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T45	625	0	0	0
T51	0	1	0	0
T52	0	1	0	0
T55	0	1	0	0
T132	0	1	0	0
T164	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	72	0	0
T8	10018	1	0	0
T9	508	0	0	0
T10	834	2	0	0
T11	511	0	0	0
T14	0	1	0	0
T20	0	1	0	0
T21	0	1	0	0
T31	4411	0	0	0
T32	505	0	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T45	625	0	0	0
T51	0	1	0	0
T52	0	1	0	0
T55	0	1	0	0
T132	0	1	0	0
T164	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	78528	0	0
T8	10018	22	0	0
T9	508	0	0	0
T10	834	133	0	0
T11	511	0	0	0
T14	0	10	0	0
T20	0	79	0	0
T21	0	174	0	0
T31	4411	0	0	0
T32	505	0	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T45	625	0	0	0
T51	0	39	0	0
T52	0	10	0	0
T55	0	43	0	0
T132	0	65	0	0
T164	0	98	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	3134	0	0
T1	6250	28	0	0
T2	751	3	0	0
T3	18039	0	0	0
T4	10366	0	0	0
T7	0	3	0	0
T23	408	0	0	0
T24	493	6	0	0
T25	1305	4	0	0
T26	777	0	0	0
T27	10053	0	0	0
T28	418	2	0	0
T29	0	3	0	0
T46	0	4	0	0
T60	0	5	0	0
T61	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5360213	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	40	0	0
T8	10018	1	0	0
T9	508	0	0	0
T10	834	1	0	0
T11	511	0	0	0
T31	4411	0	0	0
T32	505	0	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T45	625	0	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	2	0	0
T54	0	2	0	0
T80	0	1	0	0
T132	0	1	0	0
T200	0	1	0	0
T201	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T5,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T10,T14,T18

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T10,T14,T18

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T10,T14,T18

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T14
1	0	Covered	T5,T1,T2
1	1	Covered	T10,T14,T18

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T14,T18
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T14,T18
0	1	Covered	T10,T18,T55
1	0	Covered	T14

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T14,T18
1	-	Covered	T10,T18,T55

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T14,T18
DetectSt	168	Covered	T10,T14,T18
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T10,T14,T18

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T14,T18
DebounceSt->IdleSt	163	Covered	T54,T202,T161
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T10,T14,T18
IdleSt->DebounceSt	148	Covered	T10,T14,T18
StableSt->IdleSt	206	Covered	T10,T14,T18

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T14,T18
0	1	Covered	T10,T14,T18
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T14,T18
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T14,T18
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T83
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T14,T18
DebounceSt	-	0	1	0	-	-	-	Covered	T54,T202,T161
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T14,T18
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T10,T14,T18
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T14,T18
StableSt	-	-	-	-	-	-	0	Covered	T10,T14,T18
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6011137	134	0	0
CntIncr_A	6011137	70015	0	0
CntNoWrap_A	6011137	5357757	0	0
DetectStDropOut_A	6011137	0	0	0
DetectedOut_A	6011137	28540	0	0
DetectedPulseOut_A	6011137	64	0	0
DisabledIdleSt_A	6011137	5009037	0	0
DisabledNoDetection_A	6011137	5011307	0	0
EnterDebounceSt_A	6011137	70	0	0
EnterDetectSt_A	6011137	64	0	0
EnterStableSt_A	6011137	64	0	0
PulseIsPulse_A	6011137	64	0	0
StayInStableSt	6011137	28456	0	0
gen_high_level_sva.HighLevelEvent_A	6011137	5360213	0	0
gen_not_sticky_sva.StableStDropOut_A	6011137	43	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	134	0	0
T10	834	2	0	0
T11	511	0	0	0
T12	22960	0	0	0
T14	0	2	0	0
T18	0	2	0	0
T35	633	0	0	0
T45	625	0	0	0
T54	0	3	0	0
T55	0	2	0	0
T62	493	0	0	0
T64	502	0	0	0
T65	524	0	0	0
T88	0	4	0	0
T89	0	4	0	0
T157	0	2	0	0
T187	0	2	0	0
T189	605	0	0	0
T190	428	0	0	0
T203	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	70015	0	0
T10	834	74	0	0
T11	511	0	0	0
T12	22960	0	0	0
T14	0	35	0	0
T18	0	40	0	0
T35	633	0	0	0
T45	625	0	0	0
T54	0	163	0	0
T55	0	48	0	0
T62	493	0	0	0
T64	502	0	0	0
T65	524	0	0	0
T88	0	52542	0	0
T89	0	144	0	0
T157	0	83	0	0
T187	0	53	0	0
T189	605	0	0	0
T190	428	0	0	0
T203	0	104	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5357757	0	0
T1	6250	2449	0	0
T2	751	350	0	0
T3	18039	17591	0	0
T4	10366	9952	0	0
T5	15041	14612	0	0
T23	408	7	0	0
T24	493	92	0	0
T25	1305	103	0	0
T26	777	376	0	0
T27	10053	9652	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	28540	0	0
T10	834	98	0	0
T11	511	0	0	0
T12	22960	0	0	0
T14	0	10	0	0
T18	0	43	0	0
T35	633	0	0	0
T45	625	0	0	0
T54	0	507	0	0
T55	0	35	0	0
T62	493	0	0	0
T64	502	0	0	0
T65	524	0	0	0
T88	0	21884	0	0
T89	0	411	0	0
T157	0	125	0	0
T187	0	312	0	0
T189	605	0	0	0
T190	428	0	0	0
T203	0	248	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	64	0	0
T10	834	1	0	0
T11	511	0	0	0
T12	22960	0	0	0
T14	0	1	0	0
T18	0	1	0	0
T35	633	0	0	0
T45	625	0	0	0
T54	0	1	0	0
T55	0	1	0	0
T62	493	0	0	0
T64	502	0	0	0
T65	524	0	0	0
T88	0	2	0	0
T89	0	2	0	0
T157	0	1	0	0
T187	0	1	0	0
T189	605	0	0	0
T190	428	0	0	0
T203	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5009037	0	0
T1	6250	2449	0	0
T2	751	350	0	0
T3	18039	17591	0	0
T4	10366	9952	0	0
T5	15041	14612	0	0
T23	408	7	0	0
T24	493	92	0	0
T25	1305	103	0	0
T26	777	376	0	0
T27	10053	9652	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5011307	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	70	0	0
T10	834	1	0	0
T11	511	0	0	0
T12	22960	0	0	0
T14	0	1	0	0
T18	0	1	0	0
T35	633	0	0	0
T45	625	0	0	0
T54	0	2	0	0
T55	0	1	0	0
T62	493	0	0	0
T64	502	0	0	0
T65	524	0	0	0
T88	0	2	0	0
T89	0	2	0	0
T157	0	1	0	0
T187	0	1	0	0
T189	605	0	0	0
T190	428	0	0	0
T203	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	64	0	0
T10	834	1	0	0
T11	511	0	0	0
T12	22960	0	0	0
T14	0	1	0	0
T18	0	1	0	0
T35	633	0	0	0
T45	625	0	0	0
T54	0	1	0	0
T55	0	1	0	0
T62	493	0	0	0
T64	502	0	0	0
T65	524	0	0	0
T88	0	2	0	0
T89	0	2	0	0
T157	0	1	0	0
T187	0	1	0	0
T189	605	0	0	0
T190	428	0	0	0
T203	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	64	0	0
T10	834	1	0	0
T11	511	0	0	0
T12	22960	0	0	0
T14	0	1	0	0
T18	0	1	0	0
T35	633	0	0	0
T45	625	0	0	0
T54	0	1	0	0
T55	0	1	0	0
T62	493	0	0	0
T64	502	0	0	0
T65	524	0	0	0
T88	0	2	0	0
T89	0	2	0	0
T157	0	1	0	0
T187	0	1	0	0
T189	605	0	0	0
T190	428	0	0	0
T203	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	64	0	0
T10	834	1	0	0
T11	511	0	0	0
T12	22960	0	0	0
T14	0	1	0	0
T18	0	1	0	0
T35	633	0	0	0
T45	625	0	0	0
T54	0	1	0	0
T55	0	1	0	0
T62	493	0	0	0
T64	502	0	0	0
T65	524	0	0	0
T88	0	2	0	0
T89	0	2	0	0
T157	0	1	0	0
T187	0	1	0	0
T189	605	0	0	0
T190	428	0	0	0
T203	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	28456	0	0
T10	834	97	0	0
T11	511	0	0	0
T12	22960	0	0	0
T14	0	9	0	0
T18	0	42	0	0
T35	633	0	0	0
T45	625	0	0	0
T54	0	506	0	0
T55	0	34	0	0
T62	493	0	0	0
T64	502	0	0	0
T65	524	0	0	0
T88	0	21881	0	0
T89	0	408	0	0
T157	0	124	0	0
T187	0	310	0	0
T189	605	0	0	0
T190	428	0	0	0
T203	0	245	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5360213	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	43	0	0
T10	834	1	0	0
T11	511	0	0	0
T12	22960	0	0	0
T18	0	1	0	0
T35	633	0	0	0
T45	625	0	0	0
T54	0	1	0	0
T55	0	1	0	0
T62	493	0	0	0
T64	502	0	0	0
T65	524	0	0	0
T88	0	1	0	0
T89	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0
T189	605	0	0	0
T190	428	0	0	0
T203	0	1	0	0
T204	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T5,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T14,T52,T53

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T14,T52,T53

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T14,T52,T53

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T52,T79
1	0	Covered	T5,T1,T2
1	1	Covered	T14,T52,T53

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T52,T53
0	1	Covered	T199,T205
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T52,T53
0	1	Covered	T52,T53,T88
1	0	Covered	T14

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T52,T53
1	-	Covered	T52,T53,T88

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T14,T52,T53
DetectSt	168	Covered	T14,T52,T53
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T14,T52,T53

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T14,T52,T53
DebounceSt->IdleSt	163	Covered	T89,T201,T83
DetectSt->IdleSt	186	Covered	T199,T205
DetectSt->StableSt	191	Covered	T14,T52,T53
IdleSt->DebounceSt	148	Covered	T14,T52,T53
StableSt->IdleSt	206	Covered	T14,T52,T53

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T52,T53
0	1	Covered	T14,T52,T53
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T52,T53
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T52,T53
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T83
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T52,T53
DebounceSt	-	0	1	0	-	-	-	Covered	T89,T201
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T52,T53
DetectSt	-	-	-	-	1	-	-	Covered	T199,T205
DetectSt	-	-	-	-	0	1	-	Covered	T14,T52,T53
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T14,T52,T53
StableSt	-	-	-	-	-	-	0	Covered	T14,T52,T53
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6011137	69	0	0
CntIncr_A	6011137	50409	0	0
CntNoWrap_A	6011137	5357822	0	0
DetectStDropOut_A	6011137	2	0	0
DetectedOut_A	6011137	40598	0	0
DetectedPulseOut_A	6011137	31	0	0
DisabledIdleSt_A	6011137	4954427	0	0
DisabledNoDetection_A	6011137	4956706	0	0
EnterDebounceSt_A	6011137	36	0	0
EnterDetectSt_A	6011137	33	0	0
EnterStableSt_A	6011137	31	0	0
PulseIsPulse_A	6011137	31	0	0
StayInStableSt	6011137	40552	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6011137	6736	0	0
gen_low_level_sva.LowLevelEvent_A	6011137	5360213	0	0
gen_not_sticky_sva.StableStDropOut_A	6011137	15	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	69	0	0
T14	8504	2	0	0
T15	671	0	0	0
T16	2986	0	0	0
T17	20177	0	0	0
T18	103663	0	0	0
T52	0	2	0	0
T53	0	4	0	0
T54	0	4	0	0
T57	58412	0	0	0
T58	713	0	0	0
T66	505	0	0	0
T67	524	0	0	0
T80	0	2	0	0
T88	0	2	0	0
T89	0	3	0	0
T179	0	2	0	0
T201	0	3	0	0
T204	0	2	0	0
T206	423	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	50409	0	0
T14	8504	35	0	0
T15	671	0	0	0
T16	2986	0	0	0
T17	20177	0	0	0
T18	103663	0	0	0
T52	0	20	0	0
T53	0	94	0	0
T54	0	163	0	0
T57	58412	0	0	0
T58	713	0	0	0
T66	505	0	0	0
T67	524	0	0	0
T80	0	85	0	0
T88	0	26271	0	0
T89	0	140	0	0
T179	0	75	0	0
T201	0	176	0	0
T204	0	34	0	0
T206	423	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5357822	0	0
T1	6250	2449	0	0
T2	751	350	0	0
T3	18039	17591	0	0
T4	10366	9952	0	0
T5	15041	14612	0	0
T23	408	7	0	0
T24	493	92	0	0
T25	1305	103	0	0
T26	777	376	0	0
T27	10053	9652	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	2	0	0
T199	1483	1	0	0
T205	0	1	0	0
T207	667	0	0	0
T208	9314	0	0	0
T209	403	0	0	0
T210	407	0	0	0
T211	489	0	0	0
T212	522	0	0	0
T213	5336	0	0	0
T214	402	0	0	0
T215	502	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	40598	0	0
T14	8504	10	0	0
T15	671	0	0	0
T16	2986	0	0	0
T17	20177	0	0	0
T18	103663	0	0	0
T52	0	39	0	0
T53	0	80	0	0
T54	0	81	0	0
T57	58412	0	0	0
T58	713	0	0	0
T66	505	0	0	0
T67	524	0	0	0
T80	0	161	0	0
T88	0	26316	0	0
T89	0	42	0	0
T179	0	163	0	0
T201	0	54	0	0
T204	0	78	0	0
T206	423	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	31	0	0
T14	8504	1	0	0
T15	671	0	0	0
T16	2986	0	0	0
T17	20177	0	0	0
T18	103663	0	0	0
T52	0	1	0	0
T53	0	2	0	0
T54	0	2	0	0
T57	58412	0	0	0
T58	713	0	0	0
T66	505	0	0	0
T67	524	0	0	0
T80	0	1	0	0
T88	0	1	0	0
T89	0	1	0	0
T179	0	1	0	0
T201	0	1	0	0
T204	0	1	0	0
T206	423	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	4954427	0	0
T1	6250	2449	0	0
T2	751	350	0	0
T3	18039	17591	0	0
T4	10366	9952	0	0
T5	15041	14612	0	0
T23	408	7	0	0
T24	493	92	0	0
T25	1305	103	0	0
T26	777	376	0	0
T27	10053	9652	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	4956706	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	36	0	0
T14	8504	1	0	0
T15	671	0	0	0
T16	2986	0	0	0
T17	20177	0	0	0
T18	103663	0	0	0
T52	0	1	0	0
T53	0	2	0	0
T54	0	2	0	0
T57	58412	0	0	0
T58	713	0	0	0
T66	505	0	0	0
T67	524	0	0	0
T80	0	1	0	0
T88	0	1	0	0
T89	0	2	0	0
T179	0	1	0	0
T201	0	2	0	0
T204	0	1	0	0
T206	423	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	33	0	0
T14	8504	1	0	0
T15	671	0	0	0
T16	2986	0	0	0
T17	20177	0	0	0
T18	103663	0	0	0
T52	0	1	0	0
T53	0	2	0	0
T54	0	2	0	0
T57	58412	0	0	0
T58	713	0	0	0
T66	505	0	0	0
T67	524	0	0	0
T80	0	1	0	0
T88	0	1	0	0
T89	0	1	0	0
T179	0	1	0	0
T201	0	1	0	0
T204	0	1	0	0
T206	423	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	31	0	0
T14	8504	1	0	0
T15	671	0	0	0
T16	2986	0	0	0
T17	20177	0	0	0
T18	103663	0	0	0
T52	0	1	0	0
T53	0	2	0	0
T54	0	2	0	0
T57	58412	0	0	0
T58	713	0	0	0
T66	505	0	0	0
T67	524	0	0	0
T80	0	1	0	0
T88	0	1	0	0
T89	0	1	0	0
T179	0	1	0	0
T201	0	1	0	0
T204	0	1	0	0
T206	423	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	31	0	0
T14	8504	1	0	0
T15	671	0	0	0
T16	2986	0	0	0
T17	20177	0	0	0
T18	103663	0	0	0
T52	0	1	0	0
T53	0	2	0	0
T54	0	2	0	0
T57	58412	0	0	0
T58	713	0	0	0
T66	505	0	0	0
T67	524	0	0	0
T80	0	1	0	0
T88	0	1	0	0
T89	0	1	0	0
T179	0	1	0	0
T201	0	1	0	0
T204	0	1	0	0
T206	423	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	40552	0	0
T14	8504	9	0	0
T15	671	0	0	0
T16	2986	0	0	0
T17	20177	0	0	0
T18	103663	0	0	0
T52	0	38	0	0
T53	0	78	0	0
T54	0	77	0	0
T57	58412	0	0	0
T58	713	0	0	0
T66	505	0	0	0
T67	524	0	0	0
T80	0	159	0	0
T88	0	26315	0	0
T89	0	40	0	0
T179	0	161	0	0
T201	0	53	0	0
T204	0	76	0	0
T206	423	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	6736	0	0
T1	6250	28	0	0
T2	751	1	0	0
T3	18039	9	0	0
T4	10366	6	0	0
T5	15041	15	0	0
T23	408	0	0	0
T24	493	6	0	0
T25	1305	4	0	0
T26	777	0	0	0
T27	10053	28	0	0
T28	0	1	0	0
T29	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5360213	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	15	0	0
T22	1388	0	0	0
T36	1637	0	0	0
T52	584	1	0	0
T53	0	2	0	0
T55	2392	0	0	0
T88	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0
T163	0	1	0	0
T184	865	0	0	0
T201	0	1	0	0
T216	0	1	0	0
T217	0	1	0	0
T218	0	1	0	0
T219	507	0	0	0
T220	506	0	0	0
T221	407	0	0	0
T222	429	0	0	0
T223	453	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T5,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T14,T15,T18

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T14,T15,T18

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T14,T15,T18

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T14,T15
1	0	Covered	T5,T1,T2
1	1	Covered	T14,T15,T18

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T18
0	1	Covered	T19,T205,T186
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T18
0	1	Covered	T15,T19,T53
1	0	Covered	T14

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T15,T18
1	-	Covered	T15,T19,T53

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T14,T15,T18
DetectSt	168	Covered	T14,T15,T18
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T14,T15,T18

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T14,T15,T18
DebounceSt->IdleSt	163	Covered	T224,T199,T225
DetectSt->IdleSt	186	Covered	T19,T205,T186
DetectSt->StableSt	191	Covered	T14,T15,T18
IdleSt->DebounceSt	148	Covered	T14,T15,T18
StableSt->IdleSt	206	Covered	T14,T15,T18

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T15,T18
0	1	Covered	T14,T15,T18
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T18
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T15,T18
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T83
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T15,T18
DebounceSt	-	0	1	0	-	-	-	Covered	T224,T199,T225
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T15,T18
DetectSt	-	-	-	-	1	-	-	Covered	T19,T205,T186
DetectSt	-	-	-	-	0	1	-	Covered	T14,T15,T18
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T14,T15,T19
StableSt	-	-	-	-	-	-	0	Covered	T14,T15,T18
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6011137	146	0	0
CntIncr_A	6011137	62604	0	0
CntNoWrap_A	6011137	5357745	0	0
DetectStDropOut_A	6011137	3	0	0
DetectedOut_A	6011137	81513	0	0
DetectedPulseOut_A	6011137	67	0	0
DisabledIdleSt_A	6011137	5100851	0	0
DisabledNoDetection_A	6011137	5103114	0	0
EnterDebounceSt_A	6011137	76	0	0
EnterDetectSt_A	6011137	70	0	0
EnterStableSt_A	6011137	67	0	0
PulseIsPulse_A	6011137	67	0	0
StayInStableSt	6011137	81418	0	0
gen_high_level_sva.HighLevelEvent_A	6011137	5360213	0	0
gen_not_sticky_sva.StableStDropOut_A	6011137	38	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	146	0	0
T14	8504	2	0	0
T15	671	2	0	0
T16	2986	0	0	0
T17	20177	0	0	0
T18	103663	2	0	0
T19	0	4	0	0
T20	0	2	0	0
T52	0	2	0	0
T53	0	2	0	0
T55	0	2	0	0
T57	58412	0	0	0
T58	713	0	0	0
T66	505	0	0	0
T67	524	0	0	0
T115	0	2	0	0
T165	0	2	0	0
T206	423	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	62604	0	0
T14	8504	35	0	0
T15	671	38	0	0
T16	2986	0	0	0
T17	20177	0	0	0
T18	103663	40	0	0
T19	0	196	0	0
T20	0	28	0	0
T52	0	20	0	0
T53	0	47	0	0
T55	0	51	0	0
T57	58412	0	0	0
T58	713	0	0	0
T66	505	0	0	0
T67	524	0	0	0
T115	0	66	0	0
T165	0	54	0	0
T206	423	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5357745	0	0
T1	6250	2449	0	0
T2	751	350	0	0
T3	18039	17591	0	0
T4	10366	9952	0	0
T5	15041	14612	0	0
T23	408	7	0	0
T24	493	92	0	0
T25	1305	103	0	0
T26	777	376	0	0
T27	10053	9652	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	3	0	0
T19	9205	1	0	0
T20	518	0	0	0
T49	33572	0	0	0
T50	20160	0	0	0
T59	729	0	0	0
T136	502	0	0	0
T137	8402	0	0	0
T138	486	0	0	0
T139	522	0	0	0
T140	426	0	0	0
T186	0	1	0	0
T205	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	81513	0	0
T14	8504	11	0	0
T15	671	44	0	0
T16	2986	0	0	0
T17	20177	0	0	0
T18	103663	39	0	0
T19	0	270	0	0
T20	0	38	0	0
T52	0	73	0	0
T53	0	99	0	0
T55	0	56	0	0
T57	58412	0	0	0
T58	713	0	0	0
T66	505	0	0	0
T67	524	0	0	0
T115	0	37	0	0
T165	0	92	0	0
T206	423	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	67	0	0
T14	8504	1	0	0
T15	671	1	0	0
T16	2986	0	0	0
T17	20177	0	0	0
T18	103663	1	0	0
T19	0	1	0	0
T20	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T55	0	1	0	0
T57	58412	0	0	0
T58	713	0	0	0
T66	505	0	0	0
T67	524	0	0	0
T115	0	1	0	0
T165	0	1	0	0
T206	423	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5100851	0	0
T1	6250	2449	0	0
T2	751	350	0	0
T3	18039	17591	0	0
T4	10366	9952	0	0
T5	15041	14612	0	0
T23	408	7	0	0
T24	493	92	0	0
T25	1305	103	0	0
T26	777	376	0	0
T27	10053	9652	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5103114	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	76	0	0
T14	8504	1	0	0
T15	671	1	0	0
T16	2986	0	0	0
T17	20177	0	0	0
T18	103663	1	0	0
T19	0	2	0	0
T20	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T55	0	1	0	0
T57	58412	0	0	0
T58	713	0	0	0
T66	505	0	0	0
T67	524	0	0	0
T115	0	1	0	0
T165	0	1	0	0
T206	423	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	70	0	0
T14	8504	1	0	0
T15	671	1	0	0
T16	2986	0	0	0
T17	20177	0	0	0
T18	103663	1	0	0
T19	0	2	0	0
T20	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T55	0	1	0	0
T57	58412	0	0	0
T58	713	0	0	0
T66	505	0	0	0
T67	524	0	0	0
T115	0	1	0	0
T165	0	1	0	0
T206	423	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	67	0	0
T14	8504	1	0	0
T15	671	1	0	0
T16	2986	0	0	0
T17	20177	0	0	0
T18	103663	1	0	0
T19	0	1	0	0
T20	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T55	0	1	0	0
T57	58412	0	0	0
T58	713	0	0	0
T66	505	0	0	0
T67	524	0	0	0
T115	0	1	0	0
T165	0	1	0	0
T206	423	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	67	0	0
T14	8504	1	0	0
T15	671	1	0	0
T16	2986	0	0	0
T17	20177	0	0	0
T18	103663	1	0	0
T19	0	1	0	0
T20	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T55	0	1	0	0
T57	58412	0	0	0
T58	713	0	0	0
T66	505	0	0	0
T67	524	0	0	0
T115	0	1	0	0
T165	0	1	0	0
T206	423	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	81418	0	0
T14	8504	10	0	0
T15	671	43	0	0
T16	2986	0	0	0
T17	20177	0	0	0
T18	103663	37	0	0
T19	0	269	0	0
T20	0	36	0	0
T52	0	71	0	0
T53	0	98	0	0
T55	0	54	0	0
T57	58412	0	0	0
T58	713	0	0	0
T66	505	0	0	0
T67	524	0	0	0
T115	0	35	0	0
T165	0	90	0	0
T206	423	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5360213	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	38	0	0
T15	671	1	0	0
T16	2986	0	0	0
T17	20177	0	0	0
T18	103663	0	0	0
T19	9205	1	0	0
T53	0	1	0	0
T57	58412	0	0	0
T58	713	0	0	0
T66	505	0	0	0
T67	524	0	0	0
T89	0	2	0	0
T107	0	1	0	0
T159	0	1	0	0
T178	0	1	0	0
T179	0	1	0	0
T188	0	2	0	0
T199	0	1	0	0
T206	423	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T5,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T9,T14,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T9,T14,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T9,T14,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T14,T18
1	0	Covered	T5,T1,T2
1	1	Covered	T9,T14,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T14,T21
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T14,T21
0	1	Covered	T80,T158,T226
1	0	Covered	T14

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T14,T21
1	-	Covered	T80,T158,T226

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T14,T21
DetectSt	168	Covered	T9,T14,T21
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T9,T14,T21

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T14,T21
DebounceSt->IdleSt	163	Covered	T200,T54,T83
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T9,T14,T21
IdleSt->DebounceSt	148	Covered	T9,T14,T21
StableSt->IdleSt	206	Covered	T14,T132,T54

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T14,T21
0	1	Covered	T9,T14,T21
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T14,T21
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T14,T21
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T83
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T14,T21
DebounceSt	-	0	1	0	-	-	-	Covered	T54
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T14,T21
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T9,T14,T21
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T14,T80,T158
StableSt	-	-	-	-	-	-	0	Covered	T9,T14,T21
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6011137	72	0	0
CntIncr_A	6011137	54625	0	0
CntNoWrap_A	6011137	5357819	0	0
DetectStDropOut_A	6011137	0	0	0
DetectedOut_A	6011137	16732	0	0
DetectedPulseOut_A	6011137	35	0	0
DisabledIdleSt_A	6011137	5205075	0	0
DisabledNoDetection_A	6011137	5207347	0	0
EnterDebounceSt_A	6011137	38	0	0
EnterDetectSt_A	6011137	35	0	0
EnterStableSt_A	6011137	35	0	0
PulseIsPulse_A	6011137	35	0	0
StayInStableSt	6011137	16674	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6011137	6351	0	0
gen_low_level_sva.LowLevelEvent_A	6011137	5360213	0	0
gen_not_sticky_sva.StableStDropOut_A	6011137	11	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	72	0	0
T9	508	2	0	0
T10	834	0	0	0
T11	511	0	0	0
T14	0	2	0	0
T21	0	2	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T45	625	0	0	0
T51	0	2	0	0
T54	0	3	0	0
T62	493	0	0	0
T80	0	4	0	0
T132	0	2	0	0
T179	0	2	0	0
T189	605	0	0	0
T190	428	0	0	0
T227	0	2	0	0
T228	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	54625	0	0
T9	508	21	0	0
T10	834	0	0	0
T11	511	0	0	0
T14	0	35	0	0
T21	0	86	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T45	625	0	0	0
T51	0	74	0	0
T54	0	194	0	0
T62	493	0	0	0
T80	0	170	0	0
T132	0	22053	0	0
T179	0	75	0	0
T189	605	0	0	0
T190	428	0	0	0
T200	0	45	0	0
T227	0	31	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5357819	0	0
T1	6250	2449	0	0
T2	751	350	0	0
T3	18039	17591	0	0
T4	10366	9952	0	0
T5	15041	14612	0	0
T23	408	7	0	0
T24	493	92	0	0
T25	1305	103	0	0
T26	777	376	0	0
T27	10053	9652	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	16732	0	0
T9	508	41	0	0
T10	834	0	0	0
T11	511	0	0	0
T14	0	11	0	0
T21	0	41	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T45	625	0	0	0
T51	0	143	0	0
T54	0	38	0	0
T62	493	0	0	0
T80	0	80	0	0
T132	0	40	0	0
T179	0	163	0	0
T189	605	0	0	0
T190	428	0	0	0
T227	0	41	0	0
T228	0	309	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	35	0	0
T9	508	1	0	0
T10	834	0	0	0
T11	511	0	0	0
T14	0	1	0	0
T21	0	1	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T45	625	0	0	0
T51	0	1	0	0
T54	0	1	0	0
T62	493	0	0	0
T80	0	2	0	0
T132	0	1	0	0
T179	0	1	0	0
T189	605	0	0	0
T190	428	0	0	0
T227	0	1	0	0
T228	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5205075	0	0
T1	6250	2449	0	0
T2	751	350	0	0
T3	18039	17591	0	0
T4	10366	9952	0	0
T5	15041	14612	0	0
T23	408	7	0	0
T24	493	92	0	0
T25	1305	103	0	0
T26	777	376	0	0
T27	10053	9652	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5207347	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	38	0	0
T9	508	1	0	0
T10	834	0	0	0
T11	511	0	0	0
T14	0	1	0	0
T21	0	1	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T45	625	0	0	0
T51	0	1	0	0
T54	0	2	0	0
T62	493	0	0	0
T80	0	2	0	0
T132	0	1	0	0
T179	0	1	0	0
T189	605	0	0	0
T190	428	0	0	0
T200	0	1	0	0
T227	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	35	0	0
T9	508	1	0	0
T10	834	0	0	0
T11	511	0	0	0
T14	0	1	0	0
T21	0	1	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T45	625	0	0	0
T51	0	1	0	0
T54	0	1	0	0
T62	493	0	0	0
T80	0	2	0	0
T132	0	1	0	0
T179	0	1	0	0
T189	605	0	0	0
T190	428	0	0	0
T227	0	1	0	0
T228	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	35	0	0
T9	508	1	0	0
T10	834	0	0	0
T11	511	0	0	0
T14	0	1	0	0
T21	0	1	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T45	625	0	0	0
T51	0	1	0	0
T54	0	1	0	0
T62	493	0	0	0
T80	0	2	0	0
T132	0	1	0	0
T179	0	1	0	0
T189	605	0	0	0
T190	428	0	0	0
T227	0	1	0	0
T228	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	35	0	0
T9	508	1	0	0
T10	834	0	0	0
T11	511	0	0	0
T14	0	1	0	0
T21	0	1	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T45	625	0	0	0
T51	0	1	0	0
T54	0	1	0	0
T62	493	0	0	0
T80	0	2	0	0
T132	0	1	0	0
T179	0	1	0	0
T189	605	0	0	0
T190	428	0	0	0
T227	0	1	0	0
T228	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	16674	0	0
T9	508	39	0	0
T10	834	0	0	0
T11	511	0	0	0
T14	0	10	0	0
T21	0	39	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T45	625	0	0	0
T51	0	141	0	0
T54	0	36	0	0
T62	493	0	0	0
T80	0	77	0	0
T132	0	38	0	0
T179	0	161	0	0
T189	605	0	0	0
T190	428	0	0	0
T227	0	39	0	0
T228	0	307	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	6351	0	0
T1	6250	29	0	0
T2	751	1	0	0
T3	18039	9	0	0
T4	10366	12	0	0
T5	15041	11	0	0
T23	408	0	0	0
T24	493	7	0	0
T25	1305	3	0	0
T26	777	0	0	0
T27	10053	29	0	0
T28	0	2	0	0
T29	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5360213	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	11	0	0
T80	1092	1	0	0
T89	23018	0	0	0
T158	0	1	0	0
T160	0	2	0	0
T161	0	1	0	0
T163	0	1	0	0
T178	1190	0	0	0
T201	1158	0	0	0
T218	0	1	0	0
T226	0	1	0	0
T229	0	1	0	0
T230	0	1	0	0
T231	0	1	0	0
T232	447	0	0	0
T233	421	0	0	0
T234	3934	0	0	0
T235	667	0	0	0
T236	898	0	0	0
T237	755	0	0	0