Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T5,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T8,T10,T14

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T8,T10,T14

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T8,T10,T14

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T10,T14
1	0	Covered	T5,T1,T2
1	1	Covered	T8,T10,T14

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T10,T14
0	1	Covered	T51,T238
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T10,T14
0	1	Covered	T10,T15,T132
1	0	Covered	T14

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T10,T14
1	-	Covered	T10,T15,T132

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T10,T14
DetectSt	168	Covered	T8,T10,T14
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T8,T10,T14

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T10,T14
DebounceSt->IdleSt	163	Covered	T226,T108,T205
DetectSt->IdleSt	186	Covered	T51,T238
DetectSt->StableSt	191	Covered	T8,T10,T14
IdleSt->DebounceSt	148	Covered	T8,T10,T14
StableSt->IdleSt	206	Covered	T8,T10,T14

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T10,T14
0	1	Covered	T8,T10,T14
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T10,T14
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T10,T14
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T83
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T10,T14
DebounceSt	-	0	1	0	-	-	-	Covered	T226,T108,T205
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T10,T14
DetectSt	-	-	-	-	1	-	-	Covered	T51,T238
DetectSt	-	-	-	-	0	1	-	Covered	T8,T10,T14
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T14,T15
StableSt	-	-	-	-	-	-	0	Covered	T8,T10,T14
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6011137	143	0	0
CntIncr_A	6011137	109088	0	0
CntNoWrap_A	6011137	5357748	0	0
DetectStDropOut_A	6011137	2	0	0
DetectedOut_A	6011137	68492	0	0
DetectedPulseOut_A	6011137	67	0	0
DisabledIdleSt_A	6011137	5013332	0	0
DisabledNoDetection_A	6011137	5015598	0	0
EnterDebounceSt_A	6011137	74	0	0
EnterDetectSt_A	6011137	69	0	0
EnterStableSt_A	6011137	67	0	0
PulseIsPulse_A	6011137	67	0	0
StayInStableSt	6011137	68393	0	0
gen_high_level_sva.HighLevelEvent_A	6011137	5360213	0	0
gen_not_sticky_sva.StableStDropOut_A	6011137	34	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	143	0	0
T8	10018	2	0	0
T9	508	0	0	0
T10	834	4	0	0
T11	511	0	0	0
T14	0	2	0	0
T15	0	4	0	0
T31	4411	0	0	0
T32	505	0	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T45	625	0	0	0
T51	0	2	0	0
T53	0	6	0	0
T115	0	2	0	0
T132	0	2	0	0
T164	0	2	0	0
T200	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	109088	0	0
T8	10018	75	0	0
T9	508	0	0	0
T10	834	148	0	0
T11	511	0	0	0
T14	0	35	0	0
T15	0	76	0	0
T31	4411	0	0	0
T32	505	0	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T45	625	0	0	0
T51	0	74	0	0
T53	0	141	0	0
T115	0	66	0	0
T132	0	22	0	0
T164	0	61	0	0
T200	0	93	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5357748	0	0
T1	6250	2449	0	0
T2	751	350	0	0
T3	18039	17591	0	0
T4	10366	9952	0	0
T5	15041	14612	0	0
T23	408	7	0	0
T24	493	92	0	0
T25	1305	103	0	0
T26	777	376	0	0
T27	10053	9652	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	2	0	0
T51	817	1	0	0
T52	584	0	0	0
T70	6129	0	0	0
T96	650	0	0	0
T133	522	0	0	0
T180	522	0	0	0
T181	500	0	0	0
T182	6536	0	0	0
T183	690	0	0	0
T184	865	0	0	0
T238	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	68492	0	0
T8	10018	41	0	0
T9	508	0	0	0
T10	834	137	0	0
T11	511	0	0	0
T14	0	10	0	0
T15	0	102	0	0
T31	4411	0	0	0
T32	505	0	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T45	625	0	0	0
T53	0	194	0	0
T104	0	80	0	0
T115	0	36	0	0
T132	0	43	0	0
T164	0	100	0	0
T200	0	63	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	67	0	0
T8	10018	1	0	0
T9	508	0	0	0
T10	834	2	0	0
T11	511	0	0	0
T14	0	1	0	0
T15	0	2	0	0
T31	4411	0	0	0
T32	505	0	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T45	625	0	0	0
T53	0	3	0	0
T104	0	1	0	0
T115	0	1	0	0
T132	0	1	0	0
T164	0	1	0	0
T200	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5013332	0	0
T1	6250	2449	0	0
T2	751	350	0	0
T3	18039	17591	0	0
T4	10366	9952	0	0
T5	15041	14612	0	0
T23	408	7	0	0
T24	493	92	0	0
T25	1305	103	0	0
T26	777	376	0	0
T27	10053	9652	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5015598	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	74	0	0
T8	10018	1	0	0
T9	508	0	0	0
T10	834	2	0	0
T11	511	0	0	0
T14	0	1	0	0
T15	0	2	0	0
T31	4411	0	0	0
T32	505	0	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T45	625	0	0	0
T51	0	1	0	0
T53	0	3	0	0
T115	0	1	0	0
T132	0	1	0	0
T164	0	1	0	0
T200	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	69	0	0
T8	10018	1	0	0
T9	508	0	0	0
T10	834	2	0	0
T11	511	0	0	0
T14	0	1	0	0
T15	0	2	0	0
T31	4411	0	0	0
T32	505	0	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T45	625	0	0	0
T51	0	1	0	0
T53	0	3	0	0
T115	0	1	0	0
T132	0	1	0	0
T164	0	1	0	0
T200	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	67	0	0
T8	10018	1	0	0
T9	508	0	0	0
T10	834	2	0	0
T11	511	0	0	0
T14	0	1	0	0
T15	0	2	0	0
T31	4411	0	0	0
T32	505	0	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T45	625	0	0	0
T53	0	3	0	0
T104	0	1	0	0
T115	0	1	0	0
T132	0	1	0	0
T164	0	1	0	0
T200	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	67	0	0
T8	10018	1	0	0
T9	508	0	0	0
T10	834	2	0	0
T11	511	0	0	0
T14	0	1	0	0
T15	0	2	0	0
T31	4411	0	0	0
T32	505	0	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T45	625	0	0	0
T53	0	3	0	0
T104	0	1	0	0
T115	0	1	0	0
T132	0	1	0	0
T164	0	1	0	0
T200	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	68393	0	0
T8	10018	39	0	0
T9	508	0	0	0
T10	834	134	0	0
T11	511	0	0	0
T14	0	9	0	0
T15	0	99	0	0
T31	4411	0	0	0
T32	505	0	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T45	625	0	0	0
T53	0	190	0	0
T104	0	78	0	0
T115	0	34	0	0
T132	0	42	0	0
T164	0	98	0	0
T200	0	62	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5360213	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	34	0	0
T10	834	1	0	0
T11	511	0	0	0
T12	22960	0	0	0
T15	0	1	0	0
T35	633	0	0	0
T45	625	0	0	0
T53	0	2	0	0
T62	493	0	0	0
T64	502	0	0	0
T65	524	0	0	0
T88	0	1	0	0
T132	0	1	0	0
T158	0	1	0	0
T178	0	1	0	0
T179	0	2	0	0
T189	605	0	0	0
T190	428	0	0	0
T200	0	1	0	0
T203	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T5,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T2,T10,T14

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T2,T10,T14

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T2,T10,T14

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T10
1	0	Covered	T5,T1,T3
1	1	Covered	T2,T10,T14

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T10,T14
0	1	Covered	T204
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T10,T14
0	1	Covered	T2,T10,T21
1	0	Covered	T14

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T10,T14
1	-	Covered	T2,T10,T21

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T10,T14
DetectSt	168	Covered	T2,T10,T14
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T2,T10,T14

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T10,T14
DebounceSt->IdleSt	163	Covered	T2,T200,T204
DetectSt->IdleSt	186	Covered	T204
DetectSt->StableSt	191	Covered	T2,T10,T14
IdleSt->DebounceSt	148	Covered	T2,T10,T14
StableSt->IdleSt	206	Covered	T2,T10,T14

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T10,T14
0	1	Covered	T2,T10,T14
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T10,T14
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T10,T14
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T83
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T10,T14
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T204,T218
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T10,T14
DetectSt	-	-	-	-	1	-	-	Covered	T204
DetectSt	-	-	-	-	0	1	-	Covered	T2,T10,T14
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T10,T14
StableSt	-	-	-	-	-	-	0	Covered	T2,T10,T14
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6011137	84	0	0
CntIncr_A	6011137	11455	0	0
CntNoWrap_A	6011137	5357807	0	0
DetectStDropOut_A	6011137	1	0	0
DetectedOut_A	6011137	3045	0	0
DetectedPulseOut_A	6011137	39	0	0
DisabledIdleSt_A	6011137	5277165	0	0
DisabledNoDetection_A	6011137	5279428	0	0
EnterDebounceSt_A	6011137	45	0	0
EnterDetectSt_A	6011137	40	0	0
EnterStableSt_A	6011137	39	0	0
PulseIsPulse_A	6011137	39	0	0
StayInStableSt	6011137	2987	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6011137	6341	0	0
gen_low_level_sva.LowLevelEvent_A	6011137	5360213	0	0
gen_not_sticky_sva.StableStDropOut_A	6011137	19	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	84	0	0
T2	751	3	0	0
T3	18039	0	0	0
T4	10366	0	0	0
T10	0	2	0	0
T14	0	2	0	0
T21	0	2	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T51	0	2	0	0
T52	0	2	0	0
T54	0	2	0	0
T55	0	2	0	0
T132	0	2	0	0
T227	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	11455	0	0
T2	751	78	0	0
T3	18039	0	0	0
T4	10366	0	0	0
T10	0	74	0	0
T14	0	35	0	0
T21	0	86	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T51	0	74	0	0
T52	0	20	0	0
T54	0	97	0	0
T55	0	48	0	0
T132	0	22	0	0
T200	0	45	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5357807	0	0
T1	6250	2449	0	0
T2	751	347	0	0
T3	18039	17591	0	0
T4	10366	9952	0	0
T5	15041	14612	0	0
T23	408	7	0	0
T24	493	92	0	0
T25	1305	103	0	0
T26	777	376	0	0
T27	10053	9652	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	1	0	0
T204	757	1	0	0
T239	448	0	0	0
T240	19037	0	0	0
T241	31859	0	0	0
T242	972	0	0	0
T243	19757	0	0	0
T244	523	0	0	0
T245	427	0	0	0
T246	523	0	0	0
T247	410	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	3045	0	0
T2	751	27	0	0
T3	18039	0	0	0
T4	10366	0	0	0
T10	0	63	0	0
T14	0	12	0	0
T21	0	42	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T51	0	258	0	0
T52	0	40	0	0
T54	0	37	0	0
T55	0	45	0	0
T132	0	83	0	0
T227	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	39	0	0
T2	751	1	0	0
T3	18039	0	0	0
T4	10366	0	0	0
T10	0	1	0	0
T14	0	1	0	0
T21	0	1	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T51	0	1	0	0
T52	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T132	0	1	0	0
T227	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5277165	0	0
T1	6250	2449	0	0
T2	751	3	0	0
T3	18039	17591	0	0
T4	10366	9952	0	0
T5	15041	14612	0	0
T23	408	7	0	0
T24	493	92	0	0
T25	1305	103	0	0
T26	777	376	0	0
T27	10053	9652	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5279428	0	0
T1	6250	2458	0	0
T2	751	3	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	45	0	0
T2	751	2	0	0
T3	18039	0	0	0
T4	10366	0	0	0
T10	0	1	0	0
T14	0	1	0	0
T21	0	1	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T51	0	1	0	0
T52	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T132	0	1	0	0
T200	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	40	0	0
T2	751	1	0	0
T3	18039	0	0	0
T4	10366	0	0	0
T10	0	1	0	0
T14	0	1	0	0
T21	0	1	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T51	0	1	0	0
T52	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T132	0	1	0	0
T227	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	39	0	0
T2	751	1	0	0
T3	18039	0	0	0
T4	10366	0	0	0
T10	0	1	0	0
T14	0	1	0	0
T21	0	1	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T51	0	1	0	0
T52	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T132	0	1	0	0
T227	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	39	0	0
T2	751	1	0	0
T3	18039	0	0	0
T4	10366	0	0	0
T10	0	1	0	0
T14	0	1	0	0
T21	0	1	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T51	0	1	0	0
T52	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T132	0	1	0	0
T227	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	2987	0	0
T2	751	26	0	0
T3	18039	0	0	0
T4	10366	0	0	0
T10	0	62	0	0
T14	0	11	0	0
T21	0	41	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T51	0	256	0	0
T52	0	38	0	0
T54	0	35	0	0
T55	0	43	0	0
T132	0	81	0	0
T227	0	40	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	6341	0	0
T1	6250	32	0	0
T2	751	2	0	0
T3	18039	11	0	0
T4	10366	14	0	0
T5	15041	12	0	0
T23	408	0	0	0
T24	493	8	0	0
T25	1305	5	0	0
T26	777	0	0	0
T27	10053	20	0	0
T28	0	1	0	0
T29	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5360213	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	19	0	0
T2	751	1	0	0
T3	18039	0	0	0
T4	10366	0	0	0
T10	0	1	0	0
T21	0	1	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T107	0	1	0	0
T159	0	1	0	0
T160	0	2	0	0
T201	0	1	0	0
T248	0	1	0	0
T249	0	1	0	0
T250	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T5,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T8,T10,T14

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T8,T10,T14

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T8,T10,T14

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T10,T14
1	0	Covered	T5,T1,T2
1	1	Covered	T8,T10,T14

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T10,T14
0	1	Covered	T18,T163
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T10,T14
0	1	Covered	T8,T21,T52
1	0	Covered	T14

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T10,T14
1	-	Covered	T8,T21,T52

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T10,T14
DetectSt	168	Covered	T8,T10,T14
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T8,T10,T14

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T10,T14
DebounceSt->IdleSt	163	Covered	T15,T132,T54
DetectSt->IdleSt	186	Covered	T18,T163
DetectSt->StableSt	191	Covered	T8,T10,T14
IdleSt->DebounceSt	148	Covered	T8,T10,T14
StableSt->IdleSt	206	Covered	T8,T14,T18

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T10,T14
0	1	Covered	T8,T10,T14
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T10,T14
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T10,T14
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T83
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T10,T14
DebounceSt	-	0	1	0	-	-	-	Covered	T15,T132,T54
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T10,T14
DetectSt	-	-	-	-	1	-	-	Covered	T18,T163
DetectSt	-	-	-	-	0	1	-	Covered	T8,T10,T14
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T14,T21
StableSt	-	-	-	-	-	-	0	Covered	T8,T10,T14
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6011137	131	0	0
CntIncr_A	6011137	26255	0	0
CntNoWrap_A	6011137	5357760	0	0
DetectStDropOut_A	6011137	2	0	0
DetectedOut_A	6011137	15248	0	0
DetectedPulseOut_A	6011137	61	0	0
DisabledIdleSt_A	6011137	5305876	0	0
DisabledNoDetection_A	6011137	5308145	0	0
EnterDebounceSt_A	6011137	68	0	0
EnterDetectSt_A	6011137	63	0	0
EnterStableSt_A	6011137	61	0	0
PulseIsPulse_A	6011137	61	0	0
StayInStableSt	6011137	15160	0	0
gen_high_level_sva.HighLevelEvent_A	6011137	5360213	0	0
gen_not_sticky_sva.StableStDropOut_A	6011137	33	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	131	0	0
T8	10018	2	0	0
T9	508	0	0	0
T10	834	2	0	0
T11	511	0	0	0
T14	0	2	0	0
T15	0	1	0	0
T18	0	4	0	0
T21	0	2	0	0
T31	4411	0	0	0
T32	505	0	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T45	625	0	0	0
T51	0	2	0	0
T52	0	2	0	0
T132	0	3	0	0
T187	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	26255	0	0
T8	10018	75	0	0
T9	508	0	0	0
T10	834	74	0	0
T11	511	0	0	0
T14	0	35	0	0
T15	0	38	0	0
T18	0	80	0	0
T21	0	86	0	0
T31	4411	0	0	0
T32	505	0	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T45	625	0	0	0
T51	0	74	0	0
T52	0	20	0	0
T132	0	22075	0	0
T187	0	53	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5357760	0	0
T1	6250	2449	0	0
T2	751	350	0	0
T3	18039	17591	0	0
T4	10366	9952	0	0
T5	15041	14612	0	0
T23	408	7	0	0
T24	493	92	0	0
T25	1305	103	0	0
T26	777	376	0	0
T27	10053	9652	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	2	0	0
T18	103663	1	0	0
T19	9205	0	0	0
T49	33572	0	0	0
T50	20160	0	0	0
T59	729	0	0	0
T136	502	0	0	0
T137	8402	0	0	0
T138	486	0	0	0
T139	522	0	0	0
T140	426	0	0	0
T163	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	15248	0	0
T8	10018	22	0	0
T9	508	0	0	0
T10	834	40	0	0
T11	511	0	0	0
T14	0	11	0	0
T18	0	39	0	0
T21	0	47	0	0
T31	4411	0	0	0
T32	505	0	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T45	625	0	0	0
T51	0	40	0	0
T52	0	74	0	0
T53	0	212	0	0
T132	0	9184	0	0
T187	0	116	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	61	0	0
T8	10018	1	0	0
T9	508	0	0	0
T10	834	1	0	0
T11	511	0	0	0
T14	0	1	0	0
T18	0	1	0	0
T21	0	1	0	0
T31	4411	0	0	0
T32	505	0	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T45	625	0	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	2	0	0
T132	0	1	0	0
T187	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5305876	0	0
T1	6250	2449	0	0
T2	751	350	0	0
T3	18039	17591	0	0
T4	10366	9952	0	0
T5	15041	14612	0	0
T23	408	7	0	0
T24	493	92	0	0
T25	1305	103	0	0
T26	777	376	0	0
T27	10053	9652	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5308145	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	68	0	0
T8	10018	1	0	0
T9	508	0	0	0
T10	834	1	0	0
T11	511	0	0	0
T14	0	1	0	0
T15	0	1	0	0
T18	0	2	0	0
T21	0	1	0	0
T31	4411	0	0	0
T32	505	0	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T45	625	0	0	0
T51	0	1	0	0
T52	0	1	0	0
T132	0	2	0	0
T187	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	63	0	0
T8	10018	1	0	0
T9	508	0	0	0
T10	834	1	0	0
T11	511	0	0	0
T14	0	1	0	0
T18	0	2	0	0
T21	0	1	0	0
T31	4411	0	0	0
T32	505	0	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T45	625	0	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	2	0	0
T132	0	1	0	0
T187	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	61	0	0
T8	10018	1	0	0
T9	508	0	0	0
T10	834	1	0	0
T11	511	0	0	0
T14	0	1	0	0
T18	0	1	0	0
T21	0	1	0	0
T31	4411	0	0	0
T32	505	0	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T45	625	0	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	2	0	0
T132	0	1	0	0
T187	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	61	0	0
T8	10018	1	0	0
T9	508	0	0	0
T10	834	1	0	0
T11	511	0	0	0
T14	0	1	0	0
T18	0	1	0	0
T21	0	1	0	0
T31	4411	0	0	0
T32	505	0	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T45	625	0	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	2	0	0
T132	0	1	0	0
T187	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	15160	0	0
T8	10018	21	0	0
T9	508	0	0	0
T10	834	38	0	0
T11	511	0	0	0
T14	0	10	0	0
T18	0	37	0	0
T21	0	46	0	0
T31	4411	0	0	0
T32	505	0	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T45	625	0	0	0
T51	0	38	0	0
T52	0	73	0	0
T53	0	209	0	0
T132	0	9182	0	0
T187	0	115	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5360213	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	33	0	0
T8	10018	1	0	0
T9	508	0	0	0
T10	834	0	0	0
T11	511	0	0	0
T21	0	1	0	0
T31	4411	0	0	0
T32	505	0	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T45	625	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T80	0	1	0	0
T89	0	2	0	0
T157	0	1	0	0
T178	0	1	0	0
T187	0	1	0	0
T227	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T5,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T2,T8,T14

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T2,T8,T14

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T2,T8,T14

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T10
1	0	Covered	T5,T1,T3
1	1	Covered	T2,T8,T14

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T14
0	1	Covered	T166
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T14
0	1	Covered	T2,T53,T89
1	0	Covered	T14

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T8,T14
1	-	Covered	T2,T53,T89

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T8,T14
DetectSt	168	Covered	T2,T8,T14
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T2,T8,T14

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T8,T14
DebounceSt->IdleSt	163	Covered	T157,T89,T110
DetectSt->IdleSt	186	Covered	T166
DetectSt->StableSt	191	Covered	T2,T8,T14
IdleSt->DebounceSt	148	Covered	T2,T8,T14
StableSt->IdleSt	206	Covered	T2,T8,T14

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T8,T14
0	1	Covered	T2,T8,T14
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T14
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T8,T14
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T83
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T8,T14
DebounceSt	-	0	1	0	-	-	-	Covered	T157,T89,T110
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T8,T14
DetectSt	-	-	-	-	1	-	-	Covered	T166
DetectSt	-	-	-	-	0	1	-	Covered	T2,T8,T14
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T14,T53
StableSt	-	-	-	-	-	-	0	Covered	T2,T8,T14
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6011137	98	0	0
CntIncr_A	6011137	33765	0	0
CntNoWrap_A	6011137	5357793	0	0
DetectStDropOut_A	6011137	1	0	0
DetectedOut_A	6011137	37373	0	0
DetectedPulseOut_A	6011137	46	0	0
DisabledIdleSt_A	6011137	5127324	0	0
DisabledNoDetection_A	6011137	5129582	0	0
EnterDebounceSt_A	6011137	51	0	0
EnterDetectSt_A	6011137	47	0	0
EnterStableSt_A	6011137	46	0	0
PulseIsPulse_A	6011137	46	0	0
StayInStableSt	6011137	37298	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6011137	6237	0	0
gen_low_level_sva.LowLevelEvent_A	6011137	5360213	0	0
gen_not_sticky_sva.StableStDropOut_A	6011137	16	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	98	0	0
T2	751	4	0	0
T3	18039	0	0	0
T4	10366	0	0	0
T8	0	2	0	0
T14	0	2	0	0
T20	0	2	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T52	0	2	0	0
T53	0	2	0	0
T79	0	2	0	0
T115	0	2	0	0
T132	0	2	0	0
T164	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	33765	0	0
T2	751	78	0	0
T3	18039	0	0	0
T4	10366	0	0	0
T8	0	75	0	0
T14	0	35	0	0
T20	0	28	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T52	0	20	0	0
T53	0	47	0	0
T79	0	36	0	0
T115	0	66	0	0
T132	0	22	0	0
T164	0	61	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5357793	0	0
T1	6250	2449	0	0
T2	751	346	0	0
T3	18039	17591	0	0
T4	10366	9952	0	0
T5	15041	14612	0	0
T23	408	7	0	0
T24	493	92	0	0
T25	1305	103	0	0
T26	777	376	0	0
T27	10053	9652	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	1	0	0
T113	23774	0	0	0
T166	941	1	0	0
T186	12664	0	0	0
T238	33413	0	0	0
T251	508	0	0	0
T252	544	0	0	0
T253	521	0	0	0
T254	436	0	0	0
T255	5570	0	0	0
T256	526	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	37373	0	0
T2	751	89	0	0
T3	18039	0	0	0
T4	10366	0	0	0
T8	0	41	0	0
T14	0	12	0	0
T20	0	39	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T52	0	39	0	0
T53	0	106	0	0
T79	0	39	0	0
T115	0	36	0	0
T132	0	149	0	0
T164	0	46	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	46	0	0
T2	751	2	0	0
T3	18039	0	0	0
T4	10366	0	0	0
T8	0	1	0	0
T14	0	1	0	0
T20	0	1	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T79	0	1	0	0
T115	0	1	0	0
T132	0	1	0	0
T164	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5127324	0	0
T1	6250	2449	0	0
T2	751	3	0	0
T3	18039	17591	0	0
T4	10366	9952	0	0
T5	15041	14612	0	0
T23	408	7	0	0
T24	493	92	0	0
T25	1305	103	0	0
T26	777	376	0	0
T27	10053	9652	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5129582	0	0
T1	6250	2458	0	0
T2	751	3	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	51	0	0
T2	751	2	0	0
T3	18039	0	0	0
T4	10366	0	0	0
T8	0	1	0	0
T14	0	1	0	0
T20	0	1	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T79	0	1	0	0
T115	0	1	0	0
T132	0	1	0	0
T164	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	47	0	0
T2	751	2	0	0
T3	18039	0	0	0
T4	10366	0	0	0
T8	0	1	0	0
T14	0	1	0	0
T20	0	1	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T79	0	1	0	0
T115	0	1	0	0
T132	0	1	0	0
T164	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	46	0	0
T2	751	2	0	0
T3	18039	0	0	0
T4	10366	0	0	0
T8	0	1	0	0
T14	0	1	0	0
T20	0	1	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T79	0	1	0	0
T115	0	1	0	0
T132	0	1	0	0
T164	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	46	0	0
T2	751	2	0	0
T3	18039	0	0	0
T4	10366	0	0	0
T8	0	1	0	0
T14	0	1	0	0
T20	0	1	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T79	0	1	0	0
T115	0	1	0	0
T132	0	1	0	0
T164	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	37298	0	0
T2	751	86	0	0
T3	18039	0	0	0
T4	10366	0	0	0
T8	0	39	0	0
T14	0	11	0	0
T20	0	37	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T52	0	37	0	0
T53	0	105	0	0
T79	0	37	0	0
T115	0	34	0	0
T132	0	147	0	0
T164	0	44	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	6237	0	0
T1	6250	30	0	0
T2	751	2	0	0
T3	18039	11	0	0
T4	10366	12	0	0
T5	15041	12	0	0
T23	408	0	0	0
T24	493	6	0	0
T25	1305	5	0	0
T26	777	0	0	0
T27	10053	31	0	0
T28	0	3	0	0
T29	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5360213	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	16	0	0
T2	751	1	0	0
T3	18039	0	0	0
T4	10366	0	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T53	0	1	0	0
T89	0	1	0	0
T159	0	1	0	0
T185	0	1	0	0
T201	0	2	0	0
T204	0	1	0	0
T248	0	1	0	0
T250	0	1	0	0
T257	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T5,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T2,T9,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T2,T9,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T2,T9,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T10
1	0	Covered	T5,T1,T3
1	1	Covered	T2,T9,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T10
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T10
0	1	Covered	T9,T10,T15
1	0	Covered	T14

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T9,T10
1	-	Covered	T9,T10,T15

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T9,T10
DetectSt	168	Covered	T2,T9,T10
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T2,T9,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T9,T10
DebounceSt->IdleSt	163	Covered	T2,T157,T108
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T2,T9,T10
IdleSt->DebounceSt	148	Covered	T2,T9,T10
StableSt->IdleSt	206	Covered	T9,T10,T14

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T9,T10
0	1	Covered	T2,T9,T10
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T10
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T9,T10
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T83
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T9,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T157,T108
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T9,T10
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T2,T9,T10
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T10,T14
StableSt	-	-	-	-	-	-	0	Covered	T2,T9,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6011137	110	0	0
CntIncr_A	6011137	97855	0	0
CntNoWrap_A	6011137	5357781	0	0
DetectStDropOut_A	6011137	0	0	0
DetectedOut_A	6011137	24704	0	0
DetectedPulseOut_A	6011137	52	0	0
DisabledIdleSt_A	6011137	5093064	0	0
DisabledNoDetection_A	6011137	5095338	0	0
EnterDebounceSt_A	6011137	58	0	0
EnterDetectSt_A	6011137	52	0	0
EnterStableSt_A	6011137	52	0	0
PulseIsPulse_A	6011137	52	0	0
StayInStableSt	6011137	24626	0	0
gen_high_level_sva.HighLevelEvent_A	6011137	5360213	0	0
gen_not_sticky_sva.StableStDropOut_A	6011137	25	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	110	0	0
T2	751	3	0	0
T3	18039	0	0	0
T4	10366	0	0	0
T9	0	2	0	0
T10	0	2	0	0
T14	0	2	0	0
T15	0	2	0	0
T19	0	4	0	0
T21	0	2	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T51	0	2	0	0
T132	0	6	0	0
T200	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	97855	0	0
T2	751	78	0	0
T3	18039	0	0	0
T4	10366	0	0	0
T9	0	21	0	0
T10	0	74	0	0
T14	0	35	0	0
T15	0	38	0	0
T19	0	196	0	0
T21	0	86	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T51	0	74	0	0
T132	0	22097	0	0
T200	0	93	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5357781	0	0
T1	6250	2449	0	0
T2	751	347	0	0
T3	18039	17591	0	0
T4	10366	9952	0	0
T5	15041	14612	0	0
T23	408	7	0	0
T24	493	92	0	0
T25	1305	103	0	0
T26	777	376	0	0
T27	10053	9652	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	24704	0	0
T2	751	214	0	0
T3	18039	0	0	0
T4	10366	0	0	0
T9	0	16	0	0
T10	0	237	0	0
T14	0	10	0	0
T15	0	36	0	0
T19	0	408	0	0
T21	0	220	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T51	0	28	0	0
T132	0	9289	0	0
T200	0	108	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	52	0	0
T2	751	1	0	0
T3	18039	0	0	0
T4	10366	0	0	0
T9	0	1	0	0
T10	0	1	0	0
T14	0	1	0	0
T15	0	1	0	0
T19	0	2	0	0
T21	0	1	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T51	0	1	0	0
T132	0	3	0	0
T200	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5093064	0	0
T1	6250	2449	0	0
T2	751	3	0	0
T3	18039	17591	0	0
T4	10366	9952	0	0
T5	15041	14612	0	0
T23	408	7	0	0
T24	493	92	0	0
T25	1305	103	0	0
T26	777	376	0	0
T27	10053	9652	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5095338	0	0
T1	6250	2458	0	0
T2	751	3	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	58	0	0
T2	751	2	0	0
T3	18039	0	0	0
T4	10366	0	0	0
T9	0	1	0	0
T10	0	1	0	0
T14	0	1	0	0
T15	0	1	0	0
T19	0	2	0	0
T21	0	1	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T51	0	1	0	0
T132	0	3	0	0
T200	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	52	0	0
T2	751	1	0	0
T3	18039	0	0	0
T4	10366	0	0	0
T9	0	1	0	0
T10	0	1	0	0
T14	0	1	0	0
T15	0	1	0	0
T19	0	2	0	0
T21	0	1	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T51	0	1	0	0
T132	0	3	0	0
T200	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	52	0	0
T2	751	1	0	0
T3	18039	0	0	0
T4	10366	0	0	0
T9	0	1	0	0
T10	0	1	0	0
T14	0	1	0	0
T15	0	1	0	0
T19	0	2	0	0
T21	0	1	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T51	0	1	0	0
T132	0	3	0	0
T200	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	52	0	0
T2	751	1	0	0
T3	18039	0	0	0
T4	10366	0	0	0
T9	0	1	0	0
T10	0	1	0	0
T14	0	1	0	0
T15	0	1	0	0
T19	0	2	0	0
T21	0	1	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T51	0	1	0	0
T132	0	3	0	0
T200	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	24626	0	0
T2	751	212	0	0
T3	18039	0	0	0
T4	10366	0	0	0
T9	0	15	0	0
T10	0	236	0	0
T14	0	9	0	0
T15	0	35	0	0
T19	0	405	0	0
T21	0	219	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T51	0	27	0	0
T132	0	9284	0	0
T200	0	106	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5360213	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	25	0	0
T9	508	1	0	0
T10	834	1	0	0
T11	511	0	0	0
T15	0	1	0	0
T19	0	1	0	0
T21	0	1	0	0
T33	425	0	0	0
T34	526	0	0	0
T35	633	0	0	0
T45	625	0	0	0
T51	0	1	0	0
T62	493	0	0	0
T88	0	1	0	0
T104	0	1	0	0
T132	0	1	0	0
T157	0	1	0	0
T189	605	0	0	0
T190	428	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T5,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T2,T9,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T2,T9,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T2,T9,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T10
1	0	Covered	T5,T1,T3
1	1	Covered	T2,T9,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T10
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T10
0	1	Covered	T2,T18,T157
1	0	Covered	T14

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T9,T10
1	-	Covered	T2,T18,T157

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T9,T10
DetectSt	168	Covered	T2,T9,T10
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T2,T9,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T9,T10
DebounceSt->IdleSt	163	Covered	T88,T217,T83
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T2,T9,T10
IdleSt->DebounceSt	148	Covered	T2,T9,T10
StableSt->IdleSt	206	Covered	T2,T14,T18

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T9,T10
0	1	Covered	T2,T9,T10
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T10
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T9,T10
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T83
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T9,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T88,T217
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T9,T10
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T2,T9,T10
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T14,T18
StableSt	-	-	-	-	-	-	0	Covered	T2,T9,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6011137	73	0	0
CntIncr_A	6011137	31372	0	0
CntNoWrap_A	6011137	5357818	0	0
DetectStDropOut_A	6011137	0	0	0
DetectedOut_A	6011137	3141	0	0
DetectedPulseOut_A	6011137	35	0	0
DisabledIdleSt_A	6011137	5146784	0	0
DisabledNoDetection_A	6011137	5149057	0	0
EnterDebounceSt_A	6011137	38	0	0
EnterDetectSt_A	6011137	35	0	0
EnterStableSt_A	6011137	35	0	0
PulseIsPulse_A	6011137	35	0	0
StayInStableSt	6011137	3086	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6011137	6899	0	0
gen_low_level_sva.LowLevelEvent_A	6011137	5360213	0	0
gen_not_sticky_sva.StableStDropOut_A	6011137	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	73	0	0
T2	751	2	0	0
T3	18039	0	0	0
T4	10366	0	0	0
T9	0	2	0	0
T10	0	2	0	0
T14	0	2	0	0
T18	0	2	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T54	0	2	0	0
T88	0	1	0	0
T157	0	4	0	0
T168	0	2	0	0
T187	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	31372	0	0
T2	751	39	0	0
T3	18039	0	0	0
T4	10366	0	0	0
T9	0	21	0	0
T10	0	74	0	0
T14	0	35	0	0
T18	0	40	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T54	0	97	0	0
T88	0	26271	0	0
T157	0	166	0	0
T168	0	13	0	0
T187	0	53	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5357818	0	0
T1	6250	2449	0	0
T2	751	348	0	0
T3	18039	17591	0	0
T4	10366	9952	0	0
T5	15041	14612	0	0
T23	408	7	0	0
T24	493	92	0	0
T25	1305	103	0	0
T26	777	376	0	0
T27	10053	9652	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	3141	0	0
T2	751	42	0	0
T3	18039	0	0	0
T4	10366	0	0	0
T9	0	40	0	0
T10	0	39	0	0
T14	0	11	0	0
T18	0	43	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T54	0	339	0	0
T157	0	81	0	0
T168	0	43	0	0
T187	0	235	0	0
T258	0	78	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	35	0	0
T2	751	1	0	0
T3	18039	0	0	0
T4	10366	0	0	0
T9	0	1	0	0
T10	0	1	0	0
T14	0	1	0	0
T18	0	1	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T54	0	1	0	0
T157	0	2	0	0
T168	0	1	0	0
T187	0	1	0	0
T258	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5146784	0	0
T1	6250	2449	0	0
T2	751	3	0	0
T3	18039	17591	0	0
T4	10366	9952	0	0
T5	15041	14612	0	0
T23	408	7	0	0
T24	493	92	0	0
T25	1305	103	0	0
T26	777	376	0	0
T27	10053	9652	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5149057	0	0
T1	6250	2458	0	0
T2	751	3	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	38	0	0
T2	751	1	0	0
T3	18039	0	0	0
T4	10366	0	0	0
T9	0	1	0	0
T10	0	1	0	0
T14	0	1	0	0
T18	0	1	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T54	0	1	0	0
T88	0	1	0	0
T157	0	2	0	0
T168	0	1	0	0
T187	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	35	0	0
T2	751	1	0	0
T3	18039	0	0	0
T4	10366	0	0	0
T9	0	1	0	0
T10	0	1	0	0
T14	0	1	0	0
T18	0	1	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T54	0	1	0	0
T157	0	2	0	0
T168	0	1	0	0
T187	0	1	0	0
T258	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	35	0	0
T2	751	1	0	0
T3	18039	0	0	0
T4	10366	0	0	0
T9	0	1	0	0
T10	0	1	0	0
T14	0	1	0	0
T18	0	1	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T54	0	1	0	0
T157	0	2	0	0
T168	0	1	0	0
T187	0	1	0	0
T258	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	35	0	0
T2	751	1	0	0
T3	18039	0	0	0
T4	10366	0	0	0
T9	0	1	0	0
T10	0	1	0	0
T14	0	1	0	0
T18	0	1	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T54	0	1	0	0
T157	0	2	0	0
T168	0	1	0	0
T187	0	1	0	0
T258	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	3086	0	0
T2	751	41	0	0
T3	18039	0	0	0
T4	10366	0	0	0
T9	0	38	0	0
T10	0	37	0	0
T14	0	10	0	0
T18	0	42	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T54	0	337	0	0
T157	0	78	0	0
T168	0	41	0	0
T187	0	233	0	0
T258	0	76	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	6899	0	0
T1	6250	30	0	0
T2	751	1	0	0
T3	18039	12	0	0
T4	10366	12	0	0
T5	15041	12	0	0
T23	408	0	0	0
T24	493	8	0	0
T25	1305	4	0	0
T26	777	3	0	0
T27	10053	30	0	0
T28	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5360213	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	14	0	0
T2	751	1	0	0
T3	18039	0	0	0
T4	10366	0	0	0
T18	0	1	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T157	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0
T185	0	1	0	0
T216	0	1	0	0
T248	0	1	0	0
T249	0	1	0	0
T250	0	1	0	0