Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T27,T48,T6
1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T27,T48,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T27,T48,T6

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T27,T48,T6

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T27,T48,T6
1	0	Covered	T27,T48,T6
1	1	Covered	T27,T48,T6

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T27,T48,T6
0	1	Covered	T13,T14,T17
1	0	Covered	T13,T14,T17

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T27,T48,T6
0	1	Covered	T27,T48,T6
1	0	Covered	T14,T17,T68

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T27,T48,T6
1	-	Covered	T27,T48,T6

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T27,T48,T6
DetectSt	168	Covered	T27,T48,T6
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T27,T48,T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T27,T48,T6
DebounceSt->IdleSt	163	Covered	T14,T259,T260
DetectSt->IdleSt	186	Covered	T13,T14,T17
DetectSt->StableSt	191	Covered	T27,T48,T6
IdleSt->DebounceSt	148	Covered	T27,T48,T6
StableSt->IdleSt	206	Covered	T27,T48,T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T27,T48,T6
0	1	Covered	T27,T48,T6
0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T27,T48,T6
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T27,T48,T6
IdleSt	0	-	-	-	-	-	-	Covered	T27,T48,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T14,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T27,T48,T6
DebounceSt	-	0	1	0	-	-	-	Covered	T14,T259,T260
DebounceSt	-	0	0	-	-	-	-	Covered	T27,T48,T6
DetectSt	-	-	-	-	1	-	-	Covered	T13,T14,T17
DetectSt	-	-	-	-	0	1	-	Covered	T27,T48,T6
DetectSt	-	-	-	-	0	0	-	Covered	T27,T48,T6
StableSt	-	-	-	-	-	-	1	Covered	T27,T48,T6
StableSt	-	-	-	-	-	-	0	Covered	T27,T48,T6
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6011137	2772	0	0
CntIncr_A	6011137	95747	0	0
CntNoWrap_A	6011137	5355119	0	0
DetectStDropOut_A	6011137	411	0	0
DetectedOut_A	6011137	65558	0	0
DetectedPulseOut_A	6011137	812	0	0
DisabledIdleSt_A	6011137	4916093	0	0
DisabledNoDetection_A	6011137	4918234	0	0
EnterDebounceSt_A	6011137	1395	0	0
EnterDetectSt_A	6011137	1377	0	0
EnterStableSt_A	6011137	812	0	0
PulseIsPulse_A	6011137	812	0	0
StayInStableSt	6011137	64657	0	0
gen_high_event_sva.HighLevelEvent_A	6011137	5360213	0	0
gen_high_level_sva.HighLevelEvent_A	6011137	5360213	0	0
gen_not_sticky_sva.StableStDropOut_A	6011137	706	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	2772	0	0
T6	36286	18	0	0
T11	0	2	0	0
T13	0	48	0	0
T14	0	16	0	0
T17	0	58	0	0
T27	10053	22	0	0
T28	418	0	0	0
T29	1232	0	0	0
T46	496	0	0	0
T47	728	0	0	0
T48	30444	24	0	0
T56	10964	34	0	0
T60	755	0	0	0
T61	494	0	0	0
T68	0	26	0	0
T69	0	24	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	95747	0	0
T6	36286	621	0	0
T11	0	21	0	0
T13	0	1598	0	0
T14	0	562	0	0
T17	0	2795	0	0
T27	10053	1012	0	0
T28	418	0	0	0
T29	1232	0	0	0
T46	496	0	0	0
T47	728	0	0	0
T48	30444	780	0	0
T56	10964	952	0	0
T60	755	0	0	0
T61	494	0	0	0
T68	0	923	0	0
T69	0	712	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5355119	0	0
T1	6250	2449	0	0
T2	751	350	0	0
T3	18039	17591	0	0
T4	10366	9952	0	0
T5	15041	14612	0	0
T23	408	7	0	0
T24	493	92	0	0
T25	1305	103	0	0
T26	777	376	0	0
T27	10053	9630	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	411	0	0
T13	20662	7	0	0
T14	8504	1	0	0
T15	671	0	0	0
T16	2986	0	0	0
T17	20177	14	0	0
T57	58412	0	0	0
T63	497	0	0	0
T66	505	0	0	0
T67	524	0	0	0
T69	0	12	0	0
T99	0	12	0	0
T100	0	14	0	0
T102	0	11	0	0
T103	0	10	0	0
T105	0	6	0	0
T259	0	2	0	0
T261	404	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	65558	0	0
T6	36286	728	0	0
T11	0	85	0	0
T14	0	422	0	0
T17	0	5	0	0
T27	10053	324	0	0
T28	418	0	0	0
T29	1232	0	0	0
T46	496	0	0	0
T47	728	0	0	0
T48	30444	852	0	0
T56	10964	931	0	0
T60	755	0	0	0
T61	494	0	0	0
T68	0	125	0	0
T70	0	226	0	0
T262	0	151	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	812	0	0
T6	36286	9	0	0
T11	0	1	0	0
T14	0	5	0	0
T17	0	5	0	0
T27	10053	11	0	0
T28	418	0	0	0
T29	1232	0	0	0
T46	496	0	0	0
T47	728	0	0	0
T48	30444	12	0	0
T56	10964	17	0	0
T60	755	0	0	0
T61	494	0	0	0
T68	0	13	0	0
T70	0	9	0	0
T262	0	5	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	4916093	0	0
T1	6250	2449	0	0
T2	751	350	0	0
T3	18039	17591	0	0
T4	10366	9952	0	0
T5	15041	14612	0	0
T23	408	7	0	0
T24	493	92	0	0
T25	1305	103	0	0
T26	777	376	0	0
T27	10053	3452	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	4918234	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	3452	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	1395	0	0
T6	36286	9	0	0
T11	0	1	0	0
T13	0	24	0	0
T14	0	9	0	0
T17	0	29	0	0
T27	10053	11	0	0
T28	418	0	0	0
T29	1232	0	0	0
T46	496	0	0	0
T47	728	0	0	0
T48	30444	12	0	0
T56	10964	17	0	0
T60	755	0	0	0
T61	494	0	0	0
T68	0	13	0	0
T69	0	12	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	1377	0	0
T6	36286	9	0	0
T11	0	1	0	0
T13	0	24	0	0
T14	0	7	0	0
T17	0	29	0	0
T27	10053	11	0	0
T28	418	0	0	0
T29	1232	0	0	0
T46	496	0	0	0
T47	728	0	0	0
T48	30444	12	0	0
T56	10964	17	0	0
T60	755	0	0	0
T61	494	0	0	0
T68	0	13	0	0
T69	0	12	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	812	0	0
T6	36286	9	0	0
T11	0	1	0	0
T14	0	5	0	0
T17	0	5	0	0
T27	10053	11	0	0
T28	418	0	0	0
T29	1232	0	0	0
T46	496	0	0	0
T47	728	0	0	0
T48	30444	12	0	0
T56	10964	17	0	0
T60	755	0	0	0
T61	494	0	0	0
T68	0	13	0	0
T70	0	9	0	0
T262	0	5	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	812	0	0
T6	36286	9	0	0
T11	0	1	0	0
T14	0	5	0	0
T17	0	5	0	0
T27	10053	11	0	0
T28	418	0	0	0
T29	1232	0	0	0
T46	496	0	0	0
T47	728	0	0	0
T48	30444	12	0	0
T56	10964	17	0	0
T60	755	0	0	0
T61	494	0	0	0
T68	0	13	0	0
T70	0	9	0	0
T262	0	5	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	64657	0	0
T6	36286	718	0	0
T11	0	83	0	0
T14	0	417	0	0
T27	10053	313	0	0
T28	418	0	0	0
T29	1232	0	0	0
T46	496	0	0	0
T47	728	0	0	0
T48	30444	835	0	0
T56	10964	914	0	0
T60	755	0	0	0
T61	494	0	0	0
T68	0	112	0	0
T70	0	217	0	0
T262	0	146	0	0
T263	0	3903	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5360213	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5360213	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	706	0	0
T6	36286	8	0	0
T14	0	4	0	0
T27	10053	11	0	0
T28	418	0	0	0
T29	1232	0	0	0
T46	496	0	0	0
T47	728	0	0	0
T48	30444	7	0	0
T56	10964	17	0	0
T60	755	0	0	0
T61	494	0	0	0
T68	0	3	0	0
T70	0	9	0	0
T262	0	5	0	0
T263	0	27	0	0
T264	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T3
1	Covered	T5,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T3
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T5,T1,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T5,T1,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T5,T1,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T3
1	0	Covered	T5,T1,T3
1	1	Covered	T5,T1,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T3
0	1	Covered	T98,T101,T104
1	0	Covered	T14,T83

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T3
0	1	Covered	T5,T1,T3
1	0	Covered	T83

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T1,T3
1	-	Covered	T5,T1,T3

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T1,T3
DetectSt	168	Covered	T5,T1,T3
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T5,T1,T3

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T1,T3
DebounceSt->IdleSt	163	Covered	T3,T30,T14
DetectSt->IdleSt	186	Covered	T14,T98,T101
DetectSt->StableSt	191	Covered	T5,T1,T3
IdleSt->DebounceSt	148	Covered	T5,T1,T3
StableSt->IdleSt	206	Covered	T5,T1,T3

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T1,T3
0	1	Covered	T5,T1,T3
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T3
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T1,T3
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T14,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T1,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T30,T18
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T1,T3
DetectSt	-	-	-	-	1	-	-	Covered	T14,T98,T101
DetectSt	-	-	-	-	0	1	-	Covered	T5,T1,T3
DetectSt	-	-	-	-	0	0	-	Covered	T5,T1,T3
StableSt	-	-	-	-	-	-	1	Covered	T5,T1,T3
StableSt	-	-	-	-	-	-	0	Covered	T5,T1,T3
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6011137	838	0	0
CntIncr_A	6011137	41035	0	0
CntNoWrap_A	6011137	5357053	0	0
DetectStDropOut_A	6011137	45	0	0
DetectedOut_A	6011137	13175	0	0
DetectedPulseOut_A	6011137	331	0	0
DisabledIdleSt_A	6011137	4994235	0	0
DisabledNoDetection_A	6011137	4995859	0	0
EnterDebounceSt_A	6011137	458	0	0
EnterDetectSt_A	6011137	381	0	0
EnterStableSt_A	6011137	331	0	0
PulseIsPulse_A	6011137	331	0	0
StayInStableSt	6011137	12826	0	0
gen_high_level_sva.HighLevelEvent_A	6011137	5360213	0	0
gen_not_sticky_sva.StableStDropOut_A	6011137	311	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	838	0	0
T1	6250	2	0	0
T2	751	0	0	0
T3	18039	9	0	0
T4	10366	0	0	0
T5	15041	2	0	0
T6	0	2	0	0
T8	0	4	0	0
T11	0	2	0	0
T14	0	8	0	0
T16	0	2	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T30	0	1	0	0
T48	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	41035	0	0
T1	6250	25	0	0
T2	751	0	0	0
T3	18039	290	0	0
T4	10366	0	0	0
T5	15041	104	0	0
T6	0	80	0	0
T8	0	50	0	0
T11	0	25	0	0
T14	0	242	0	0
T16	0	25	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T30	0	20	0	0
T48	0	123	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5357053	0	0
T1	6250	2447	0	0
T2	751	350	0	0
T3	18039	17582	0	0
T4	10366	9952	0	0
T5	15041	14610	0	0
T23	408	7	0	0
T24	493	92	0	0
T25	1305	103	0	0
T26	777	376	0	0
T27	10053	9652	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	45	0	0
T69	5616	0	0	0
T95	756	0	0	0
T98	22001	4	0	0
T101	0	7	0	0
T104	0	4	0	0
T106	0	2	0	0
T107	0	1	0	0
T108	0	9	0	0
T109	0	3	0	0
T110	0	5	0	0
T112	0	3	0	0
T113	0	1	0	0
T115	4082	0	0	0
T116	402	0	0	0
T117	546	0	0	0
T118	534	0	0	0
T119	693	0	0	0
T120	502	0	0	0
T121	495	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	13175	0	0
T1	6250	3	0	0
T2	751	0	0	0
T3	18039	210	0	0
T4	10366	0	0	0
T5	15041	72	0	0
T6	0	34	0	0
T8	0	7	0	0
T11	0	3	0	0
T14	0	108	0	0
T16	0	4	0	0
T19	0	8	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T48	0	170	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	331	0	0
T1	6250	1	0	0
T2	751	0	0	0
T3	18039	4	0	0
T4	10366	0	0	0
T5	15041	1	0	0
T6	0	1	0	0
T8	0	2	0	0
T11	0	1	0	0
T14	0	1	0	0
T16	0	1	0	0
T19	0	2	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T48	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	4994235	0	0
T1	6250	2358	0	0
T2	751	350	0	0
T3	18039	14104	0	0
T4	10366	6044	0	0
T5	15041	10072	0	0
T23	408	7	0	0
T24	493	92	0	0
T25	1305	103	0	0
T26	777	376	0	0
T27	10053	9328	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	4995859	0	0
T1	6250	2366	0	0
T2	751	351	0	0
T3	18039	14104	0	0
T4	10366	6044	0	0
T5	15041	10072	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9329	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	458	0	0
T1	6250	1	0	0
T2	751	0	0	0
T3	18039	5	0	0
T4	10366	0	0	0
T5	15041	1	0	0
T6	0	1	0	0
T8	0	2	0	0
T11	0	1	0	0
T14	0	5	0	0
T16	0	1	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T30	0	1	0	0
T48	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	381	0	0
T1	6250	1	0	0
T2	751	0	0	0
T3	18039	4	0	0
T4	10366	0	0	0
T5	15041	1	0	0
T6	0	1	0	0
T8	0	2	0	0
T11	0	1	0	0
T14	0	3	0	0
T16	0	1	0	0
T19	0	2	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T48	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	331	0	0
T1	6250	1	0	0
T2	751	0	0	0
T3	18039	4	0	0
T4	10366	0	0	0
T5	15041	1	0	0
T6	0	1	0	0
T8	0	2	0	0
T11	0	1	0	0
T14	0	1	0	0
T16	0	1	0	0
T19	0	2	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T48	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	331	0	0
T1	6250	1	0	0
T2	751	0	0	0
T3	18039	4	0	0
T4	10366	0	0	0
T5	15041	1	0	0
T6	0	1	0	0
T8	0	2	0	0
T11	0	1	0	0
T14	0	1	0	0
T16	0	1	0	0
T19	0	2	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T48	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	12826	0	0
T1	6250	2	0	0
T2	751	0	0	0
T3	18039	206	0	0
T4	10366	0	0	0
T5	15041	71	0	0
T6	0	33	0	0
T8	0	5	0	0
T11	0	2	0	0
T14	0	107	0	0
T16	0	3	0	0
T19	0	6	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T48	0	164	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5360213	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	311	0	0
T1	6250	1	0	0
T2	751	0	0	0
T3	18039	4	0	0
T4	10366	0	0	0
T5	15041	1	0	0
T6	0	1	0	0
T8	0	2	0	0
T11	0	1	0	0
T14	0	1	0	0
T16	0	1	0	0
T19	0	2	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T49	0	4	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T27,T48,T6
1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T27,T48,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T27,T48,T6

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T27,T48,T6

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T27,T48,T6
1	0	Covered	T27,T48,T6
1	1	Covered	T27,T48,T6

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T27,T48,T6
0	1	Covered	T14,T69,T99
1	0	Covered	T14,T265,T266

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T27,T48,T6
0	1	Covered	T27,T48,T6
1	0	Covered	T266

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T27,T48,T6
1	-	Covered	T27,T48,T6

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T27,T48,T6
DetectSt	168	Covered	T27,T48,T6
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T27,T48,T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T27,T48,T6
DebounceSt->IdleSt	163	Covered	T14,T259,T260
DetectSt->IdleSt	186	Covered	T14,T69,T99
DetectSt->StableSt	191	Covered	T27,T48,T6
IdleSt->DebounceSt	148	Covered	T27,T48,T6
StableSt->IdleSt	206	Covered	T27,T48,T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T27,T48,T6
0	1	Covered	T27,T48,T6
0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T27,T48,T6
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T27,T48,T6
IdleSt	0	-	-	-	-	-	-	Covered	T27,T48,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T14,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T27,T48,T6
DebounceSt	-	0	1	0	-	-	-	Covered	T14,T259,T260
DebounceSt	-	0	0	-	-	-	-	Covered	T27,T48,T6
DetectSt	-	-	-	-	1	-	-	Covered	T14,T69,T99
DetectSt	-	-	-	-	0	1	-	Covered	T27,T48,T6
DetectSt	-	-	-	-	0	0	-	Covered	T27,T48,T6
StableSt	-	-	-	-	-	-	1	Covered	T27,T48,T6
StableSt	-	-	-	-	-	-	0	Covered	T27,T48,T6
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6011137	2953	0	0
CntIncr_A	6011137	95227	0	0
CntNoWrap_A	6011137	5354938	0	0
DetectStDropOut_A	6011137	460	0	0
DetectedOut_A	6011137	73130	0	0
DetectedPulseOut_A	6011137	843	0	0
DisabledIdleSt_A	6011137	4912407	0	0
DisabledNoDetection_A	6011137	4914546	0	0
EnterDebounceSt_A	6011137	1487	0	0
EnterDetectSt_A	6011137	1467	0	0
EnterStableSt_A	6011137	843	0	0
PulseIsPulse_A	6011137	843	0	0
StayInStableSt	6011137	72197	0	0
gen_high_event_sva.HighLevelEvent_A	6011137	5360213	0	0
gen_high_level_sva.HighLevelEvent_A	6011137	5360213	0	0
gen_not_sticky_sva.StableStDropOut_A	6011137	744	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	2953	0	0
T6	36286	34	0	0
T13	0	18	0	0
T14	0	16	0	0
T17	0	30	0	0
T27	10053	40	0	0
T28	418	0	0	0
T29	1232	0	0	0
T46	496	0	0	0
T47	728	0	0	0
T48	30444	16	0	0
T56	10964	6	0	0
T60	755	0	0	0
T61	494	0	0	0
T68	0	30	0	0
T69	0	62	0	0
T70	0	38	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	95227	0	0
T6	36286	1173	0	0
T13	0	522	0	0
T14	0	674	0	0
T17	0	990	0	0
T27	10053	1820	0	0
T28	418	0	0	0
T29	1232	0	0	0
T46	496	0	0	0
T47	728	0	0	0
T48	30444	368	0	0
T56	10964	264	0	0
T60	755	0	0	0
T61	494	0	0	0
T68	0	870	0	0
T69	0	1863	0	0
T70	0	570	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5354938	0	0
T1	6250	2449	0	0
T2	751	350	0	0
T3	18039	17591	0	0
T4	10366	9952	0	0
T5	15041	14612	0	0
T23	408	7	0	0
T24	493	92	0	0
T25	1305	103	0	0
T26	777	376	0	0
T27	10053	9612	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	460	0	0
T14	8504	1	0	0
T15	671	0	0	0
T16	2986	0	0	0
T17	20177	0	0	0
T18	103663	0	0	0
T57	58412	0	0	0
T58	713	0	0	0
T66	505	0	0	0
T67	524	0	0	0
T69	0	31	0	0
T99	0	17	0	0
T100	0	28	0	0
T102	0	22	0	0
T103	0	30	0	0
T206	423	0	0	0
T259	0	4	0	0
T265	0	5	0	0
T267	0	4	0	0
T268	0	18	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	73130	0	0
T6	36286	2227	0	0
T13	0	97	0	0
T14	0	509	0	0
T17	0	1681	0	0
T27	10053	1957	0	0
T28	418	0	0	0
T29	1232	0	0	0
T46	496	0	0	0
T47	728	0	0	0
T48	30444	1086	0	0
T56	10964	12	0	0
T60	755	0	0	0
T61	494	0	0	0
T68	0	1495	0	0
T70	0	1441	0	0
T262	0	2290	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	843	0	0
T6	36286	17	0	0
T13	0	9	0	0
T14	0	5	0	0
T17	0	15	0	0
T27	10053	20	0	0
T28	418	0	0	0
T29	1232	0	0	0
T46	496	0	0	0
T47	728	0	0	0
T48	30444	8	0	0
T56	10964	3	0	0
T60	755	0	0	0
T61	494	0	0	0
T68	0	15	0	0
T70	0	19	0	0
T262	0	25	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	4912407	0	0
T1	6250	2449	0	0
T2	751	350	0	0
T3	18039	17591	0	0
T4	10366	9952	0	0
T5	15041	14612	0	0
T23	408	7	0	0
T24	493	92	0	0
T25	1305	103	0	0
T26	777	376	0	0
T27	10053	2081	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	4914546	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	2081	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	1487	0	0
T6	36286	17	0	0
T13	0	9	0	0
T14	0	9	0	0
T17	0	15	0	0
T27	10053	20	0	0
T28	418	0	0	0
T29	1232	0	0	0
T46	496	0	0	0
T47	728	0	0	0
T48	30444	8	0	0
T56	10964	3	0	0
T60	755	0	0	0
T61	494	0	0	0
T68	0	15	0	0
T69	0	31	0	0
T70	0	19	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	1467	0	0
T6	36286	17	0	0
T13	0	9	0	0
T14	0	7	0	0
T17	0	15	0	0
T27	10053	20	0	0
T28	418	0	0	0
T29	1232	0	0	0
T46	496	0	0	0
T47	728	0	0	0
T48	30444	8	0	0
T56	10964	3	0	0
T60	755	0	0	0
T61	494	0	0	0
T68	0	15	0	0
T69	0	31	0	0
T70	0	19	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	843	0	0
T6	36286	17	0	0
T13	0	9	0	0
T14	0	5	0	0
T17	0	15	0	0
T27	10053	20	0	0
T28	418	0	0	0
T29	1232	0	0	0
T46	496	0	0	0
T47	728	0	0	0
T48	30444	8	0	0
T56	10964	3	0	0
T60	755	0	0	0
T61	494	0	0	0
T68	0	15	0	0
T70	0	19	0	0
T262	0	25	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	843	0	0
T6	36286	17	0	0
T13	0	9	0	0
T14	0	5	0	0
T17	0	15	0	0
T27	10053	20	0	0
T28	418	0	0	0
T29	1232	0	0	0
T46	496	0	0	0
T47	728	0	0	0
T48	30444	8	0	0
T56	10964	3	0	0
T60	755	0	0	0
T61	494	0	0	0
T68	0	15	0	0
T70	0	19	0	0
T262	0	25	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	72197	0	0
T6	36286	2206	0	0
T13	0	88	0	0
T14	0	504	0	0
T17	0	1663	0	0
T27	10053	1937	0	0
T28	418	0	0	0
T29	1232	0	0	0
T46	496	0	0	0
T47	728	0	0	0
T48	30444	1073	0	0
T56	10964	9	0	0
T60	755	0	0	0
T61	494	0	0	0
T68	0	1477	0	0
T70	0	1422	0	0
T262	0	2265	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5360213	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5360213	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	744	0	0
T6	36286	13	0	0
T13	0	9	0	0
T14	0	5	0	0
T17	0	12	0	0
T27	10053	20	0	0
T28	418	0	0	0
T29	1232	0	0	0
T46	496	0	0	0
T47	728	0	0	0
T48	30444	3	0	0
T56	10964	3	0	0
T60	755	0	0	0
T61	494	0	0	0
T68	0	12	0	0
T70	0	19	0	0
T262	0	25	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T3,T4
1	Covered	T5,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T3,T4
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T5,T3,T4

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T5,T3,T4

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T5,T3,T4

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T3,T4
1	0	Covered	T5,T1,T3
1	1	Covered	T5,T3,T4

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T3,T4
0	1	Covered	T82,T187,T269
1	0	Covered	T14,T83

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T3,T4
0	1	Covered	T5,T3,T4
1	0	Covered	T14,T85,T83

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T3,T4
1	-	Covered	T5,T3,T4

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T3,T4
DetectSt	168	Covered	T5,T3,T4
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T5,T3,T4

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T3,T4
DebounceSt->IdleSt	163	Covered	T3,T12,T14
DetectSt->IdleSt	186	Covered	T14,T82,T187
DetectSt->StableSt	191	Covered	T5,T3,T4
IdleSt->DebounceSt	148	Covered	T5,T3,T4
StableSt->IdleSt	206	Covered	T5,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T3,T4
0	1	Covered	T5,T3,T4
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T3,T4
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T3,T4
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T14,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T3,T4
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T12,T49
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T3,T4
DetectSt	-	-	-	-	1	-	-	Covered	T14,T82,T187
DetectSt	-	-	-	-	0	1	-	Covered	T5,T3,T4
DetectSt	-	-	-	-	0	0	-	Covered	T5,T3,T4
StableSt	-	-	-	-	-	-	1	Covered	T5,T3,T4
StableSt	-	-	-	-	-	-	0	Covered	T5,T3,T4
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6011137	940	0	0
CntIncr_A	6011137	49319	0	0
CntNoWrap_A	6011137	5356951	0	0
DetectStDropOut_A	6011137	78	0	0
DetectedOut_A	6011137	16409	0	0
DetectedPulseOut_A	6011137	366	0	0
DisabledIdleSt_A	6011137	4990173	0	0
DisabledNoDetection_A	6011137	4991846	0	0
EnterDebounceSt_A	6011137	492	0	0
EnterDetectSt_A	6011137	448	0	0
EnterStableSt_A	6011137	366	0	0
PulseIsPulse_A	6011137	366	0	0
StayInStableSt	6011137	16012	0	0
gen_high_level_sva.HighLevelEvent_A	6011137	5360213	0	0
gen_not_sticky_sva.StableStDropOut_A	6011137	331	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	940	0	0
T1	6250	0	0	0
T2	751	0	0	0
T3	18039	9	0	0
T4	10366	12	0	0
T5	15041	8	0	0
T6	0	8	0	0
T12	0	16	0	0
T14	0	8	0	0
T17	0	2	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T48	0	10	0	0
T49	0	25	0	0
T50	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	49319	0	0
T1	6250	0	0	0
T2	751	0	0	0
T3	18039	278	0	0
T4	10366	468	0	0
T5	15041	668	0	0
T6	0	260	0	0
T12	0	674	0	0
T14	0	333	0	0
T17	0	76	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T48	0	195	0	0
T49	0	1569	0	0
T50	0	212	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5356951	0	0
T1	6250	2449	0	0
T2	751	350	0	0
T3	18039	17582	0	0
T4	10366	9940	0	0
T5	15041	14604	0	0
T23	408	7	0	0
T24	493	92	0	0
T25	1305	103	0	0
T26	777	376	0	0
T27	10053	9652	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	78	0	0
T69	5616	0	0	0
T82	8507	4	0	0
T98	22001	0	0	0
T104	0	3	0	0
T107	0	4	0	0
T115	4082	0	0	0
T116	402	0	0	0
T117	546	0	0	0
T118	534	0	0	0
T176	0	3	0	0
T187	0	7	0	0
T200	0	1	0	0
T269	0	3	0	0
T270	0	4	0	0
T271	0	3	0	0
T272	0	3	0	0
T273	526	0	0	0
T274	506	0	0	0
T275	595	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	16409	0	0
T1	6250	0	0	0
T2	751	0	0	0
T3	18039	224	0	0
T4	10366	395	0	0
T5	15041	37	0	0
T6	0	197	0	0
T12	0	553	0	0
T14	0	108	0	0
T17	0	88	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T48	0	292	0	0
T49	0	73	0	0
T50	0	10	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	366	0	0
T1	6250	0	0	0
T2	751	0	0	0
T3	18039	4	0	0
T4	10366	6	0	0
T5	15041	4	0	0
T6	0	4	0	0
T12	0	7	0	0
T14	0	1	0	0
T17	0	1	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T48	0	5	0	0
T49	0	12	0	0
T50	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	4990173	0	0
T1	6250	2449	0	0
T2	751	350	0	0
T3	18039	14104	0	0
T4	10366	6044	0	0
T5	15041	10072	0	0
T23	408	7	0	0
T24	493	92	0	0
T25	1305	103	0	0
T26	777	376	0	0
T27	10053	7695	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	4991846	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	14104	0	0
T4	10366	6044	0	0
T5	15041	10072	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	7696	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	492	0	0
T1	6250	0	0	0
T2	751	0	0	0
T3	18039	5	0	0
T4	10366	6	0	0
T5	15041	4	0	0
T6	0	4	0	0
T12	0	9	0	0
T14	0	5	0	0
T17	0	1	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T48	0	5	0	0
T49	0	13	0	0
T50	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	448	0	0
T1	6250	0	0	0
T2	751	0	0	0
T3	18039	4	0	0
T4	10366	6	0	0
T5	15041	4	0	0
T6	0	4	0	0
T12	0	7	0	0
T14	0	3	0	0
T17	0	1	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T48	0	5	0	0
T49	0	12	0	0
T50	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	366	0	0
T1	6250	0	0	0
T2	751	0	0	0
T3	18039	4	0	0
T4	10366	6	0	0
T5	15041	4	0	0
T6	0	4	0	0
T12	0	7	0	0
T14	0	1	0	0
T17	0	1	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T48	0	5	0	0
T49	0	12	0	0
T50	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	366	0	0
T1	6250	0	0	0
T2	751	0	0	0
T3	18039	4	0	0
T4	10366	6	0	0
T5	15041	4	0	0
T6	0	4	0	0
T12	0	7	0	0
T14	0	1	0	0
T17	0	1	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T48	0	5	0	0
T49	0	12	0	0
T50	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	16012	0	0
T1	6250	0	0	0
T2	751	0	0	0
T3	18039	220	0	0
T4	10366	389	0	0
T5	15041	33	0	0
T6	0	193	0	0
T12	0	546	0	0
T14	0	107	0	0
T17	0	86	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T48	0	282	0	0
T49	0	61	0	0
T50	0	8	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5360213	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	331	0	0
T1	6250	0	0	0
T2	751	0	0	0
T3	18039	4	0	0
T4	10366	6	0	0
T5	15041	4	0	0
T6	0	4	0	0
T12	0	7	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T49	0	12	0	0
T50	0	2	0	0
T68	0	2	0	0
T98	0	14	0	0
T276	0	7	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T27,T48,T6
1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T27,T48,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T27,T48,T6

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T27,T48,T6

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T27,T48,T6
1	0	Covered	T27,T48,T6
1	1	Covered	T27,T48,T6

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T27,T48,T6
0	1	Covered	T14,T69,T70
1	0	Covered	T14,T70,T85

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T27,T48,T6
0	1	Covered	T27,T48,T6
1	0	Covered	T83

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T27,T48,T6
1	-	Covered	T27,T48,T6

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T27,T48,T6
DetectSt	168	Covered	T27,T48,T6
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T27,T48,T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T27,T48,T6
DebounceSt->IdleSt	163	Covered	T14,T259,T260
DetectSt->IdleSt	186	Covered	T14,T69,T70
DetectSt->StableSt	191	Covered	T27,T48,T6
IdleSt->DebounceSt	148	Covered	T27,T48,T6
StableSt->IdleSt	206	Covered	T27,T48,T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T27,T48,T6
0	1	Covered	T27,T48,T6
0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T27,T48,T6
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T27,T48,T6
IdleSt	0	-	-	-	-	-	-	Covered	T27,T48,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T14,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T27,T48,T6
DebounceSt	-	0	1	0	-	-	-	Covered	T14,T259,T260
DebounceSt	-	0	0	-	-	-	-	Covered	T27,T48,T6
DetectSt	-	-	-	-	1	-	-	Covered	T14,T69,T70
DetectSt	-	-	-	-	0	1	-	Covered	T27,T48,T6
DetectSt	-	-	-	-	0	0	-	Covered	T27,T48,T6
StableSt	-	-	-	-	-	-	1	Covered	T27,T48,T6
StableSt	-	-	-	-	-	-	0	Covered	T27,T48,T6
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6011137	3251	0	0
CntIncr_A	6011137	108562	0	0
CntNoWrap_A	6011137	5354640	0	0
DetectStDropOut_A	6011137	515	0	0
DetectedOut_A	6011137	91663	0	0
DetectedPulseOut_A	6011137	1000	0	0
DisabledIdleSt_A	6011137	4899280	0	0
DisabledNoDetection_A	6011137	4901387	0	0
EnterDebounceSt_A	6011137	1634	0	0
EnterDetectSt_A	6011137	1617	0	0
EnterStableSt_A	6011137	1000	0	0
PulseIsPulse_A	6011137	1000	0	0
StayInStableSt	6011137	90539	0	0
gen_high_event_sva.HighLevelEvent_A	6011137	5360213	0	0
gen_high_level_sva.HighLevelEvent_A	6011137	5360213	0	0
gen_not_sticky_sva.StableStDropOut_A	6011137	875	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	3251	0	0
T6	36286	62	0	0
T13	0	22	0	0
T14	0	16	0	0
T17	0	18	0	0
T27	10053	56	0	0
T28	418	0	0	0
T29	1232	0	0	0
T46	496	0	0	0
T47	728	0	0	0
T48	30444	50	0	0
T56	10964	46	0	0
T60	755	0	0	0
T61	494	0	0	0
T68	0	50	0	0
T69	0	26	0	0
T70	0	44	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	108562	0	0
T6	36286	2449	0	0
T13	0	528	0	0
T14	0	564	0	0
T17	0	675	0	0
T27	10053	1904	0	0
T28	418	0	0	0
T29	1232	0	0	0
T46	496	0	0	0
T47	728	0	0	0
T48	30444	1000	0	0
T56	10964	1794	0	0
T60	755	0	0	0
T61	494	0	0	0
T68	0	1200	0	0
T69	0	775	0	0
T70	0	1042	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5354640	0	0
T1	6250	2449	0	0
T2	751	350	0	0
T3	18039	17591	0	0
T4	10366	9952	0	0
T5	15041	14612	0	0
T23	408	7	0	0
T24	493	92	0	0
T25	1305	103	0	0
T26	777	376	0	0
T27	10053	9596	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	515	0	0
T14	8504	1	0	0
T15	671	0	0	0
T16	2986	0	0	0
T17	20177	0	0	0
T18	103663	0	0	0
T57	58412	0	0	0
T58	713	0	0	0
T66	505	0	0	0
T67	524	0	0	0
T69	0	13	0	0
T70	0	9	0	0
T99	0	12	0	0
T100	0	28	0	0
T102	0	14	0	0
T103	0	31	0	0
T105	0	18	0	0
T206	423	0	0	0
T259	0	10	0	0
T267	0	7	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	91663	0	0
T6	36286	3770	0	0
T13	0	1302	0	0
T14	0	506	0	0
T17	0	1234	0	0
T27	10053	1506	0	0
T28	418	0	0	0
T29	1232	0	0	0
T46	496	0	0	0
T47	728	0	0	0
T48	30444	2349	0	0
T56	10964	2037	0	0
T60	755	0	0	0
T61	494	0	0	0
T68	0	2389	0	0
T262	0	161	0	0
T263	0	1245	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	1000	0	0
T6	36286	31	0	0
T13	0	11	0	0
T14	0	5	0	0
T17	0	9	0	0
T27	10053	28	0	0
T28	418	0	0	0
T29	1232	0	0	0
T46	496	0	0	0
T47	728	0	0	0
T48	30444	25	0	0
T56	10964	23	0	0
T60	755	0	0	0
T61	494	0	0	0
T68	0	25	0	0
T262	0	3	0	0
T263	0	22	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	4899280	0	0
T1	6250	2449	0	0
T2	751	350	0	0
T3	18039	17591	0	0
T4	10366	9952	0	0
T5	15041	14612	0	0
T23	408	7	0	0
T24	493	92	0	0
T25	1305	103	0	0
T26	777	376	0	0
T27	10053	3394	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	4901387	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	3394	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	1634	0	0
T6	36286	31	0	0
T13	0	11	0	0
T14	0	9	0	0
T17	0	9	0	0
T27	10053	28	0	0
T28	418	0	0	0
T29	1232	0	0	0
T46	496	0	0	0
T47	728	0	0	0
T48	30444	25	0	0
T56	10964	23	0	0
T60	755	0	0	0
T61	494	0	0	0
T68	0	25	0	0
T69	0	13	0	0
T70	0	22	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	1617	0	0
T6	36286	31	0	0
T13	0	11	0	0
T14	0	7	0	0
T17	0	9	0	0
T27	10053	28	0	0
T28	418	0	0	0
T29	1232	0	0	0
T46	496	0	0	0
T47	728	0	0	0
T48	30444	25	0	0
T56	10964	23	0	0
T60	755	0	0	0
T61	494	0	0	0
T68	0	25	0	0
T69	0	13	0	0
T70	0	22	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	1000	0	0
T6	36286	31	0	0
T13	0	11	0	0
T14	0	5	0	0
T17	0	9	0	0
T27	10053	28	0	0
T28	418	0	0	0
T29	1232	0	0	0
T46	496	0	0	0
T47	728	0	0	0
T48	30444	25	0	0
T56	10964	23	0	0
T60	755	0	0	0
T61	494	0	0	0
T68	0	25	0	0
T262	0	3	0	0
T263	0	22	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	1000	0	0
T6	36286	31	0	0
T13	0	11	0	0
T14	0	5	0	0
T17	0	9	0	0
T27	10053	28	0	0
T28	418	0	0	0
T29	1232	0	0	0
T46	496	0	0	0
T47	728	0	0	0
T48	30444	25	0	0
T56	10964	23	0	0
T60	755	0	0	0
T61	494	0	0	0
T68	0	25	0	0
T262	0	3	0	0
T263	0	22	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	90539	0	0
T6	36286	3729	0	0
T13	0	1290	0	0
T14	0	501	0	0
T17	0	1223	0	0
T27	10053	1478	0	0
T28	418	0	0	0
T29	1232	0	0	0
T46	496	0	0	0
T47	728	0	0	0
T48	30444	2316	0	0
T56	10964	2013	0	0
T60	755	0	0	0
T61	494	0	0	0
T68	0	2360	0	0
T262	0	158	0	0
T263	0	1222	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5360213	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5360213	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	875	0	0
T6	36286	21	0	0
T13	0	10	0	0
T14	0	5	0	0
T17	0	7	0	0
T27	10053	28	0	0
T28	418	0	0	0
T29	1232	0	0	0
T46	496	0	0	0
T47	728	0	0	0
T48	30444	17	0	0
T56	10964	22	0	0
T60	755	0	0	0
T61	494	0	0	0
T68	0	21	0	0
T262	0	3	0	0
T263	0	21	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T3,T4
1	Covered	T5,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T3,T4
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T5,T3,T4

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T5,T3,T4

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T5,T3,T4

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T3,T4
1	0	Covered	T5,T1,T3
1	1	Covered	T5,T3,T4

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T3,T4
0	1	Covered	T5,T50,T82
1	0	Covered	T14,T83

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T48
0	1	Covered	T3,T4,T6
1	0	Covered	T14,T86

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T4,T48
1	-	Covered	T3,T4,T6

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T3,T4
DetectSt	168	Covered	T5,T3,T4
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T3,T4,T48

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T3,T4
DebounceSt->IdleSt	163	Covered	T5,T14,T49
DetectSt->IdleSt	186	Covered	T5,T14,T50
DetectSt->StableSt	191	Covered	T3,T4,T48
IdleSt->DebounceSt	148	Covered	T5,T3,T4
StableSt->IdleSt	206	Covered	T3,T4,T48

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T3,T4
0	1	Covered	T5,T3,T4
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T3,T4
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T3,T4
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T14,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T3,T4
DebounceSt	-	0	1	0	-	-	-	Covered	T5,T49,T50
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T3,T4
DetectSt	-	-	-	-	1	-	-	Covered	T5,T14,T50
DetectSt	-	-	-	-	0	1	-	Covered	T3,T4,T48
DetectSt	-	-	-	-	0	0	-	Covered	T5,T3,T4
StableSt	-	-	-	-	-	-	1	Covered	T3,T4,T6
StableSt	-	-	-	-	-	-	0	Covered	T3,T4,T48
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6011137	818	0	0
CntIncr_A	6011137	43626	0	0
CntNoWrap_A	6011137	5357073	0	0
DetectStDropOut_A	6011137	81	0	0
DetectedOut_A	6011137	15897	0	0
DetectedPulseOut_A	6011137	306	0	0
DisabledIdleSt_A	6011137	4976240	0	0
DisabledNoDetection_A	6011137	4977883	0	0
EnterDebounceSt_A	6011137	427	0	0
EnterDetectSt_A	6011137	391	0	0
EnterStableSt_A	6011137	306	0	0
PulseIsPulse_A	6011137	306	0	0
StayInStableSt	6011137	15536	0	0
gen_high_level_sva.HighLevelEvent_A	6011137	5360213	0	0
gen_not_sticky_sva.StableStDropOut_A	6011137	249	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	818	0	0
T1	6250	0	0	0
T2	751	0	0	0
T3	18039	2	0	0
T4	10366	4	0	0
T5	15041	11	0	0
T6	0	20	0	0
T12	0	2	0	0
T13	0	2	0	0
T14	0	8	0	0
T17	0	4	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T48	0	16	0	0
T56	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	43626	0	0
T1	6250	0	0	0
T2	751	0	0	0
T3	18039	109	0	0
T4	10366	248	0	0
T5	15041	972	0	0
T6	0	850	0	0
T12	0	139	0	0
T13	0	53	0	0
T14	0	329	0	0
T17	0	172	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T48	0	360	0	0
T56	0	57	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5357073	0	0
T1	6250	2449	0	0
T2	751	350	0	0
T3	18039	17589	0	0
T4	10366	9948	0	0
T5	15041	14601	0	0
T23	408	7	0	0
T24	493	92	0	0
T25	1305	103	0	0
T26	777	376	0	0
T27	10053	9652	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	81	0	0
T1	6250	0	0	0
T2	751	0	0	0
T3	18039	0	0	0
T4	10366	0	0	0
T5	15041	5	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T50	0	1	0	0
T82	0	1	0	0
T104	0	3	0	0
T106	0	7	0	0
T176	0	11	0	0
T200	0	1	0	0
T277	0	1	0	0
T278	0	1	0	0
T279	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	15897	0	0
T3	18039	10	0	0
T4	10366	39	0	0
T6	0	286	0	0
T12	0	19	0	0
T13	0	96	0	0
T14	0	108	0	0
T17	0	160	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T48	30444	421	0	0
T49	0	28	0	0
T56	0	92	0	0
T60	755	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	306	0	0
T3	18039	1	0	0
T4	10366	2	0	0
T6	0	10	0	0
T12	0	1	0	0
T13	0	1	0	0
T14	0	1	0	0
T17	0	2	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T48	30444	8	0	0
T49	0	2	0	0
T56	0	1	0	0
T60	755	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	4976240	0	0
T1	6250	2449	0	0
T2	751	350	0	0
T3	18039	14104	0	0
T4	10366	6044	0	0
T5	15041	10072	0	0
T23	408	7	0	0
T24	493	92	0	0
T25	1305	103	0	0
T26	777	376	0	0
T27	10053	8146	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	4977883	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	14104	0	0
T4	10366	6044	0	0
T5	15041	10072	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	8147	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	427	0	0
T1	6250	0	0	0
T2	751	0	0	0
T3	18039	1	0	0
T4	10366	2	0	0
T5	15041	6	0	0
T6	0	10	0	0
T12	0	1	0	0
T13	0	1	0	0
T14	0	5	0	0
T17	0	2	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T48	0	8	0	0
T56	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	391	0	0
T1	6250	0	0	0
T2	751	0	0	0
T3	18039	1	0	0
T4	10366	2	0	0
T5	15041	5	0	0
T6	0	10	0	0
T12	0	1	0	0
T13	0	1	0	0
T14	0	3	0	0
T17	0	2	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T48	0	8	0	0
T56	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	306	0	0
T3	18039	1	0	0
T4	10366	2	0	0
T6	0	10	0	0
T12	0	1	0	0
T13	0	1	0	0
T14	0	1	0	0
T17	0	2	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T48	30444	8	0	0
T49	0	2	0	0
T56	0	1	0	0
T60	755	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	306	0	0
T3	18039	1	0	0
T4	10366	2	0	0
T6	0	10	0	0
T12	0	1	0	0
T13	0	1	0	0
T14	0	1	0	0
T17	0	2	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T48	30444	8	0	0
T49	0	2	0	0
T56	0	1	0	0
T60	755	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	15536	0	0
T3	18039	9	0	0
T4	10366	37	0	0
T6	0	268	0	0
T12	0	18	0	0
T13	0	95	0	0
T14	0	107	0	0
T17	0	158	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T48	30444	405	0	0
T49	0	26	0	0
T56	0	90	0	0
T60	755	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5360213	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	249	0	0
T3	18039	1	0	0
T4	10366	2	0	0
T6	0	2	0	0
T12	0	1	0	0
T13	0	1	0	0
T17	0	2	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T28	418	0	0	0
T29	1232	0	0	0
T48	30444	0	0	0
T49	0	2	0	0
T60	755	0	0	0
T68	0	4	0	0
T98	0	6	0	0
T276	0	1	0	0