Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T27,T48,T6
1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T27,T48,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T27,T48,T6

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T27,T48,T6

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T27,T48,T6
1	0	Covered	T27,T48,T6
1	1	Covered	T27,T48,T6

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T27,T48,T6
0	1	Covered	T6,T14,T69
1	0	Covered	T6,T14,T70

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T27,T48,T56
0	1	Covered	T27,T48,T56
1	0	Covered	T78,T83

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T27,T48,T56
1	-	Covered	T27,T48,T56

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T27,T48,T6
DetectSt	168	Covered	T27,T48,T6
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T27,T48,T56

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T27,T48,T6
DebounceSt->IdleSt	163	Covered	T14,T259,T260
DetectSt->IdleSt	186	Covered	T6,T14,T69
DetectSt->StableSt	191	Covered	T27,T48,T56
IdleSt->DebounceSt	148	Covered	T27,T48,T6
StableSt->IdleSt	206	Covered	T27,T48,T56

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T27,T48,T6
0	1	Covered	T27,T48,T6
0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T27,T48,T6
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T27,T48,T6
IdleSt	0	-	-	-	-	-	-	Covered	T27,T48,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T14,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T27,T48,T6
DebounceSt	-	0	1	0	-	-	-	Covered	T14,T259,T260
DebounceSt	-	0	0	-	-	-	-	Covered	T27,T48,T6
DetectSt	-	-	-	-	1	-	-	Covered	T6,T14,T69
DetectSt	-	-	-	-	0	1	-	Covered	T27,T48,T56
DetectSt	-	-	-	-	0	0	-	Covered	T27,T48,T6
StableSt	-	-	-	-	-	-	1	Covered	T27,T48,T56
StableSt	-	-	-	-	-	-	0	Covered	T27,T48,T56
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6011137	3025	0	0
CntIncr_A	6011137	101618	0	0
CntNoWrap_A	6011137	5354866	0	0
DetectStDropOut_A	6011137	447	0	0
DetectedOut_A	6011137	79347	0	0
DetectedPulseOut_A	6011137	929	0	0
DisabledIdleSt_A	6011137	4903928	0	0
DisabledNoDetection_A	6011137	4906045	0	0
EnterDebounceSt_A	6011137	1524	0	0
EnterDetectSt_A	6011137	1502	0	0
EnterStableSt_A	6011137	929	0	0
PulseIsPulse_A	6011137	929	0	0
StayInStableSt	6011137	78306	0	0
gen_high_event_sva.HighLevelEvent_A	6011137	5360213	0	0
gen_high_level_sva.HighLevelEvent_A	6011137	5360213	0	0
gen_not_sticky_sva.StableStDropOut_A	6011137	809	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	3025	0	0
T6	36286	52	0	0
T13	0	50	0	0
T14	0	16	0	0
T17	0	50	0	0
T27	10053	30	0	0
T28	418	0	0	0
T29	1232	0	0	0
T46	496	0	0	0
T47	728	0	0	0
T48	30444	34	0	0
T56	10964	18	0	0
T60	755	0	0	0
T61	494	0	0	0
T68	0	26	0	0
T69	0	20	0	0
T70	0	40	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	101618	0	0
T6	36286	3482	0	0
T13	0	1225	0	0
T14	0	709	0	0
T17	0	2000	0	0
T27	10053	900	0	0
T28	418	0	0	0
T29	1232	0	0	0
T46	496	0	0	0
T47	728	0	0	0
T48	30444	714	0	0
T56	10964	801	0	0
T60	755	0	0	0
T61	494	0	0	0
T68	0	624	0	0
T69	0	596	0	0
T70	0	952	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5354866	0	0
T1	6250	2449	0	0
T2	751	350	0	0
T3	18039	17591	0	0
T4	10366	9952	0	0
T5	15041	14612	0	0
T23	408	7	0	0
T24	493	92	0	0
T25	1305	103	0	0
T26	777	376	0	0
T27	10053	9622	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	447	0	0
T6	36286	7	0	0
T7	116381	0	0	0
T8	10018	0	0	0
T14	0	1	0	0
T30	2062	0	0	0
T31	4411	0	0	0
T32	505	0	0	0
T46	496	0	0	0
T47	728	0	0	0
T56	10964	0	0	0
T61	494	0	0	0
T69	0	10	0	0
T70	0	7	0	0
T99	0	15	0	0
T100	0	26	0	0
T102	0	10	0	0
T103	0	6	0	0
T105	0	7	0	0
T265	0	18	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	79347	0	0
T6	36286	0	0	0
T13	0	2983	0	0
T14	0	462	0	0
T17	0	3033	0	0
T27	10053	920	0	0
T28	418	0	0	0
T29	1232	0	0	0
T46	496	0	0	0
T47	728	0	0	0
T48	30444	1467	0	0
T56	10964	183	0	0
T60	755	0	0	0
T61	494	0	0	0
T68	0	1332	0	0
T262	0	447	0	0
T263	0	92	0	0
T264	0	483	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	929	0	0
T6	36286	0	0	0
T13	0	25	0	0
T14	0	5	0	0
T17	0	25	0	0
T27	10053	15	0	0
T28	418	0	0	0
T29	1232	0	0	0
T46	496	0	0	0
T47	728	0	0	0
T48	30444	17	0	0
T56	10964	9	0	0
T60	755	0	0	0
T61	494	0	0	0
T68	0	13	0	0
T262	0	10	0	0
T263	0	2	0	0
T264	0	9	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	4903928	0	0
T1	6250	2449	0	0
T2	751	350	0	0
T3	18039	17591	0	0
T4	10366	9952	0	0
T5	15041	14612	0	0
T23	408	7	0	0
T24	493	92	0	0
T25	1305	103	0	0
T26	777	376	0	0
T27	10053	3450	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	4906045	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	3450	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	1524	0	0
T6	36286	26	0	0
T13	0	25	0	0
T14	0	9	0	0
T17	0	25	0	0
T27	10053	15	0	0
T28	418	0	0	0
T29	1232	0	0	0
T46	496	0	0	0
T47	728	0	0	0
T48	30444	17	0	0
T56	10964	9	0	0
T60	755	0	0	0
T61	494	0	0	0
T68	0	13	0	0
T69	0	10	0	0
T70	0	20	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	1502	0	0
T6	36286	26	0	0
T13	0	25	0	0
T14	0	7	0	0
T17	0	25	0	0
T27	10053	15	0	0
T28	418	0	0	0
T29	1232	0	0	0
T46	496	0	0	0
T47	728	0	0	0
T48	30444	17	0	0
T56	10964	9	0	0
T60	755	0	0	0
T61	494	0	0	0
T68	0	13	0	0
T69	0	10	0	0
T70	0	20	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	929	0	0
T6	36286	0	0	0
T13	0	25	0	0
T14	0	5	0	0
T17	0	25	0	0
T27	10053	15	0	0
T28	418	0	0	0
T29	1232	0	0	0
T46	496	0	0	0
T47	728	0	0	0
T48	30444	17	0	0
T56	10964	9	0	0
T60	755	0	0	0
T61	494	0	0	0
T68	0	13	0	0
T262	0	10	0	0
T263	0	2	0	0
T264	0	9	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	929	0	0
T6	36286	0	0	0
T13	0	25	0	0
T14	0	5	0	0
T17	0	25	0	0
T27	10053	15	0	0
T28	418	0	0	0
T29	1232	0	0	0
T46	496	0	0	0
T47	728	0	0	0
T48	30444	17	0	0
T56	10964	9	0	0
T60	755	0	0	0
T61	494	0	0	0
T68	0	13	0	0
T262	0	10	0	0
T263	0	2	0	0
T264	0	9	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	78306	0	0
T6	36286	0	0	0
T13	0	2952	0	0
T14	0	457	0	0
T17	0	3003	0	0
T27	10053	905	0	0
T28	418	0	0	0
T29	1232	0	0	0
T46	496	0	0	0
T47	728	0	0	0
T48	30444	1444	0	0
T56	10964	174	0	0
T60	755	0	0	0
T61	494	0	0	0
T68	0	1317	0	0
T262	0	437	0	0
T263	0	90	0	0
T264	0	473	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5360213	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5360213	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	809	0	0
T6	36286	0	0	0
T13	0	19	0	0
T14	0	5	0	0
T17	0	20	0	0
T27	10053	15	0	0
T28	418	0	0	0
T29	1232	0	0	0
T46	496	0	0	0
T47	728	0	0	0
T48	30444	11	0	0
T56	10964	9	0	0
T60	755	0	0	0
T61	494	0	0	0
T68	0	11	0	0
T262	0	10	0	0
T263	0	2	0	0
T264	0	8	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T3,T4
1	Covered	T5,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T3,T4
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T5,T3,T4

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T2	VC_COV_UNR
1	Covered	T5,T3,T4

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T5,T3,T4

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T3,T4
1	0	Covered	T5,T1,T3
1	1	Covered	T5,T3,T4

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T3,T4
0	1	Covered	T82,T187,T280
1	0	Covered	T14,T83,T84

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T3,T4
0	1	Covered	T5,T3,T4
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T3,T4
1	-	Covered	T5,T3,T4

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T3,T4
DetectSt	168	Covered	T5,T3,T4
IdleSt	163	Covered	T5,T1,T2
StableSt	191	Covered	T5,T3,T4

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T3,T4
DebounceSt->IdleSt	163	Covered	T3,T4,T48
DetectSt->IdleSt	186	Covered	T14,T82,T187
DetectSt->StableSt	191	Covered	T5,T3,T4
IdleSt->DebounceSt	148	Covered	T5,T3,T4
StableSt->IdleSt	206	Covered	T5,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T3,T4
0	1	Covered	T5,T3,T4
0	0	Excluded	T5,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T3,T4
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T3,T4
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T14,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T3,T4
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T4,T48
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T3,T4
DetectSt	-	-	-	-	1	-	-	Covered	T14,T82,T187
DetectSt	-	-	-	-	0	1	-	Covered	T5,T3,T4
DetectSt	-	-	-	-	0	0	-	Covered	T5,T3,T4
StableSt	-	-	-	-	-	-	1	Covered	T5,T3,T4
StableSt	-	-	-	-	-	-	0	Covered	T5,T3,T4
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6011137	833	0	0
CntIncr_A	6011137	45106	0	0
CntNoWrap_A	6011137	5357058	0	0
DetectStDropOut_A	6011137	66	0	0
DetectedOut_A	6011137	14212	0	0
DetectedPulseOut_A	6011137	319	0	0
DisabledIdleSt_A	6011137	4983236	0	0
DisabledNoDetection_A	6011137	4984885	0	0
EnterDebounceSt_A	6011137	444	0	0
EnterDetectSt_A	6011137	390	0	0
EnterStableSt_A	6011137	319	0	0
PulseIsPulse_A	6011137	319	0	0
StayInStableSt	6011137	13869	0	0
gen_high_level_sva.HighLevelEvent_A	6011137	5360213	0	0
gen_not_sticky_sva.StableStDropOut_A	6011137	295	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	833	0	0
T1	6250	0	0	0
T2	751	0	0	0
T3	18039	7	0	0
T4	10366	7	0	0
T5	15041	8	0	0
T12	0	2	0	0
T13	0	10	0	0
T14	0	8	0	0
T17	0	4	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T48	0	11	0	0
T49	0	2	0	0
T50	0	16	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	45106	0	0
T1	6250	0	0	0
T2	751	0	0	0
T3	18039	292	0	0
T4	10366	356	0	0
T5	15041	544	0	0
T12	0	100	0	0
T13	0	385	0	0
T14	0	284	0	0
T17	0	160	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T48	0	304	0	0
T49	0	84	0	0
T50	0	752	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5357058	0	0
T1	6250	2449	0	0
T2	751	350	0	0
T3	18039	17584	0	0
T4	10366	9945	0	0
T5	15041	14604	0	0
T23	408	7	0	0
T24	493	92	0	0
T25	1305	103	0	0
T26	777	376	0	0
T27	10053	9652	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	66	0	0
T69	5616	0	0	0
T82	8507	2	0	0
T89	0	2	0	0
T98	22001	0	0	0
T106	0	7	0	0
T109	0	3	0	0
T115	4082	0	0	0
T116	402	0	0	0
T117	546	0	0	0
T118	534	0	0	0
T187	0	7	0	0
T273	526	0	0	0
T274	506	0	0	0
T275	595	0	0	0
T280	0	9	0	0
T281	0	9	0	0
T282	0	3	0	0
T283	0	7	0	0
T284	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	14212	0	0
T1	6250	0	0	0
T2	751	0	0	0
T3	18039	88	0	0
T4	10366	127	0	0
T5	15041	161	0	0
T12	0	59	0	0
T13	0	359	0	0
T14	0	108	0	0
T17	0	174	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T48	0	205	0	0
T49	0	49	0	0
T50	0	144	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	319	0	0
T1	6250	0	0	0
T2	751	0	0	0
T3	18039	3	0	0
T4	10366	3	0	0
T5	15041	4	0	0
T12	0	1	0	0
T13	0	5	0	0
T14	0	1	0	0
T17	0	2	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T48	0	5	0	0
T49	0	1	0	0
T50	0	8	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	4983236	0	0
T1	6250	2449	0	0
T2	751	350	0	0
T3	18039	14104	0	0
T4	10366	6044	0	0
T5	15041	10072	0	0
T23	408	7	0	0
T24	493	92	0	0
T25	1305	103	0	0
T26	777	376	0	0
T27	10053	8732	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	4984885	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	14104	0	0
T4	10366	6044	0	0
T5	15041	10072	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	8733	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	444	0	0
T1	6250	0	0	0
T2	751	0	0	0
T3	18039	4	0	0
T4	10366	4	0	0
T5	15041	4	0	0
T12	0	1	0	0
T13	0	5	0	0
T14	0	5	0	0
T17	0	2	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T48	0	6	0	0
T49	0	1	0	0
T50	0	8	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	390	0	0
T1	6250	0	0	0
T2	751	0	0	0
T3	18039	3	0	0
T4	10366	3	0	0
T5	15041	4	0	0
T12	0	1	0	0
T13	0	5	0	0
T14	0	3	0	0
T17	0	2	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T48	0	5	0	0
T49	0	1	0	0
T50	0	8	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	319	0	0
T1	6250	0	0	0
T2	751	0	0	0
T3	18039	3	0	0
T4	10366	3	0	0
T5	15041	4	0	0
T12	0	1	0	0
T13	0	5	0	0
T14	0	1	0	0
T17	0	2	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T48	0	5	0	0
T49	0	1	0	0
T50	0	8	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	319	0	0
T1	6250	0	0	0
T2	751	0	0	0
T3	18039	3	0	0
T4	10366	3	0	0
T5	15041	4	0	0
T12	0	1	0	0
T13	0	5	0	0
T14	0	1	0	0
T17	0	2	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T48	0	5	0	0
T49	0	1	0	0
T50	0	8	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	13869	0	0
T1	6250	0	0	0
T2	751	0	0	0
T3	18039	85	0	0
T4	10366	124	0	0
T5	15041	157	0	0
T12	0	58	0	0
T13	0	354	0	0
T14	0	107	0	0
T17	0	172	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T48	0	196	0	0
T49	0	48	0	0
T50	0	136	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	5360213	0	0
T1	6250	2458	0	0
T2	751	351	0	0
T3	18039	17598	0	0
T4	10366	9955	0	0
T5	15041	14617	0	0
T23	408	8	0	0
T24	493	93	0	0
T25	1305	105	0	0
T26	777	377	0	0
T27	10053	9653	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6011137	295	0	0
T1	6250	0	0	0
T2	751	0	0	0
T3	18039	3	0	0
T4	10366	3	0	0
T5	15041	4	0	0
T12	0	1	0	0
T13	0	5	0	0
T14	0	1	0	0
T17	0	2	0	0
T23	408	0	0	0
T24	493	0	0	0
T25	1305	0	0	0
T26	777	0	0	0
T27	10053	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	8	0	0