Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.34	100.00	96.72	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1180808185	20501	0	0
auto_block_debounce_ctl_rd_A	1180808185	2393	0	0
auto_block_out_ctl_rd_A	1180808185	3059	0	0
com_det_ctl_0_rd_A	1180808185	4303	0	0
com_det_ctl_1_rd_A	1180808185	4308	0	0
com_det_ctl_2_rd_A	1180808185	4324	0	0
com_det_ctl_3_rd_A	1180808185	4392	0	0
com_out_ctl_0_rd_A	1180808185	4893	0	0
com_out_ctl_1_rd_A	1180808185	4967	0	0
com_out_ctl_2_rd_A	1180808185	4957	0	0
com_out_ctl_3_rd_A	1180808185	4599	0	0
com_pre_det_ctl_0_rd_A	1180808185	1783	0	0
com_pre_det_ctl_1_rd_A	1180808185	1857	0	0
com_pre_det_ctl_2_rd_A	1180808185	1710	0	0
com_pre_det_ctl_3_rd_A	1180808185	1733	0	0
com_pre_sel_ctl_0_rd_A	1180808185	4934	0	0
com_pre_sel_ctl_1_rd_A	1180808185	5185	0	0
com_pre_sel_ctl_2_rd_A	1180808185	5053	0	0
com_pre_sel_ctl_3_rd_A	1180808185	5010	0	0
com_sel_ctl_0_rd_A	1180808185	5225	0	0
com_sel_ctl_1_rd_A	1180808185	4915	0	0
com_sel_ctl_2_rd_A	1180808185	5165	0	0
com_sel_ctl_3_rd_A	1180808185	5071	0	0
ec_rst_ctl_rd_A	1180808185	2829	0	0
intr_enable_rd_A	1180808185	2749	0	0
key_intr_ctl_rd_A	1180808185	4416	0	0
key_intr_debounce_ctl_rd_A	1180808185	1928	0	0
key_invert_ctl_rd_A	1180808185	5304	0	0
pin_allowed_ctl_rd_A	1180808185	7574	0	0
pin_out_ctl_rd_A	1180808185	5926	0	0
pin_out_value_rd_A	1180808185	5705	0	0
regwen_rd_A	1180808185	2036	0	0
ulp_ac_debounce_ctl_rd_A	1180808185	2081	0	0
ulp_ctl_rd_A	1180808185	1877	0	0
ulp_lid_debounce_ctl_rd_A	1180808185	1844	0	0
ulp_pwrb_debounce_ctl_rd_A	1180808185	2040	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	20501	0	0
T1	750006	8	0	0
T2	127048	0	0	0
T3	216477	0	0	0
T4	466496	0	0	0
T8	0	10	0	0
T18	0	24	0	0
T19	0	15	0	0
T23	51093	0	0	0
T24	246720	0	0	0
T25	626300	0	0	0
T26	373544	0	0	0
T27	246292	0	0	0
T28	209340	0	0	0
T115	0	14	0	0
T131	0	15	0	0
T132	0	19	0	0
T165	0	7	0	0
T182	0	3	0	0
T300	0	15	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	2393	0	0
T8	456742	37	0	0
T9	66049	0	0	0
T10	200493	0	0	0
T11	46023	0	0	0
T31	485235	0	0	0
T32	12634	0	0	0
T33	53281	0	0	0
T34	63074	0	0	0
T35	25358	0	0	0
T45	34902	0	0	0
T57	0	12	0	0
T58	0	8	0	0
T97	0	16	0	0
T104	0	39	0	0
T135	0	7	0	0
T165	0	36	0	0
T171	0	6	0	0
T183	0	3	0	0
T301	0	5	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	3059	0	0
T8	456742	23	0	0
T9	66049	0	0	0
T10	200493	0	0	0
T11	46023	0	0	0
T31	485235	0	0	0
T32	12634	0	0	0
T33	53281	0	0	0
T34	63074	0	0	0
T35	25358	0	0	0
T45	34902	0	0	0
T57	0	6	0	0
T58	0	13	0	0
T97	0	4	0	0
T104	0	34	0	0
T135	0	9	0	0
T165	0	23	0	0
T171	0	14	0	0
T183	0	1	0	0
T301	0	9	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	4303	0	0
T4	466496	42	0	0
T6	453578	109	0	0
T8	0	22	0	0
T13	0	75	0	0
T25	626300	0	0	0
T26	373544	0	0	0
T27	246292	0	0	0
T28	209340	0	0	0
T29	184871	0	0	0
T46	136607	0	0	0
T48	243556	0	0	0
T49	0	67	0	0
T50	0	32	0	0
T60	200217	0	0	0
T70	0	35	0	0
T165	0	11	0	0
T265	0	67	0	0
T302	0	31	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	4308	0	0
T4	466496	20	0	0
T6	453578	118	0	0
T8	0	21	0	0
T13	0	79	0	0
T25	626300	0	0	0
T26	373544	0	0	0
T27	246292	0	0	0
T28	209340	0	0	0
T29	184871	0	0	0
T46	136607	0	0	0
T48	243556	0	0	0
T49	0	90	0	0
T50	0	34	0	0
T60	200217	0	0	0
T70	0	21	0	0
T165	0	21	0	0
T265	0	79	0	0
T302	0	38	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	4324	0	0
T4	466496	42	0	0
T6	453578	98	0	0
T8	0	12	0	0
T13	0	73	0	0
T25	626300	0	0	0
T26	373544	0	0	0
T27	246292	0	0	0
T28	209340	0	0	0
T29	184871	0	0	0
T46	136607	0	0	0
T48	243556	0	0	0
T49	0	69	0	0
T50	0	43	0	0
T60	200217	0	0	0
T70	0	57	0	0
T165	0	18	0	0
T265	0	73	0	0
T302	0	21	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	4392	0	0
T4	466496	33	0	0
T6	453578	85	0	0
T8	0	16	0	0
T13	0	68	0	0
T25	626300	0	0	0
T26	373544	0	0	0
T27	246292	0	0	0
T28	209340	0	0	0
T29	184871	0	0	0
T46	136607	0	0	0
T48	243556	0	0	0
T49	0	59	0	0
T50	0	21	0	0
T60	200217	0	0	0
T70	0	41	0	0
T165	0	15	0	0
T265	0	82	0	0
T302	0	27	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	4893	0	0
T4	466496	31	0	0
T6	453578	94	0	0
T8	0	13	0	0
T13	0	77	0	0
T25	626300	0	0	0
T26	373544	0	0	0
T27	246292	0	0	0
T28	209340	0	0	0
T29	184871	0	0	0
T46	136607	0	0	0
T48	243556	0	0	0
T49	0	56	0	0
T50	0	37	0	0
T60	200217	0	0	0
T70	0	43	0	0
T165	0	4	0	0
T265	0	64	0	0
T302	0	23	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	4967	0	0
T4	466496	42	0	0
T6	453578	109	0	0
T8	0	5	0	0
T13	0	62	0	0
T25	626300	0	0	0
T26	373544	0	0	0
T27	246292	0	0	0
T28	209340	0	0	0
T29	184871	0	0	0
T46	136607	0	0	0
T48	243556	0	0	0
T49	0	76	0	0
T50	0	50	0	0
T60	200217	0	0	0
T70	0	30	0	0
T165	0	15	0	0
T265	0	90	0	0
T302	0	30	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	4957	0	0
T4	466496	65	0	0
T6	453578	101	0	0
T8	0	18	0	0
T13	0	69	0	0
T25	626300	0	0	0
T26	373544	0	0	0
T27	246292	0	0	0
T28	209340	0	0	0
T29	184871	0	0	0
T46	136607	0	0	0
T48	243556	0	0	0
T49	0	83	0	0
T50	0	40	0	0
T60	200217	0	0	0
T70	0	25	0	0
T165	0	10	0	0
T265	0	73	0	0
T302	0	28	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	4599	0	0
T4	466496	32	0	0
T6	453578	110	0	0
T8	0	22	0	0
T13	0	67	0	0
T25	626300	0	0	0
T26	373544	0	0	0
T27	246292	0	0	0
T28	209340	0	0	0
T29	184871	0	0	0
T46	136607	0	0	0
T48	243556	0	0	0
T49	0	62	0	0
T50	0	44	0	0
T60	200217	0	0	0
T70	0	34	0	0
T165	0	14	0	0
T265	0	79	0	0
T302	0	29	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1783	0	0
T8	456742	18	0	0
T9	66049	0	0	0
T10	200493	0	0	0
T11	46023	0	0	0
T31	485235	0	0	0
T32	12634	0	0	0
T33	53281	0	0	0
T34	63074	0	0	0
T35	25358	0	0	0
T45	34902	0	0	0
T104	0	9	0	0
T108	0	10	0	0
T135	0	13	0	0
T158	0	4	0	0
T165	0	14	0	0
T216	0	24	0	0
T303	0	19	0	0
T304	0	12	0	0
T305	0	24	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1857	0	0
T8	456742	27	0	0
T9	66049	0	0	0
T10	200493	0	0	0
T11	46023	0	0	0
T31	485235	0	0	0
T32	12634	0	0	0
T33	53281	0	0	0
T34	63074	0	0	0
T35	25358	0	0	0
T45	34902	0	0	0
T104	0	20	0	0
T108	0	9	0	0
T135	0	2	0	0
T158	0	12	0	0
T165	0	19	0	0
T216	0	7	0	0
T303	0	24	0	0
T304	0	9	0	0
T305	0	27	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1710	0	0
T8	456742	22	0	0
T9	66049	0	0	0
T10	200493	0	0	0
T11	46023	0	0	0
T31	485235	0	0	0
T32	12634	0	0	0
T33	53281	0	0	0
T34	63074	0	0	0
T35	25358	0	0	0
T45	34902	0	0	0
T104	0	17	0	0
T108	0	11	0	0
T158	0	6	0	0
T159	0	9	0	0
T165	0	14	0	0
T216	0	17	0	0
T303	0	18	0	0
T304	0	11	0	0
T305	0	23	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1733	0	0
T8	456742	7	0	0
T9	66049	0	0	0
T10	200493	0	0	0
T11	46023	0	0	0
T31	485235	0	0	0
T32	12634	0	0	0
T33	53281	0	0	0
T34	63074	0	0	0
T35	25358	0	0	0
T45	34902	0	0	0
T104	0	12	0	0
T108	0	12	0	0
T135	0	7	0	0
T158	0	15	0	0
T159	0	3	0	0
T165	0	22	0	0
T303	0	12	0	0
T304	0	5	0	0
T305	0	19	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	4934	0	0
T4	466496	27	0	0
T6	453578	95	0	0
T8	0	16	0	0
T13	0	64	0	0
T25	626300	0	0	0
T26	373544	0	0	0
T27	246292	0	0	0
T28	209340	0	0	0
T29	184871	0	0	0
T46	136607	0	0	0
T48	243556	0	0	0
T49	0	69	0	0
T50	0	37	0	0
T60	200217	0	0	0
T70	0	29	0	0
T165	0	11	0	0
T265	0	78	0	0
T302	0	26	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	5185	0	0
T4	466496	48	0	0
T6	453578	91	0	0
T8	0	22	0	0
T13	0	83	0	0
T25	626300	0	0	0
T26	373544	0	0	0
T27	246292	0	0	0
T28	209340	0	0	0
T29	184871	0	0	0
T46	136607	0	0	0
T48	243556	0	0	0
T49	0	59	0	0
T50	0	43	0	0
T60	200217	0	0	0
T70	0	24	0	0
T165	0	22	0	0
T265	0	75	0	0
T302	0	37	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	5053	0	0
T4	466496	47	0	0
T6	453578	77	0	0
T8	0	7	0	0
T13	0	70	0	0
T25	626300	0	0	0
T26	373544	0	0	0
T27	246292	0	0	0
T28	209340	0	0	0
T29	184871	0	0	0
T46	136607	0	0	0
T48	243556	0	0	0
T49	0	65	0	0
T50	0	47	0	0
T60	200217	0	0	0
T70	0	22	0	0
T165	0	12	0	0
T265	0	75	0	0
T302	0	49	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	5010	0	0
T4	466496	47	0	0
T6	453578	111	0	0
T8	0	21	0	0
T13	0	75	0	0
T25	626300	0	0	0
T26	373544	0	0	0
T27	246292	0	0	0
T28	209340	0	0	0
T29	184871	0	0	0
T46	136607	0	0	0
T48	243556	0	0	0
T49	0	73	0	0
T50	0	37	0	0
T60	200217	0	0	0
T70	0	31	0	0
T165	0	18	0	0
T265	0	77	0	0
T302	0	36	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	5225	0	0
T4	466496	41	0	0
T6	453578	90	0	0
T8	0	26	0	0
T13	0	69	0	0
T25	626300	0	0	0
T26	373544	0	0	0
T27	246292	0	0	0
T28	209340	0	0	0
T29	184871	0	0	0
T46	136607	0	0	0
T48	243556	0	0	0
T49	0	81	0	0
T50	0	59	0	0
T60	200217	0	0	0
T70	0	28	0	0
T165	0	9	0	0
T265	0	71	0	0
T302	0	31	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	4915	0	0
T4	466496	30	0	0
T6	453578	78	0	0
T8	0	22	0	0
T13	0	69	0	0
T25	626300	0	0	0
T26	373544	0	0	0
T27	246292	0	0	0
T28	209340	0	0	0
T29	184871	0	0	0
T46	136607	0	0	0
T48	243556	0	0	0
T49	0	77	0	0
T50	0	42	0	0
T60	200217	0	0	0
T70	0	26	0	0
T165	0	11	0	0
T265	0	75	0	0
T302	0	49	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	5165	0	0
T4	466496	59	0	0
T6	453578	115	0	0
T8	0	27	0	0
T13	0	90	0	0
T25	626300	0	0	0
T26	373544	0	0	0
T27	246292	0	0	0
T28	209340	0	0	0
T29	184871	0	0	0
T46	136607	0	0	0
T48	243556	0	0	0
T49	0	80	0	0
T50	0	34	0	0
T60	200217	0	0	0
T70	0	32	0	0
T165	0	25	0	0
T265	0	56	0	0
T302	0	39	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	5071	0	0
T4	466496	45	0	0
T6	453578	106	0	0
T8	0	25	0	0
T13	0	70	0	0
T25	626300	0	0	0
T26	373544	0	0	0
T27	246292	0	0	0
T28	209340	0	0	0
T29	184871	0	0	0
T46	136607	0	0	0
T48	243556	0	0	0
T49	0	61	0	0
T50	0	53	0	0
T60	200217	0	0	0
T70	0	34	0	0
T165	0	15	0	0
T265	0	87	0	0
T302	0	33	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	2829	0	0
T4	466496	7	0	0
T6	453578	36	0	0
T8	0	22	0	0
T13	0	18	0	0
T25	626300	0	0	0
T26	373544	0	0	0
T27	246292	0	0	0
T28	209340	0	0	0
T29	184871	0	0	0
T46	136607	0	0	0
T48	243556	0	0	0
T49	0	39	0	0
T50	0	19	0	0
T60	200217	2	0	0
T165	0	14	0	0
T184	0	8	0	0
T275	0	3	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	2749	0	0
T6	453578	0	0	0
T8	0	24	0	0
T25	626300	12	0	0
T26	373544	0	0	0
T27	246292	0	0	0
T28	209340	0	0	0
T29	184871	0	0	0
T46	136607	0	0	0
T48	243556	0	0	0
T55	0	8	0	0
T56	712751	0	0	0
T60	200217	0	0	0
T104	0	10	0	0
T135	0	13	0	0
T158	0	46	0	0
T159	0	27	0	0
T165	0	27	0	0
T306	0	22	0	0
T307	0	15	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	4416	0	0
T8	456742	26	0	0
T9	66049	0	0	0
T10	200493	3	0	0
T11	46023	0	0	0
T31	485235	0	0	0
T32	12634	0	0	0
T33	53281	0	0	0
T34	63074	0	0	0
T35	25358	0	0	0
T45	34902	0	0	0
T52	0	1	0	0
T104	0	10	0	0
T135	0	3	0	0
T158	0	15	0	0
T164	0	5	0	0
T165	0	18	0	0
T168	0	1	0	0
T203	0	1	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1928	0	0
T8	456742	14	0	0
T9	66049	0	0	0
T10	200493	0	0	0
T11	46023	0	0	0
T31	485235	0	0	0
T32	12634	0	0	0
T33	53281	0	0	0
T34	63074	0	0	0
T35	25358	0	0	0
T45	34902	0	0	0
T104	0	4	0	0
T108	0	10	0	0
T158	0	5	0	0
T165	0	11	0	0
T216	0	14	0	0
T229	0	24	0	0
T303	0	28	0	0
T304	0	15	0	0
T305	0	15	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	5304	0	0
T8	456742	24	0	0
T9	66049	0	0	0
T10	200493	0	0	0
T11	46023	0	0	0
T31	485235	0	0	0
T32	12634	0	0	0
T33	53281	0	0	0
T34	63074	0	0	0
T35	25358	0	0	0
T45	34902	0	0	0
T62	0	65	0	0
T104	0	71	0	0
T135	0	18	0	0
T151	0	65	0	0
T158	0	14	0	0
T159	0	105	0	0
T165	0	150	0	0
T303	0	17	0	0
T308	0	46	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	7574	0	0
T6	453578	0	0	0
T8	0	77	0	0
T25	626300	83	0	0
T26	373544	0	0	0
T27	246292	0	0	0
T28	209340	0	0	0
T29	184871	0	0	0
T46	136607	0	0	0
T48	243556	0	0	0
T49	0	69	0	0
T56	712751	0	0	0
T60	200217	0	0	0
T64	0	64	0	0
T104	0	112	0	0
T136	0	70	0	0
T165	0	17	0	0
T168	0	131	0	0
T309	0	45	0	0
T310	0	79	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	5926	0	0
T6	453578	0	0	0
T8	0	108	0	0
T25	626300	67	0	0
T26	373544	0	0	0
T27	246292	0	0	0
T28	209340	0	0	0
T29	184871	0	0	0
T46	136607	0	0	0
T48	243556	0	0	0
T49	0	58	0	0
T56	712751	0	0	0
T60	200217	0	0	0
T64	0	72	0	0
T104	0	82	0	0
T136	0	79	0	0
T165	0	8	0	0
T168	0	132	0	0
T309	0	73	0	0
T310	0	72	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	5705	0	0
T6	453578	0	0	0
T8	0	86	0	0
T25	626300	50	0	0
T26	373544	0	0	0
T27	246292	0	0	0
T28	209340	0	0	0
T29	184871	0	0	0
T46	136607	0	0	0
T48	243556	0	0	0
T49	0	63	0	0
T56	712751	0	0	0
T60	200217	0	0	0
T64	0	85	0	0
T104	0	77	0	0
T136	0	63	0	0
T165	0	6	0	0
T168	0	167	0	0
T309	0	80	0	0
T310	0	58	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	2036	0	0
T8	456742	27	0	0
T9	66049	0	0	0
T10	200493	0	0	0
T11	46023	0	0	0
T31	485235	0	0	0
T32	12634	0	0	0
T33	53281	0	0	0
T34	63074	0	0	0
T35	25358	0	0	0
T45	34902	0	0	0
T104	0	18	0	0
T108	0	5	0	0
T135	0	3	0	0
T158	0	6	0	0
T159	0	2	0	0
T165	0	9	0	0
T303	0	24	0	0
T304	0	11	0	0
T305	0	8	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	2081	0	0
T8	456742	7	0	0
T9	66049	0	0	0
T10	200493	0	0	0
T11	46023	0	0	0
T31	485235	0	0	0
T32	12634	0	0	0
T33	53281	0	0	0
T34	63074	0	0	0
T35	25358	0	0	0
T39	0	10	0	0
T45	34902	0	0	0
T73	0	10	0	0
T104	0	2	0	0
T134	0	5	0	0
T135	0	10	0	0
T158	0	18	0	0
T159	0	5	0	0
T165	0	18	0	0
T303	0	16	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1877	0	0
T8	456742	19	0	0
T9	66049	0	0	0
T10	200493	0	0	0
T11	46023	0	0	0
T31	485235	0	0	0
T32	12634	0	0	0
T33	53281	0	0	0
T34	63074	0	0	0
T35	25358	0	0	0
T39	0	3	0	0
T45	34902	2	0	0
T73	0	1	0	0
T104	0	1	0	0
T135	0	22	0	0
T158	0	15	0	0
T159	0	9	0	0
T165	0	23	0	0
T303	0	21	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	1844	0	0
T8	456742	11	0	0
T9	66049	0	0	0
T10	200493	0	0	0
T11	46023	0	0	0
T31	485235	0	0	0
T32	12634	0	0	0
T33	53281	0	0	0
T34	63074	0	0	0
T35	25358	0	0	0
T39	0	9	0	0
T45	34902	1	0	0
T104	0	9	0	0
T134	0	12	0	0
T135	0	5	0	0
T158	0	12	0	0
T159	0	10	0	0
T165	0	9	0	0
T303	0	12	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180808185	2040	0	0
T8	456742	41	0	0
T9	66049	0	0	0
T10	200493	0	0	0
T11	46023	0	0	0
T31	485235	0	0	0
T32	12634	0	0	0
T33	53281	0	0	0
T34	63074	0	0	0
T35	25358	0	0	0
T39	0	3	0	0
T45	34902	4	0	0
T73	0	8	0	0
T104	0	14	0	0
T134	0	16	0	0
T135	0	2	0	0
T158	0	5	0	0
T159	0	2	0	0
T165	0	13	0	0