Unified Coverage Report :: Module

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T1,T3
1	0	Covered	T5,T1,T3
1	1	Covered	T7,T22,T36

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T1,T3
1	0	Covered	T7,T22,T36
1	1	Covered	T5,T1,T3

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	239485	0	0
SrcPulseCheck_M	2147483647	241819	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	239485
T1	13618858	2
T2	2429683	0
T3	4491882	21
T4	9081110	9
T5	5979015	15
T6	4898640	39
T7	423435	0
T8	0	18
T12	0	9
T13	0	7
T14	0	15
T18	0	16
T19	0	16
T23	979335	0
T24	4698033	0
T25	11927105	0
T26	7862295	14
T27	7454111	3
T28	2937448	0
T29	2048365	0
T30	495039	2
T35	0	12
T46	1371030	0
T47	3542610	14
T48	2740000	36
T56	7237150	6
T57	0	16
T58	0	12
T59	0	12
T60	2009720	0
T61	1090608	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	241819
T1	14362614	2
T2	2682277	0
T3	4888758	21
T4	9993370	9
T5	5979015	15
T6	4898640	39
T7	116381	0
T8	0	18
T12	0	9
T13	0	7
T14	0	15
T18	0	16
T19	0	16
T23	1080705	0
T24	5190487	0
T25	13177095	0
T26	8607829	14
T27	7926589	3
T28	3355292	0
T29	2232004	0
T30	2062	2
T35	0	12
T46	1371030	0
T47	3542610	14
T48	2740000	36
T56	7237150	6
T57	0	16
T58	0	12
T59	0	12
T60	2009720	0
T61	1090608	0

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T1,T3
1	0	Covered	T5,T1,T3
1	1	Covered	T43,T291,T71

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T1,T3
1	0	Covered	T43,T291,T71
1	1	Covered	T5,T1,T3

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6294349	2053	0	0
SrcPulseCheck_M	1180808185	2115	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6294349	2053
T1	6250	2
T2	751	0
T3	18039	7
T4	10366	3
T5	15041	5
T6	0	13
T7	0	1
T23	408	0
T24	493	0
T25	1305	0
T26	777	0
T27	10053	1
T48	0	12
T56	0	2
T60	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1180808185	2115
T1	750006	2
T2	127048	0
T3	216477	7
T4	466496	3
T5	383560	5
T6	0	13
T7	0	1
T23	51093	0
T24	246720	0
T25	626300	0
T26	373544	0
T27	246292	1
T48	0	12
T56	0	2
T60	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T1,T3
1	0	Covered	T5,T1,T3
1	1	Covered	T43,T291,T71

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T1,T3
1	0	Covered	T43,T291,T71
1	1	Covered	T5,T1,T3

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1180808185	2108	0	0
SrcPulseCheck_M	6294349	2108	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1180808185	2108
T1	750006	2
T2	127048	0
T3	216477	7
T4	466496	3
T5	383560	5
T6	0	13
T7	0	1
T23	51093	0
T24	246720	0
T25	626300	0
T26	373544	0
T27	246292	1
T48	0	12
T56	0	2
T60	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6294349	2108
T1	6250	2
T2	751	0
T3	18039	7
T4	10366	3
T5	15041	5
T6	0	13
T7	0	1
T23	408	0
T24	493	0
T25	1305	0
T26	777	0
T27	10053	1
T48	0	12
T56	0	2
T60	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T7,T8,T45
1	0	Covered	T7,T8,T45
1	1	Covered	T22,T36,T37

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T7,T8,T45
1	0	Covered	T22,T36,T37
1	1	Covered	T7,T8,T45

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6294349	1111	0	0
SrcPulseCheck_M	1180808185	1172	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6294349	1111
T7	116381	1
T8	10018	1
T9	508	0
T10	834	0
T14	0	1
T18	0	5
T19	0	3
T22	0	2
T30	2062	0
T31	4411	0
T32	505	0
T33	425	0
T34	526	0
T35	633	0
T36	0	2
T37	0	3
T38	0	2
T45	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1180808185	1172
T7	423435	1
T8	456742	1
T9	66049	0
T10	200493	0
T14	0	1
T18	0	5
T19	0	3
T22	0	2
T30	495039	0
T31	485235	0
T32	12634	0
T33	53281	0
T34	63074	0
T35	25358	0
T36	0	2
T37	0	3
T38	0	2
T45	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T7,T8,T45
1	0	Covered	T7,T8,T45
1	1	Covered	T22,T36,T37

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T7,T8,T45
1	0	Covered	T22,T36,T37
1	1	Covered	T7,T8,T45

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1180808185	1165	0	0
SrcPulseCheck_M	6294349	1165	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1180808185	1165
T7	423435	1
T8	456742	1
T9	66049	0
T10	200493	0
T14	0	1
T18	0	5
T19	0	3
T22	0	2
T30	495039	0
T31	485235	0
T32	12634	0
T33	53281	0
T34	63074	0
T35	25358	0
T36	0	2
T37	0	3
T38	0	2
T45	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6294349	1165
T7	116381	1
T8	10018	1
T9	508	0
T10	834	0
T14	0	1
T18	0	5
T19	0	3
T22	0	2
T30	2062	0
T31	4411	0
T32	505	0
T33	425	0
T34	526	0
T35	633	0
T36	0	2
T37	0	3
T38	0	2
T45	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T7,T8,T45
1	0	Covered	T7,T8,T45
1	1	Covered	T22,T36,T37

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T7,T8,T45
1	0	Covered	T22,T36,T37
1	1	Covered	T7,T8,T45

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6294349	1113	0	0
SrcPulseCheck_M	1180808185	1173	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6294349	1113
T7	116381	1
T8	10018	1
T9	508	0
T10	834	0
T14	0	1
T18	0	5
T19	0	3
T22	0	2
T30	2062	0
T31	4411	0
T32	505	0
T33	425	0
T34	526	0
T35	633	0
T36	0	2
T37	0	3
T38	0	2
T45	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1180808185	1173
T7	423435	1
T8	456742	1
T9	66049	0
T10	200493	0
T14	0	1
T18	0	5
T19	0	3
T22	0	2
T30	495039	0
T31	485235	0
T32	12634	0
T33	53281	0
T34	63074	0
T35	25358	0
T36	0	2
T37	0	3
T38	0	2
T45	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T7,T8,T45
1	0	Covered	T7,T8,T45
1	1	Covered	T22,T36,T37

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T7,T8,T45
1	0	Covered	T22,T36,T37
1	1	Covered	T7,T8,T45

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1180808185	1166	0	0
SrcPulseCheck_M	6294349	1166	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1180808185	1166
T7	423435	1
T8	456742	1
T9	66049	0
T10	200493	0
T14	0	1
T18	0	5
T19	0	3
T22	0	2
T30	495039	0
T31	485235	0
T32	12634	0
T33	53281	0
T34	63074	0
T35	25358	0
T36	0	2
T37	0	3
T38	0	2
T45	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6294349	1166
T7	116381	1
T8	10018	1
T9	508	0
T10	834	0
T14	0	1
T18	0	5
T19	0	3
T22	0	2
T30	2062	0
T31	4411	0
T32	505	0
T33	425	0
T34	526	0
T35	633	0
T36	0	2
T37	0	3
T38	0	2
T45	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T7,T8,T45
1	0	Covered	T7,T8,T45
1	1	Covered	T22,T36,T37

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T7,T8,T45
1	0	Covered	T22,T36,T37
1	1	Covered	T7,T8,T45

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6294349	1121	0	0
SrcPulseCheck_M	1180808185	1182	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6294349	1121
T7	116381	1
T8	10018	1
T9	508	0
T10	834	0
T14	0	1
T18	0	5
T19	0	3
T22	0	2
T30	2062	0
T31	4411	0
T32	505	0
T33	425	0
T34	526	0
T35	633	0
T36	0	2
T37	0	3
T38	0	2
T45	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1180808185	1182
T7	423435	1
T8	456742	1
T9	66049	0
T10	200493	0
T14	0	1
T18	0	5
T19	0	3
T22	0	2
T30	495039	0
T31	485235	0
T32	12634	0
T33	53281	0
T34	63074	0
T35	25358	0
T36	0	2
T37	0	3
T38	0	2
T45	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T7,T8,T45
1	0	Covered	T7,T8,T45
1	1	Covered	T22,T36,T37

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T7,T8,T45
1	0	Covered	T22,T36,T37
1	1	Covered	T7,T8,T45

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1180808185	1175	0	0
SrcPulseCheck_M	6294349	1175	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1180808185	1175
T7	423435	1
T8	456742	1
T9	66049	0
T10	200493	0
T14	0	1
T18	0	5
T19	0	3
T22	0	2
T30	495039	0
T31	485235	0
T32	12634	0
T33	53281	0
T34	63074	0
T35	25358	0
T36	0	2
T37	0	3
T38	0	2
T45	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6294349	1175
T7	116381	1
T8	10018	1
T9	508	0
T10	834	0
T14	0	1
T18	0	5
T19	0	3
T22	0	2
T30	2062	0
T31	4411	0
T32	505	0
T33	425	0
T34	526	0
T35	633	0
T36	0	2
T37	0	3
T38	0	2
T45	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T7,T14,T18
1	0	Covered	T7,T14,T18
1	1	Covered	T7,T14,T18

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T7,T14,T18
1	0	Covered	T7,T14,T18
1	1	Covered	T7,T14,T18

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6294349	1134	0	0
SrcPulseCheck_M	1180808185	1191	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6294349	1134
T7	116381	2
T8	10018	0
T9	508	0
T10	834	0
T14	0	4
T18	0	6
T19	0	2
T22	0	4
T30	2062	0
T31	4411	0
T32	505	0
T33	425	0
T34	526	0
T35	633	0
T36	0	2
T37	0	6
T38	0	2
T39	0	4
T40	0	4

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1180808185	1191
T7	423435	2
T8	456742	0
T9	66049	0
T10	200493	0
T14	0	4
T18	0	6
T19	0	2
T22	0	4
T30	495039	0
T31	485235	0
T32	12634	0
T33	53281	0
T34	63074	0
T35	25358	0
T36	0	2
T37	0	6
T38	0	2
T39	0	4
T40	0	4

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T7,T14,T18
1	0	Covered	T7,T14,T18
1	1	Covered	T7,T14,T18

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T7,T14,T18
1	0	Covered	T7,T14,T18
1	1	Covered	T7,T14,T18

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1180808185	1184	0	0
SrcPulseCheck_M	6294349	1184	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1180808185	1184
T7	423435	2
T8	456742	0
T9	66049	0
T10	200493	0
T14	0	4
T18	0	6
T19	0	2
T22	0	4
T30	495039	0
T31	485235	0
T32	12634	0
T33	53281	0
T34	63074	0
T35	25358	0
T36	0	2
T37	0	6
T38	0	2
T39	0	4
T40	0	4

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6294349	1184
T7	116381	2
T8	10018	0
T9	508	0
T10	834	0
T14	0	4
T18	0	6
T19	0	2
T22	0	4
T30	2062	0
T31	4411	0
T32	505	0
T33	425	0
T34	526	0
T35	633	0
T36	0	2
T37	0	6
T38	0	2
T39	0	4
T40	0	4

Line Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T7,T18,T19
1	0	Covered	T7,T18,T19
1	1	Covered	T22,T37,T39

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T7,T18,T19
1	0	Covered	T22,T37,T39
1	1	Covered	T7,T18,T19

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6294349	577	0	0
SrcPulseCheck_M	1180808185	639	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6294349	577
T7	116381	1
T8	10018	0
T9	508	0
T10	834	0
T18	0	3
T19	0	1
T22	0	2
T30	2062	0
T31	4411	0
T32	505	0
T33	425	0
T34	526	0
T35	633	0
T36	0	1
T37	0	3
T38	0	1
T39	0	2
T40	0	2
T41	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1180808185	639
T7	423435	1
T8	456742	0
T9	66049	0
T10	200493	0
T18	0	3
T19	0	1
T22	0	2
T30	495039	0
T31	485235	0
T32	12634	0
T33	53281	0
T34	63074	0
T35	25358	0
T36	0	1
T37	0	3
T38	0	1
T39	0	2
T40	0	2
T41	0	1

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T4,T50,T98

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T1,T3,T4
1	0	Covered	T4,T50,T98
1	1	Covered	T1,T3,T4

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6294349	1203	0	0
SrcPulseCheck_M	1180808185	1278	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6294349	1203
T1	6250	1
T2	751	0
T3	18039	4
T4	10366	3
T6	0	4
T7	0	1
T11	0	1
T12	0	1
T13	0	6
T14	0	1
T16	0	1
T23	408	0
T24	493	0
T25	1305	0
T26	777	0
T27	10053	0
T28	418	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1180808185	1278
T1	750006	1
T2	127048	0
T3	216477	4
T4	466496	3
T6	0	4
T7	0	1
T8	0	2
T11	0	1
T12	0	1
T13	0	6
T14	0	1
T23	51093	0
T24	246720	0
T25	626300	0
T26	373544	0
T27	246292	0
T28	209340	0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T1,T24,T46
1	0	Covered	T1,T24,T46
1	1	Covered	T1,T24,T46

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T1,T24,T46
1	0	Covered	T1,T24,T46
1	1	Covered	T1,T24,T46

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6294349	3255	0	0
SrcPulseCheck_M	1180808185	3312	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6294349	3255
T1	6250	60
T2	751	0
T3	18039	0
T4	10366	0
T16	0	20
T18	0	120
T19	0	40
T23	408	0
T24	493	20
T25	1305	0
T26	777	0
T27	10053	0
T28	418	0
T32	0	20
T46	0	20
T61	0	20
T62	0	20
T63	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1180808185	3312
T1	750006	60
T2	127048	0
T3	216477	0
T4	466496	0
T16	0	20
T18	0	120
T19	0	40
T23	51093	0
T24	246720	20
T25	626300	0
T26	373544	0
T27	246292	0
T28	209340	0
T32	0	20
T46	0	20
T61	0	20
T62	0	20
T63	0	20

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T1,T24,T46
1	0	Covered	T1,T24,T46
1	1	Covered	T1,T24,T46

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T1,T24,T46
1	0	Covered	T1,T24,T46
1	1	Covered	T1,T24,T46

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1180808185	3306	0	0
SrcPulseCheck_M	6294349	3306	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1180808185	3306
T1	750006	60
T2	127048	0
T3	216477	0
T4	466496	0
T16	0	20
T18	0	120
T19	0	40
T23	51093	0
T24	246720	20
T25	626300	0
T26	373544	0
T27	246292	0
T28	209340	0
T32	0	20
T46	0	20
T61	0	20
T62	0	20
T63	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6294349	3306
T1	6250	60
T2	751	0
T3	18039	0
T4	10366	0
T16	0	20
T18	0	120
T19	0	40
T23	408	0
T24	493	20
T25	1305	0
T26	777	0
T27	10053	0
T28	418	0
T32	0	20
T46	0	20
T61	0	20
T62	0	20
T63	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T1,T24,T25
1	0	Covered	T1,T24,T25
1	1	Covered	T1,T25,T30

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T1,T24,T25
1	0	Covered	T1,T25,T30
1	1	Covered	T1,T24,T25

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6294349	6599	0	0
SrcPulseCheck_M	1180808185	6666	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6294349	6599
T1	6250	23
T2	751	0
T3	18039	0
T4	10366	0
T8	0	138
T23	408	0
T24	493	1
T25	1305	20
T26	777	0
T27	10053	0
T28	418	0
T30	0	20
T32	0	1
T34	0	20
T46	0	1
T61	0	1
T62	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1180808185	6666
T1	750006	23
T2	127048	0
T3	216477	0
T4	466496	0
T8	0	139
T23	51093	0
T24	246720	1
T25	626300	20
T26	373544	0
T27	246292	0
T28	209340	0
T30	0	20
T32	0	1
T34	0	20
T46	0	1
T61	0	1
T62	0	1

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T1,T24,T25
1	0	Covered	T1,T24,T25
1	1	Covered	T1,T25,T30

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T1,T24,T25
1	0	Covered	T1,T25,T30
1	1	Covered	T1,T24,T25

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1180808185	6655	0	0
SrcPulseCheck_M	6294349	6655	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1180808185	6655
T1	750006	23
T2	127048	0
T3	216477	0
T4	466496	0
T8	0	138
T23	51093	0
T24	246720	1
T25	626300	20
T26	373544	0
T27	246292	0
T28	209340	0
T30	0	20
T32	0	1
T34	0	20
T46	0	1
T61	0	1
T62	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6294349	6655
T1	6250	23
T2	751	0
T3	18039	0
T4	10366	0
T8	0	138
T23	408	0
T24	493	1
T25	1305	20
T26	777	0
T27	10053	0
T28	418	0
T30	0	20
T32	0	1
T34	0	20
T46	0	1
T61	0	1
T62	0	1

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T1,T3
1	0	Covered	T5,T1,T3
1	1	Covered	T1,T25,T30

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T1,T3
1	0	Covered	T1,T25,T30
1	1	Covered	T5,T1,T3

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6294349	7707	0	0
SrcPulseCheck_M	1180808185	7770	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6294349	7707
T1	6250	26
T2	751	0
T3	18039	7
T4	10366	3
T5	15041	5
T6	0	13
T23	408	0
T24	493	1
T25	1305	20
T26	777	0
T27	10053	1
T48	0	12
T60	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1180808185	7770
T1	750006	26
T2	127048	0
T3	216477	7
T4	466496	3
T5	383560	5
T6	0	13
T23	51093	0
T24	246720	1
T25	626300	20
T26	373544	0
T27	246292	1
T48	0	12
T60	0	1

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T1,T3
1	0	Covered	T5,T1,T3
1	1	Covered	T1,T25,T30

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T1,T3
1	0	Covered	T1,T25,T30
1	1	Covered	T5,T1,T3

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1180808185	7759	0	0
SrcPulseCheck_M	6294349	7759	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1180808185	7759
T1	750006	26
T2	127048	0
T3	216477	7
T4	466496	3
T5	383560	5
T6	0	13
T23	51093	0
T24	246720	1
T25	626300	20
T26	373544	0
T27	246292	1
T48	0	12
T60	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6294349	7759
T1	6250	26
T2	751	0
T3	18039	7
T4	10366	3
T5	15041	5
T6	0	13
T23	408	0
T24	493	1
T25	1305	20
T26	777	0
T27	10053	1
T48	0	12
T60	0	1

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T1,T25,T30
1	0	Covered	T1,T25,T30
1	1	Covered	T1,T25,T30

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T1,T25,T30
1	0	Covered	T1,T25,T30
1	1	Covered	T1,T25,T30

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6294349	6456	0	0
SrcPulseCheck_M	1180808185	6524	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6294349	6456
T1	6250	20
T2	751	0
T3	18039	0
T4	10366	0
T8	0	138
T18	0	100
T23	408	0
T24	493	0
T25	1305	20
T26	777	0
T27	10053	0
T28	418	0
T30	0	20
T34	0	20
T64	0	20
T65	0	20
T66	0	20
T67	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1180808185	6524
T1	750006	20
T2	127048	0
T3	216477	0
T4	466496	0
T8	0	139
T18	0	100
T23	51093	0
T24	246720	0
T25	626300	20
T26	373544	0
T27	246292	0
T28	209340	0
T30	0	20
T34	0	20
T64	0	20
T65	0	20
T66	0	20
T67	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T1,T25,T30
1	0	Covered	T1,T25,T30
1	1	Covered	T1,T25,T30

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T1,T25,T30
1	0	Covered	T1,T25,T30
1	1	Covered	T1,T25,T30

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1180808185	6513	0	0
SrcPulseCheck_M	6294349	6513	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1180808185	6513
T1	750006	20
T2	127048	0
T3	216477	0
T4	466496	0
T8	0	138
T18	0	100
T23	51093	0
T24	246720	0
T25	626300	20
T26	373544	0
T27	246292	0
T28	209340	0
T30	0	20
T34	0	20
T64	0	20
T65	0	20
T66	0	20
T67	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6294349	6513
T1	6250	20
T2	751	0
T3	18039	0
T4	10366	0
T8	0	138
T18	0	100
T23	408	0
T24	493	0
T25	1305	20
T26	777	0
T27	10053	0
T28	418	0
T30	0	20
T34	0	20
T64	0	20
T65	0	20
T66	0	20
T67	0	20

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T2,T8,T9
1	0	Covered	T2,T8,T9
1	1	Covered	T14,T83,T43

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T2,T8,T9
1	0	Covered	T14,T83,T43
1	1	Covered	T2,T8,T9

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6294349	1121	0	0
SrcPulseCheck_M	1180808185	1184	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6294349	1121
T2	751	1
T3	18039	0
T4	10366	0
T8	0	1
T9	0	1
T10	0	1
T14	0	28
T15	0	1
T18	0	1
T19	0	1
T20	0	1
T21	0	1
T23	408	0
T24	493	0
T25	1305	0
T26	777	0
T27	10053	0
T28	418	0
T29	1232	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1180808185	1184
T2	127048	1
T3	216477	0
T4	466496	0
T8	0	1
T9	0	1
T10	0	1
T14	0	28
T15	0	1
T18	0	1
T19	0	1
T20	0	1
T21	0	1
T23	51093	0
T24	246720	0
T25	626300	0
T26	373544	0
T27	246292	0
T28	209340	0
T29	184871	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T2,T8,T9
1	0	Covered	T2,T8,T9
1	1	Covered	T14,T83,T43

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T2,T8,T9
1	0	Covered	T14,T83,T43
1	1	Covered	T2,T8,T9

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1180808185	1177	0	0
SrcPulseCheck_M	6294349	1177	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1180808185	1177
T2	127048	1
T3	216477	0
T4	466496	0
T8	0	1
T9	0	1
T10	0	1
T14	0	28
T15	0	1
T18	0	1
T19	0	1
T20	0	1
T21	0	1
T23	51093	0
T24	246720	0
T25	626300	0
T26	373544	0
T27	246292	0
T28	209340	0
T29	184871	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6294349	1177
T2	751	1
T3	18039	0
T4	10366	0
T8	0	1
T9	0	1
T10	0	1
T14	0	28
T15	0	1
T18	0	1
T19	0	1
T20	0	1
T21	0	1
T23	408	0
T24	493	0
T25	1305	0
T26	777	0
T27	10053	0
T28	418	0
T29	1232	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T14,T83,T43

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T1,T2
1	0	Covered	T14,T83,T43
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6294349	2081	0	0
SrcPulseCheck_M	1180808185	2143	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6294349	2081
T1	6250	1
T2	751	1
T3	18039	7
T4	10366	3
T5	15041	5
T6	0	13
T23	408	0
T24	493	0
T25	1305	0
T26	777	0
T27	10053	1
T30	0	1
T48	0	12
T56	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1180808185	2143
T1	750006	1
T2	127048	1
T3	216477	7
T4	466496	3
T5	383560	5
T6	0	13
T23	51093	0
T24	246720	0
T25	626300	0
T26	373544	0
T27	246292	1
T30	0	1
T48	0	12
T56	0	2

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T2
1	1	Covered	T14,T83,T43

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T1,T2
1	0	Covered	T14,T83,T43
1	1	Covered	T5,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1180808185	2136	0	0
SrcPulseCheck_M	6294349	2136	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1180808185	2136
T1	750006	1
T2	127048	1
T3	216477	7
T4	466496	3
T5	383560	5
T6	0	13
T23	51093	0
T24	246720	0
T25	626300	0
T26	373544	0
T27	246292	1
T30	0	1
T48	0	12
T56	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6294349	2136
T1	6250	1
T2	751	1
T3	18039	7
T4	10366	3
T5	15041	5
T6	0	13
T23	408	0
T24	493	0
T25	1305	0
T26	777	0
T27	10053	1
T30	0	1
T48	0	12
T56	0	2

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T26,T47,T8
1	0	Covered	T26,T47,T8
1	1	Covered	T26,T47,T8

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T26,T47,T8
1	0	Covered	T26,T47,T8
1	1	Covered	T26,T47,T8

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6294349	1382	0	0
SrcPulseCheck_M	1180808185	1445	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6294349	1382
T6	36286	0
T8	0	4
T14	0	2
T18	0	5
T19	0	5
T26	777	4
T27	10053	0
T28	418	0
T29	1232	0
T35	0	3
T46	496	0
T47	728	4
T48	30444	0
T56	10964	0
T57	0	5
T58	0	3
T59	0	3
T60	755	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1180808185	1445
T6	453578	0
T8	0	4
T14	0	2
T18	0	5
T19	0	5
T26	373544	4
T27	246292	0
T28	209340	0
T29	184871	0
T35	0	3
T46	136607	0
T47	353533	4
T48	243556	0
T56	712751	0
T57	0	5
T58	0	3
T59	0	3
T60	200217	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T26,T47,T8
1	0	Covered	T26,T47,T8
1	1	Covered	T26,T47,T8

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T26,T47,T8
1	0	Covered	T26,T47,T8
1	1	Covered	T26,T47,T8

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1180808185	1438	0	0
SrcPulseCheck_M	6294349	1438	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1180808185	1438
T6	453578	0
T8	0	4
T14	0	2
T18	0	5
T19	0	5
T26	373544	4
T27	246292	0
T28	209340	0
T29	184871	0
T35	0	3
T46	136607	0
T47	353533	4
T48	243556	0
T56	712751	0
T57	0	5
T58	0	3
T59	0	3
T60	200217	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6294349	1438
T6	36286	0
T8	0	4
T14	0	2
T18	0	5
T19	0	5
T26	777	4
T27	10053	0
T28	418	0
T29	1232	0
T35	0	3
T46	496	0
T47	728	4
T48	30444	0
T56	10964	0
T57	0	5
T58	0	3
T59	0	3
T60	755	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T26,T47,T8
1	0	Covered	T26,T47,T8
1	1	Covered	T26,T47,T8

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T26,T47,T8
1	0	Covered	T26,T47,T8
1	1	Covered	T26,T47,T8

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6294349	1264	0	0
SrcPulseCheck_M	1180808185	1325	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6294349	1264
T6	36286	0
T8	0	3
T14	0	1
T18	0	3
T19	0	3
T26	777	3
T27	10053	0
T28	418	0
T29	1232	0
T35	0	3
T46	496	0
T47	728	3
T48	30444	0
T56	10964	0
T57	0	3
T58	0	3
T59	0	3
T60	755	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1180808185	1325
T6	453578	0
T8	0	3
T14	0	1
T18	0	3
T19	0	3
T26	373544	3
T27	246292	0
T28	209340	0
T29	184871	0
T35	0	3
T46	136607	0
T47	353533	3
T48	243556	0
T56	712751	0
T57	0	3
T58	0	3
T59	0	3
T60	200217	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T26,T47,T8
1	0	Covered	T26,T47,T8
1	1	Covered	T26,T47,T8

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T26,T47,T8
1	0	Covered	T26,T47,T8
1	1	Covered	T26,T47,T8

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1180808185	1318	0	0
SrcPulseCheck_M	6294349	1318	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1180808185	1318
T6	453578	0
T8	0	3
T14	0	1
T18	0	3
T19	0	3
T26	373544	3
T27	246292	0
T28	209340	0
T29	184871	0
T35	0	3
T46	136607	0
T47	353533	3
T48	243556	0
T56	712751	0
T57	0	3
T58	0	3
T59	0	3
T60	200217	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6294349	1318
T6	36286	0
T8	0	3
T14	0	1
T18	0	3
T19	0	3
T26	777	3
T27	10053	0
T28	418	0
T29	1232	0
T35	0	3
T46	496	0
T47	728	3
T48	30444	0
T56	10964	0
T57	0	3
T58	0	3
T59	0	3
T60	755	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T27,T48,T6
1	0	Covered	T27,T48,T6
1	1	Covered	T27,T48,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T27,T48,T6
1	0	Covered	T27,T48,T6
1	1	Covered	T27,T48,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6294349	7264	0	0
SrcPulseCheck_M	1180808185	7333	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6294349	7264
T6	36286	90
T11	0	1
T13	0	89
T14	0	11
T17	0	81
T27	10053	79
T28	418	0
T29	1232	0
T46	496	0
T47	728	0
T48	30444	86
T56	10964	66
T60	755	0
T61	494	0
T68	0	88
T69	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1180808185	7333
T6	453578	90
T11	0	1
T13	0	89
T14	0	11
T17	0	81
T27	246292	79
T28	209340	0
T29	184871	0
T46	136607	0
T47	353533	0
T48	243556	86
T56	712751	66
T60	200217	0
T61	135832	0
T68	0	88
T69	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T27,T48,T6
1	0	Covered	T27,T48,T6
1	1	Covered	T27,T48,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T27,T48,T6
1	0	Covered	T27,T48,T6
1	1	Covered	T27,T48,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1180808185	7325	0	0
SrcPulseCheck_M	6294349	7325	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1180808185	7325
T6	453578	90
T11	0	1
T13	0	89
T14	0	11
T17	0	81
T27	246292	79
T28	209340	0
T29	184871	0
T46	136607	0
T47	353533	0
T48	243556	86
T56	712751	66
T60	200217	0
T61	135832	0
T68	0	88
T69	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6294349	7325
T6	36286	90
T11	0	1
T13	0	89
T14	0	11
T17	0	81
T27	10053	79
T28	418	0
T29	1232	0
T46	496	0
T47	728	0
T48	30444	86
T56	10964	66
T60	755	0
T61	494	0
T68	0	88
T69	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T27,T48,T6
1	0	Covered	T27,T48,T6
1	1	Covered	T27,T48,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T27,T48,T6
1	0	Covered	T27,T48,T6
1	1	Covered	T27,T48,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6294349	7240	0	0
SrcPulseCheck_M	1180808185	7306	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6294349	7240
T6	36286	82
T13	0	80
T14	0	11
T17	0	66
T27	10053	70
T28	418	0
T29	1232	0
T46	496	0
T47	728	0
T48	30444	90
T56	10964	80
T60	755	0
T61	494	0
T68	0	73
T69	0	51
T70	0	58

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1180808185	7306
T6	453578	82
T13	0	80
T14	0	11
T17	0	66
T27	246292	70
T28	209340	0
T29	184871	0
T46	136607	0
T47	353533	0
T48	243556	90
T56	712751	80
T60	200217	0
T61	135832	0
T68	0	73
T69	0	51
T70	0	58

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T27,T48,T6
1	0	Covered	T27,T48,T6
1	1	Covered	T27,T48,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T27,T48,T6
1	0	Covered	T27,T48,T6
1	1	Covered	T27,T48,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1180808185	7298	0	0
SrcPulseCheck_M	6294349	7298	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1180808185	7298
T6	453578	82
T13	0	80
T14	0	11
T17	0	66
T27	246292	70
T28	209340	0
T29	184871	0
T46	136607	0
T47	353533	0
T48	243556	90
T56	712751	80
T60	200217	0
T61	135832	0
T68	0	73
T69	0	51
T70	0	58

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6294349	7298
T6	36286	82
T13	0	80
T14	0	11
T17	0	66
T27	10053	70
T28	418	0
T29	1232	0
T46	496	0
T47	728	0
T48	30444	90
T56	10964	80
T60	755	0
T61	494	0
T68	0	73
T69	0	51
T70	0	58

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T27,T48,T6
1	0	Covered	T27,T48,T6
1	1	Covered	T27,T48,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T27,T48,T6
1	0	Covered	T27,T48,T6
1	1	Covered	T27,T48,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6294349	7055	0	0
SrcPulseCheck_M	1180808185	7120	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6294349	7055
T6	36286	68
T13	0	78
T14	0	11
T17	0	72
T27	10053	62
T28	418	0
T29	1232	0
T46	496	0
T47	728	0
T48	30444	73
T56	10964	60
T60	755	0
T61	494	0
T68	0	63
T69	0	51
T70	0	77

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1180808185	7120
T6	453578	68
T13	0	78
T14	0	11
T17	0	72
T27	246292	62
T28	209340	0
T29	184871	0
T46	136607	0
T47	353533	0
T48	243556	73
T56	712751	60
T60	200217	0
T61	135832	0
T68	0	63
T69	0	51
T70	0	77

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T27,T48,T6
1	0	Covered	T27,T48,T6
1	1	Covered	T27,T48,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T27,T48,T6
1	0	Covered	T27,T48,T6
1	1	Covered	T27,T48,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1180808185	7114	0	0
SrcPulseCheck_M	6294349	7114	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1180808185	7114
T6	453578	68
T13	0	78
T14	0	11
T17	0	72
T27	246292	62
T28	209340	0
T29	184871	0
T46	136607	0
T47	353533	0
T48	243556	73
T56	712751	60
T60	200217	0
T61	135832	0
T68	0	63
T69	0	51
T70	0	77

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6294349	7114
T6	36286	68
T13	0	78
T14	0	11
T17	0	72
T27	10053	62
T28	418	0
T29	1232	0
T46	496	0
T47	728	0
T48	30444	73
T56	10964	60
T60	755	0
T61	494	0
T68	0	63
T69	0	51
T70	0	77

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T27,T48,T6
1	0	Covered	T27,T48,T6
1	1	Covered	T27,T48,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T27,T48,T6
1	0	Covered	T27,T48,T6
1	1	Covered	T27,T48,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6294349	7139	0	0
SrcPulseCheck_M	1180808185	7205	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6294349	7139
T6	36286	99
T13	0	64
T14	0	11
T17	0	56
T27	10053	75
T28	418	0
T29	1232	0
T46	496	0
T47	728	0
T48	30444	81
T56	10964	74
T60	755	0
T61	494	0
T68	0	75
T69	0	51
T70	0	77

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1180808185	7205
T6	453578	99
T13	0	64
T14	0	11
T17	0	56
T27	246292	75
T28	209340	0
T29	184871	0
T46	136607	0
T47	353533	0
T48	243556	81
T56	712751	74
T60	200217	0
T61	135832	0
T68	0	75
T69	0	51
T70	0	77

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T27,T48,T6
1	0	Covered	T27,T48,T6
1	1	Covered	T27,T48,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T27,T48,T6
1	0	Covered	T27,T48,T6
1	1	Covered	T27,T48,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1180808185	7198	0	0
SrcPulseCheck_M	6294349	7198	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1180808185	7198
T6	453578	99
T13	0	64
T14	0	11
T17	0	56
T27	246292	75
T28	209340	0
T29	184871	0
T46	136607	0
T47	353533	0
T48	243556	81
T56	712751	74
T60	200217	0
T61	135832	0
T68	0	75
T69	0	51
T70	0	77

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6294349	7198
T6	36286	99
T13	0	64
T14	0	11
T17	0	56
T27	10053	75
T28	418	0
T29	1232	0
T46	496	0
T47	728	0
T48	30444	81
T56	10964	74
T60	755	0
T61	494	0
T68	0	75
T69	0	51
T70	0	77

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T27,T48,T6
1	0	Covered	T27,T48,T6
1	1	Covered	T14,T83,T43

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T27,T48,T6
1	0	Covered	T14,T83,T43
1	1	Covered	T27,T48,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6294349	1363	0	0
SrcPulseCheck_M	1180808185	1426	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6294349	1363
T6	36286	13
T11	0	1
T13	0	7
T14	0	9
T17	0	6
T27	10053	1
T28	418	0
T29	1232	0
T46	496	0
T47	728	0
T48	30444	12
T56	10964	2
T60	755	0
T61	494	0
T68	0	6
T69	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1180808185	1426
T6	453578	13
T11	0	1
T13	0	7
T14	0	9
T17	0	6
T27	246292	1
T28	209340	0
T29	184871	0
T46	136607	0
T47	353533	0
T48	243556	12
T56	712751	2
T60	200217	0
T61	135832	0
T68	0	6
T69	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T27,T48,T6
1	0	Covered	T27,T48,T6
1	1	Covered	T14,T83,T43

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T27,T48,T6
1	0	Covered	T14,T83,T43
1	1	Covered	T27,T48,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1180808185	1419	0	0
SrcPulseCheck_M	6294349	1419	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1180808185	1419
T6	453578	13
T11	0	1
T13	0	7
T14	0	9
T17	0	6
T27	246292	1
T28	209340	0
T29	184871	0
T46	136607	0
T47	353533	0
T48	243556	12
T56	712751	2
T60	200217	0
T61	135832	0
T68	0	6
T69	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6294349	1419
T6	36286	13
T11	0	1
T13	0	7
T14	0	9
T17	0	6
T27	10053	1
T28	418	0
T29	1232	0
T46	496	0
T47	728	0
T48	30444	12
T56	10964	2
T60	755	0
T61	494	0
T68	0	6
T69	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T27,T48,T6
1	0	Covered	T27,T48,T6
1	1	Covered	T14,T83,T43

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T27,T48,T6
1	0	Covered	T14,T83,T43
1	1	Covered	T27,T48,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6294349	1359	0	0
SrcPulseCheck_M	1180808185	1424	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6294349	1359
T6	36286	13
T13	0	7
T14	0	9
T17	0	6
T27	10053	1
T28	418	0
T29	1232	0
T46	496	0
T47	728	0
T48	30444	12
T56	10964	2
T60	755	0
T61	494	0
T68	0	6
T69	0	1
T70	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1180808185	1424
T6	453578	13
T13	0	7
T14	0	9
T17	0	6
T27	246292	1
T28	209340	0
T29	184871	0
T46	136607	0
T47	353533	0
T48	243556	12
T56	712751	2
T60	200217	0
T61	135832	0
T68	0	6
T69	0	1
T70	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T27,T48,T6
1	0	Covered	T27,T48,T6
1	1	Covered	T14,T83,T43

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T27,T48,T6
1	0	Covered	T14,T83,T43
1	1	Covered	T27,T48,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1180808185	1416	0	0
SrcPulseCheck_M	6294349	1416	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1180808185	1416
T6	453578	13
T13	0	7
T14	0	9
T17	0	6
T27	246292	1
T28	209340	0
T29	184871	0
T46	136607	0
T47	353533	0
T48	243556	12
T56	712751	2
T60	200217	0
T61	135832	0
T68	0	6
T69	0	1
T70	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6294349	1416
T6	36286	13
T13	0	7
T14	0	9
T17	0	6
T27	10053	1
T28	418	0
T29	1232	0
T46	496	0
T47	728	0
T48	30444	12
T56	10964	2
T60	755	0
T61	494	0
T68	0	6
T69	0	1
T70	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T27,T48,T6
1	0	Covered	T27,T48,T6
1	1	Covered	T14,T83,T43

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T27,T48,T6
1	0	Covered	T14,T83,T43
1	1	Covered	T27,T48,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6294349	1340	0	0
SrcPulseCheck_M	1180808185	1401	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6294349	1340
T6	36286	13
T13	0	7
T14	0	9
T17	0	6
T27	10053	1
T28	418	0
T29	1232	0
T46	496	0
T47	728	0
T48	30444	12
T56	10964	2
T60	755	0
T61	494	0
T68	0	6
T69	0	1
T70	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1180808185	1401
T6	453578	13
T13	0	7
T14	0	9
T17	0	6
T27	246292	1
T28	209340	0
T29	184871	0
T46	136607	0
T47	353533	0
T48	243556	12
T56	712751	2
T60	200217	0
T61	135832	0
T68	0	6
T69	0	1
T70	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T27,T48,T6
1	0	Covered	T27,T48,T6
1	1	Covered	T14,T83,T43

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T27,T48,T6
1	0	Covered	T14,T83,T43
1	1	Covered	T27,T48,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1180808185	1392	0	0
SrcPulseCheck_M	6294349	1392	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1180808185	1392
T6	453578	13
T13	0	7
T14	0	9
T17	0	6
T27	246292	1
T28	209340	0
T29	184871	0
T46	136607	0
T47	353533	0
T48	243556	12
T56	712751	2
T60	200217	0
T61	135832	0
T68	0	6
T69	0	1
T70	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6294349	1392
T6	36286	13
T13	0	7
T14	0	9
T17	0	6
T27	10053	1
T28	418	0
T29	1232	0
T46	496	0
T47	728	0
T48	30444	12
T56	10964	2
T60	755	0
T61	494	0
T68	0	6
T69	0	1
T70	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T27,T48,T6
1	0	Covered	T27,T48,T6
1	1	Covered	T14,T83,T43

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T27,T48,T6
1	0	Covered	T14,T83,T43
1	1	Covered	T27,T48,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6294349	1373	0	0
SrcPulseCheck_M	1180808185	1431	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6294349	1373
T6	36286	13
T13	0	7
T14	0	9
T17	0	6
T27	10053	1
T28	418	0
T29	1232	0
T46	496	0
T47	728	0
T48	30444	12
T56	10964	2
T60	755	0
T61	494	0
T68	0	6
T69	0	1
T70	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1180808185	1431
T6	453578	13
T13	0	7
T14	0	9
T17	0	6
T27	246292	1
T28	209340	0
T29	184871	0
T46	136607	0
T47	353533	0
T48	243556	12
T56	712751	2
T60	200217	0
T61	135832	0
T68	0	6
T69	0	1
T70	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T27,T48,T6
1	0	Covered	T27,T48,T6
1	1	Covered	T14,T83,T43

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T27,T48,T6
1	0	Covered	T14,T83,T43
1	1	Covered	T27,T48,T6

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1180808185	1423	0	0
SrcPulseCheck_M	6294349	1423	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1180808185	1423
T6	453578	13
T13	0	7
T14	0	9
T17	0	6
T27	246292	1
T28	209340	0
T29	184871	0
T46	136607	0
T47	353533	0
T48	243556	12
T56	712751	2
T60	200217	0
T61	135832	0
T68	0	6
T69	0	1
T70	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6294349	1423
T6	36286	13
T13	0	7
T14	0	9
T17	0	6
T27	10053	1
T28	418	0
T29	1232	0
T46	496	0
T47	728	0
T48	30444	12
T56	10964	2
T60	755	0
T61	494	0
T68	0	6
T69	0	1
T70	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T1,T3
1	0	Covered	T5,T1,T3
1	1	Covered	T27,T48,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T1,T3
1	0	Covered	T27,T48,T6
1	1	Covered	T5,T1,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6294349	7913	0	0
SrcPulseCheck_M	1180808185	7981	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6294349	7913
T1	6250	1
T2	751	0
T3	18039	7
T4	10366	3
T5	15041	5
T6	0	90
T8	0	2
T23	408	0
T24	493	0
T25	1305	0
T26	777	0
T27	10053	79
T30	0	1
T48	0	86
T56	0	66

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1180808185	7981
T1	750006	1
T2	127048	0
T3	216477	7
T4	466496	3
T5	383560	5
T6	0	90
T8	0	2
T23	51093	0
T24	246720	0
T25	626300	0
T26	373544	0
T27	246292	79
T30	0	1
T48	0	86
T56	0	66

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T1,T3
1	0	Covered	T5,T1,T3
1	1	Covered	T27,T48,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T1,T3
1	0	Covered	T27,T48,T6
1	1	Covered	T5,T1,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1180808185	7974	0	0
SrcPulseCheck_M	6294349	7974	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1180808185	7974
T1	750006	1
T2	127048	0
T3	216477	7
T4	466496	3
T5	383560	5
T6	0	90
T8	0	2
T23	51093	0
T24	246720	0
T25	626300	0
T26	373544	0
T27	246292	79
T30	0	1
T48	0	86
T56	0	66

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6294349	7974
T1	6250	1
T2	751	0
T3	18039	7
T4	10366	3
T5	15041	5
T6	0	90
T8	0	2
T23	408	0
T24	493	0
T25	1305	0
T26	777	0
T27	10053	79
T30	0	1
T48	0	86
T56	0	66

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T3,T4
1	0	Covered	T5,T3,T4
1	1	Covered	T27,T48,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T3,T4
1	0	Covered	T27,T48,T6
1	1	Covered	T5,T3,T4

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6294349	7797	0	0
SrcPulseCheck_M	1180808185	7859	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6294349	7797
T1	6250	0
T2	751	0
T3	18039	7
T4	10366	3
T5	15041	5
T6	0	82
T12	0	9
T13	0	80
T14	0	11
T23	408	0
T24	493	0
T25	1305	0
T26	777	0
T27	10053	70
T48	0	90
T56	0	80

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1180808185	7859
T1	750006	0
T2	127048	0
T3	216477	7
T4	466496	3
T5	383560	5
T6	0	82
T12	0	9
T13	0	80
T14	0	11
T23	51093	0
T24	246720	0
T25	626300	0
T26	373544	0
T27	246292	70
T48	0	90
T56	0	80

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T3,T4
1	0	Covered	T5,T3,T4
1	1	Covered	T27,T48,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T3,T4
1	0	Covered	T27,T48,T6
1	1	Covered	T5,T3,T4

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1180808185	7852	0	0
SrcPulseCheck_M	6294349	7852	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1180808185	7852
T1	750006	0
T2	127048	0
T3	216477	7
T4	466496	3
T5	383560	5
T6	0	82
T12	0	9
T13	0	80
T14	0	11
T23	51093	0
T24	246720	0
T25	626300	0
T26	373544	0
T27	246292	70
T48	0	90
T56	0	80

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6294349	7852
T1	6250	0
T2	751	0
T3	18039	7
T4	10366	3
T5	15041	5
T6	0	82
T12	0	9
T13	0	80
T14	0	11
T23	408	0
T24	493	0
T25	1305	0
T26	777	0
T27	10053	70
T48	0	90
T56	0	80

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T3,T4
1	0	Covered	T5,T3,T4
1	1	Covered	T27,T48,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T3,T4
1	0	Covered	T27,T48,T6
1	1	Covered	T5,T3,T4

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6294349	7652	0	0
SrcPulseCheck_M	1180808185	7723	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6294349	7652
T1	6250	0
T2	751	0
T3	18039	7
T4	10366	3
T5	15041	5
T6	0	68
T12	0	9
T13	0	78
T14	0	11
T23	408	0
T24	493	0
T25	1305	0
T26	777	0
T27	10053	62
T48	0	73
T56	0	60

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1180808185	7723
T1	750006	0
T2	127048	0
T3	216477	7
T4	466496	3
T5	383560	5
T6	0	68
T12	0	9
T13	0	78
T14	0	11
T23	51093	0
T24	246720	0
T25	626300	0
T26	373544	0
T27	246292	62
T48	0	73
T56	0	60

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T3,T4
1	0	Covered	T5,T3,T4
1	1	Covered	T27,T48,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T3,T4
1	0	Covered	T27,T48,T6
1	1	Covered	T5,T3,T4

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1180808185	7715	0	0
SrcPulseCheck_M	6294349	7715	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1180808185	7715
T1	750006	0
T2	127048	0
T3	216477	7
T4	466496	3
T5	383560	5
T6	0	68
T12	0	9
T13	0	78
T14	0	11
T23	51093	0
T24	246720	0
T25	626300	0
T26	373544	0
T27	246292	62
T48	0	73
T56	0	60

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6294349	7715
T1	6250	0
T2	751	0
T3	18039	7
T4	10366	3
T5	15041	5
T6	0	68
T12	0	9
T13	0	78
T14	0	11
T23	408	0
T24	493	0
T25	1305	0
T26	777	0
T27	10053	62
T48	0	73
T56	0	60

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T3,T4
1	0	Covered	T5,T3,T4
1	1	Covered	T27,T48,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T3,T4
1	0	Covered	T27,T48,T6
1	1	Covered	T5,T3,T4

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6294349	7742	0	0
SrcPulseCheck_M	1180808185	7803	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6294349	7742
T1	6250	0
T2	751	0
T3	18039	7
T4	10366	3
T5	15041	5
T6	0	99
T12	0	9
T13	0	64
T14	0	11
T23	408	0
T24	493	0
T25	1305	0
T26	777	0
T27	10053	75
T48	0	81
T56	0	74

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1180808185	7803
T1	750006	0
T2	127048	0
T3	216477	7
T4	466496	3
T5	383560	5
T6	0	99
T12	0	9
T13	0	64
T14	0	11
T23	51093	0
T24	246720	0
T25	626300	0
T26	373544	0
T27	246292	75
T48	0	81
T56	0	74

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T3,T4
1	0	Covered	T5,T3,T4
1	1	Covered	T27,T48,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T3,T4
1	0	Covered	T27,T48,T6
1	1	Covered	T5,T3,T4

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1180808185	7796	0	0
SrcPulseCheck_M	6294349	7796	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1180808185	7796
T1	750006	0
T2	127048	0
T3	216477	7
T4	466496	3
T5	383560	5
T6	0	99
T12	0	9
T13	0	64
T14	0	11
T23	51093	0
T24	246720	0
T25	626300	0
T26	373544	0
T27	246292	75
T48	0	81
T56	0	74

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6294349	7796
T1	6250	0
T2	751	0
T3	18039	7
T4	10366	3
T5	15041	5
T6	0	99
T12	0	9
T13	0	64
T14	0	11
T23	408	0
T24	493	0
T25	1305	0
T26	777	0
T27	10053	75
T48	0	81
T56	0	74

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T1,T3
1	0	Covered	T5,T1,T3
1	1	Covered	T14,T83,T43

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T1,T3
1	0	Covered	T14,T83,T43
1	1	Covered	T5,T1,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6294349	1979	0	0
SrcPulseCheck_M	1180808185	2040	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6294349	1979
T1	6250	1
T2	751	0
T3	18039	7
T4	10366	3
T5	15041	5
T6	0	13
T8	0	2
T23	408	0
T24	493	0
T25	1305	0
T26	777	0
T27	10053	1
T30	0	1
T48	0	12
T56	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1180808185	2040
T1	750006	1
T2	127048	0
T3	216477	7
T4	466496	3
T5	383560	5
T6	0	13
T8	0	2
T23	51093	0
T24	246720	0
T25	626300	0
T26	373544	0
T27	246292	1
T30	0	1
T48	0	12
T56	0	2

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T1,T3
1	0	Covered	T5,T1,T3
1	1	Covered	T14,T83,T43

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T1,T3
1	0	Covered	T14,T83,T43
1	1	Covered	T5,T1,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1180808185	2032	0	0
SrcPulseCheck_M	6294349	2032	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1180808185	2032
T1	750006	1
T2	127048	0
T3	216477	7
T4	466496	3
T5	383560	5
T6	0	13
T8	0	2
T23	51093	0
T24	246720	0
T25	626300	0
T26	373544	0
T27	246292	1
T30	0	1
T48	0	12
T56	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6294349	2032
T1	6250	1
T2	751	0
T3	18039	7
T4	10366	3
T5	15041	5
T6	0	13
T8	0	2
T23	408	0
T24	493	0
T25	1305	0
T26	777	0
T27	10053	1
T30	0	1
T48	0	12
T56	0	2

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T3,T4
1	0	Covered	T5,T3,T4
1	1	Covered	T14,T83,T43

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T3,T4
1	0	Covered	T14,T83,T43
1	1	Covered	T5,T3,T4

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6294349	1930	0	0
SrcPulseCheck_M	1180808185	1988	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6294349	1930
T1	6250	0
T2	751	0
T3	18039	7
T4	10366	3
T5	15041	5
T6	0	13
T12	0	9
T13	0	7
T14	0	9
T23	408	0
T24	493	0
T25	1305	0
T26	777	0
T27	10053	1
T48	0	12
T56	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1180808185	1988
T1	750006	0
T2	127048	0
T3	216477	7
T4	466496	3
T5	383560	5
T6	0	13
T12	0	9
T13	0	7
T14	0	9
T23	51093	0
T24	246720	0
T25	626300	0
T26	373544	0
T27	246292	1
T48	0	12
T56	0	2

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T3,T4
1	0	Covered	T5,T3,T4
1	1	Covered	T14,T83,T43

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T3,T4
1	0	Covered	T14,T83,T43
1	1	Covered	T5,T3,T4

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1180808185	1981	0	0
SrcPulseCheck_M	6294349	1981	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1180808185	1981
T1	750006	0
T2	127048	0
T3	216477	7
T4	466496	3
T5	383560	5
T6	0	13
T12	0	9
T13	0	7
T14	0	9
T23	51093	0
T24	246720	0
T25	626300	0
T26	373544	0
T27	246292	1
T48	0	12
T56	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6294349	1981
T1	6250	0
T2	751	0
T3	18039	7
T4	10366	3
T5	15041	5
T6	0	13
T12	0	9
T13	0	7
T14	0	9
T23	408	0
T24	493	0
T25	1305	0
T26	777	0
T27	10053	1
T48	0	12
T56	0	2

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T3,T4
1	0	Covered	T5,T3,T4
1	1	Covered	T14,T83,T43

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T3,T4
1	0	Covered	T14,T83,T43
1	1	Covered	T5,T3,T4

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6294349	1897	0	0
SrcPulseCheck_M	1180808185	1961	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6294349	1897
T1	6250	0
T2	751	0
T3	18039	7
T4	10366	3
T5	15041	5
T6	0	13
T12	0	9
T13	0	7
T14	0	9
T23	408	0
T24	493	0
T25	1305	0
T26	777	0
T27	10053	1
T48	0	12
T56	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1180808185	1961
T1	750006	0
T2	127048	0
T3	216477	7
T4	466496	3
T5	383560	5
T6	0	13
T12	0	9
T13	0	7
T14	0	9
T23	51093	0
T24	246720	0
T25	626300	0
T26	373544	0
T27	246292	1
T48	0	12
T56	0	2

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T3,T4
1	0	Covered	T5,T3,T4
1	1	Covered	T14,T83,T43

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T3,T4
1	0	Covered	T14,T83,T43
1	1	Covered	T5,T3,T4

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1180808185	1954	0	0
SrcPulseCheck_M	6294349	1954	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1180808185	1954
T1	750006	0
T2	127048	0
T3	216477	7
T4	466496	3
T5	383560	5
T6	0	13
T12	0	9
T13	0	7
T14	0	9
T23	51093	0
T24	246720	0
T25	626300	0
T26	373544	0
T27	246292	1
T48	0	12
T56	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6294349	1954
T1	6250	0
T2	751	0
T3	18039	7
T4	10366	3
T5	15041	5
T6	0	13
T12	0	9
T13	0	7
T14	0	9
T23	408	0
T24	493	0
T25	1305	0
T26	777	0
T27	10053	1
T48	0	12
T56	0	2

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T3,T4
1	0	Covered	T5,T3,T4
1	1	Covered	T14,T83,T43

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T3,T4
1	0	Covered	T14,T83,T43
1	1	Covered	T5,T3,T4

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6294349	1912	0	0
SrcPulseCheck_M	1180808185	1977	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6294349	1912
T1	6250	0
T2	751	0
T3	18039	7
T4	10366	3
T5	15041	5
T6	0	13
T12	0	9
T13	0	7
T14	0	9
T23	408	0
T24	493	0
T25	1305	0
T26	777	0
T27	10053	1
T48	0	12
T56	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1180808185	1977
T1	750006	0
T2	127048	0
T3	216477	7
T4	466496	3
T5	383560	5
T6	0	13
T12	0	9
T13	0	7
T14	0	9
T23	51093	0
T24	246720	0
T25	626300	0
T26	373544	0
T27	246292	1
T48	0	12
T56	0	2

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T3,T4
1	0	Covered	T5,T3,T4
1	1	Covered	T14,T83,T43

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T3,T4
1	0	Covered	T14,T83,T43
1	1	Covered	T5,T3,T4

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1180808185	1970	0	0
SrcPulseCheck_M	6294349	1970	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1180808185	1970
T1	750006	0
T2	127048	0
T3	216477	7
T4	466496	3
T5	383560	5
T6	0	13
T12	0	9
T13	0	7
T14	0	9
T23	51093	0
T24	246720	0
T25	626300	0
T26	373544	0
T27	246292	1
T48	0	12
T56	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6294349	1970
T1	6250	0
T2	751	0
T3	18039	7
T4	10366	3
T5	15041	5
T6	0	13
T12	0	9
T13	0	7
T14	0	9
T23	408	0
T24	493	0
T25	1305	0
T26	777	0
T27	10053	1
T48	0	12
T56	0	2

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T1,T3
1	0	Covered	T5,T1,T3
1	1	Covered	T14,T83,T43

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T1,T3
1	0	Covered	T14,T83,T43
1	1	Covered	T5,T1,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6294349	1947	0	0
SrcPulseCheck_M	1180808185	2007	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6294349	1947
T1	6250	1
T2	751	0
T3	18039	7
T4	10366	3
T5	15041	5
T6	0	13
T8	0	2
T23	408	0
T24	493	0
T25	1305	0
T26	777	0
T27	10053	1
T30	0	1
T48	0	12
T56	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1180808185	2007
T1	750006	1
T2	127048	0
T3	216477	7
T4	466496	3
T5	383560	5
T6	0	13
T8	0	2
T23	51093	0
T24	246720	0
T25	626300	0
T26	373544	0
T27	246292	1
T30	0	1
T48	0	12
T56	0	2

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T1,T3
1	0	Covered	T5,T1,T3
1	1	Covered	T14,T83,T43

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T1,T3
1	0	Covered	T14,T83,T43
1	1	Covered	T5,T1,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1180808185	2000	0	0
SrcPulseCheck_M	6294349	2000	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1180808185	2000
T1	750006	1
T2	127048	0
T3	216477	7
T4	466496	3
T5	383560	5
T6	0	13
T8	0	2
T23	51093	0
T24	246720	0
T25	626300	0
T26	373544	0
T27	246292	1
T30	0	1
T48	0	12
T56	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6294349	2000
T1	6250	1
T2	751	0
T3	18039	7
T4	10366	3
T5	15041	5
T6	0	13
T8	0	2
T23	408	0
T24	493	0
T25	1305	0
T26	777	0
T27	10053	1
T30	0	1
T48	0	12
T56	0	2

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T3,T4
1	0	Covered	T5,T3,T4
1	1	Covered	T14,T83,T43

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T3,T4
1	0	Covered	T14,T83,T43
1	1	Covered	T5,T3,T4

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6294349	1911	0	0
SrcPulseCheck_M	1180808185	1972	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6294349	1911
T1	6250	0
T2	751	0
T3	18039	7
T4	10366	3
T5	15041	5
T6	0	13
T12	0	9
T13	0	7
T14	0	9
T23	408	0
T24	493	0
T25	1305	0
T26	777	0
T27	10053	1
T48	0	12
T56	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1180808185	1972
T1	750006	0
T2	127048	0
T3	216477	7
T4	466496	3
T5	383560	5
T6	0	13
T12	0	9
T13	0	7
T14	0	9
T23	51093	0
T24	246720	0
T25	626300	0
T26	373544	0
T27	246292	1
T48	0	12
T56	0	2

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T3,T4
1	0	Covered	T5,T3,T4
1	1	Covered	T14,T83,T43

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T3,T4
1	0	Covered	T14,T83,T43
1	1	Covered	T5,T3,T4

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1180808185	1965	0	0
SrcPulseCheck_M	6294349	1965	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1180808185	1965
T1	750006	0
T2	127048	0
T3	216477	7
T4	466496	3
T5	383560	5
T6	0	13
T12	0	9
T13	0	7
T14	0	9
T23	51093	0
T24	246720	0
T25	626300	0
T26	373544	0
T27	246292	1
T48	0	12
T56	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6294349	1965
T1	6250	0
T2	751	0
T3	18039	7
T4	10366	3
T5	15041	5
T6	0	13
T12	0	9
T13	0	7
T14	0	9
T23	408	0
T24	493	0
T25	1305	0
T26	777	0
T27	10053	1
T48	0	12
T56	0	2

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T3,T4
1	0	Covered	T5,T3,T4
1	1	Covered	T14,T83,T43

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T3,T4
1	0	Covered	T14,T83,T43
1	1	Covered	T5,T3,T4

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6294349	1912	0	0
SrcPulseCheck_M	1180808185	1973	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6294349	1912
T1	6250	0
T2	751	0
T3	18039	7
T4	10366	3
T5	15041	5
T6	0	13
T12	0	9
T13	0	7
T14	0	9
T23	408	0
T24	493	0
T25	1305	0
T26	777	0
T27	10053	1
T48	0	12
T56	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1180808185	1973
T1	750006	0
T2	127048	0
T3	216477	7
T4	466496	3
T5	383560	5
T6	0	13
T12	0	9
T13	0	7
T14	0	9
T23	51093	0
T24	246720	0
T25	626300	0
T26	373544	0
T27	246292	1
T48	0	12
T56	0	2

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T3,T4
1	0	Covered	T5,T3,T4
1	1	Covered	T14,T83,T43

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T3,T4
1	0	Covered	T14,T83,T43
1	1	Covered	T5,T3,T4

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1180808185	1966	0	0
SrcPulseCheck_M	6294349	1966	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1180808185	1966
T1	750006	0
T2	127048	0
T3	216477	7
T4	466496	3
T5	383560	5
T6	0	13
T12	0	9
T13	0	7
T14	0	9
T23	51093	0
T24	246720	0
T25	626300	0
T26	373544	0
T27	246292	1
T48	0	12
T56	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6294349	1966
T1	6250	0
T2	751	0
T3	18039	7
T4	10366	3
T5	15041	5
T6	0	13
T12	0	9
T13	0	7
T14	0	9
T23	408	0
T24	493	0
T25	1305	0
T26	777	0
T27	10053	1
T48	0	12
T56	0	2

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T3,T4
1	0	Covered	T5,T3,T4
1	1	Covered	T14,T83,T43

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T3,T4
1	0	Covered	T14,T83,T43
1	1	Covered	T5,T3,T4

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6294349	1886	0	0
SrcPulseCheck_M	1180808185	1952	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6294349	1886
T1	6250	0
T2	751	0
T3	18039	7
T4	10366	3
T5	15041	5
T6	0	13
T12	0	9
T13	0	7
T14	0	9
T23	408	0
T24	493	0
T25	1305	0
T26	777	0
T27	10053	1
T48	0	12
T56	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1180808185	1952
T1	750006	0
T2	127048	0
T3	216477	7
T4	466496	3
T5	383560	5
T6	0	13
T12	0	9
T13	0	7
T14	0	9
T23	51093	0
T24	246720	0
T25	626300	0
T26	373544	0
T27	246292	1
T48	0	12
T56	0	2

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T3,T4
1	0	Covered	T5,T3,T4
1	1	Covered	T14,T83,T43

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T5,T3,T4
1	0	Covered	T14,T83,T43
1	1	Covered	T5,T3,T4

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1180808185	1944	0	0
SrcPulseCheck_M	6294349	1944	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1180808185	1944
T1	750006	0
T2	127048	0
T3	216477	7
T4	466496	3
T5	383560	5
T6	0	13
T12	0	9
T13	0	7
T14	0	9
T23	51093	0
T24	246720	0
T25	626300	0
T26	373544	0
T27	246292	1
T48	0	12
T56	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	6294349	1944
T1	6250	0
T2	751	0
T3	18039	7
T4	10366	3
T5	15041	5
T6	0	13
T12	0	9
T13	0	7
T14	0	9
T23	408	0
T24	493	0
T25	1305	0
T26	777	0
T27	10053	1
T48	0	12
T56	0	2

Line Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T4,T50,T98

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T1,T3,T4
1	0	Covered	T4,T50,T98
1	1	Covered	T1,T3,T4

Branch Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6294349	1102	0	0
SrcPulseCheck_M	1180808185	1163	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6294349	1102
T1	6250	1
T2	751	0
T3	18039	4
T4	10366	3
T6	0	4
T8	0	2
T11	0	1
T12	0	1
T13	0	6
T16	0	1
T17	0	4
T23	408	0
T24	493	0
T25	1305	0
T26	777	0
T27	10053	0
T28	418	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1180808185	1163
T1	750006	1
T2	127048	0
T3	216477	4
T4	466496	3
T6	0	4
T8	0	2
T11	0	1
T12	0	1
T13	0	6
T16	0	1
T17	0	4
T23	51093	0
T24	246720	0
T25	626300	0
T26	373544	0
T27	246292	0
T28	209340	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T2,T8,T9
1	0	Covered	T2,T8,T9
1	1	Covered	T2,T10,T15

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T2
0	1	Covered	T2,T8,T9
1	0	Covered	T2,T10,T15
1	1	Covered	T2,T8,T9

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	6294349	761	0	0
SrcPulseCheck_M	1180808185	821	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	6294349	761
T2	751	3
T3	18039	0
T4	10366	0
T8	0	1
T9	0	1
T10	0	2
T14	0	1
T15	0	2
T18	0	2
T19	0	3
T20	0	1
T21	0	2
T23	408	0
T24	493	0
T25	1305	0
T26	777	0
T27	10053	0
T28	418	0
T29	1232	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1180808185	821
T2	127048	3
T3	216477	0
T4	466496	0
T8	0	1
T9	0	1
T10	0	2
T14	0	1
T15	0	2
T18	0	2
T19	0	3
T20	0	1
T21	0	2
T23	51093	0
T24	246720	0
T25	626300	0
T26	373544	0
T27	246292	0
T28	209340	0
T29	184871	0

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_ec_rst_ctl_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_ulp_ac_debounce_ctl_cdc