Unified Coverage Report :: Module :: prim_generic_flop

Module : prim_generic_flop

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_ulp_status_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_ulp_status_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_ulp_status_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_ulp_status_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_ulp_status_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_ulp_status_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_wkup_status_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_wkup_status_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_wkup_status_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_wkup_status_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_combo_intr_status_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_combo_intr_status_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_combo_intr_status_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_combo_intr_status_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_combo_intr_status_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_combo_intr_status_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_key_intr_status_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_key_intr_status_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_key_intr_status_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_key_intr_status_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_key_intr_status_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_reg.u_key_intr_status_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_prim_flop_2sync_input.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_prim_flop_2sync_input.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_sysrst_ctrl_pin.u_cfg_ac_present_i_pin.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic	100.00	100.00				100.00
tb.dut.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic	100.00	100.00				100.00

Line Coverage for Module : prim_generic_flop

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	18	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1
19	1	1
21	1	1

---

Branch Coverage for Module : prim_generic_flop

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	18	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	18	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T5,T1,T2