Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.90	93.90	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	93.90	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.90	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	5	57	91.94

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	5	26	83.87	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2314

1

T1

6

T28

6

T2

14

auto[1]

632

1

T1

1

T28

9

T2

14

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2210

1

T1

6

T28

13

T2

28

auto[1]

736

1

T1

1

T28

2

T3

8

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2217

1

T1

5

T28

6

T2

28

auto[1]

729

1

T1

2

T28

9

T3

2

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2288

1

T1

1

T28

7

T2

25

auto[1]

658

1

T1

6

T28

8

T2

3

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2691

1

T1

7

T28

15

T2

28

auto[1]

255

1

T7

12

T9

4

T10

1

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2681

1

T1

7

T28

15

T2

11

auto[1]

265

1

T2

17

T7

20

T10

1

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2617

1

T1

7

T28

15

T2

11

auto[1]

329

1

T2

17

T9

2

T10

1

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2637

1

T1

7

T28

15

T2

28

auto[1]

309

1

T7

4

T9

2

T10

1

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2725

1

T1

7

T28

15

T2

25

auto[1]

221

1

T2

3

T7

18

T9

2

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2148

1

T1

5

T28

9

T2

28

auto[1]

798

1

T1

2

T28

6

T3

8

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	5	26	83.87	5
Automatically Generated Cross Bins	31	5	26	83.87	5
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	*	[auto[1]]	[auto[1]]	[auto[1]]	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel

cp_precondition_key1_in_sel

cp_precondition_key2_in_sel

cp_precondition_pwrb_in_sel

cp_precondition_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

962

1

T1

7

T28

15

T3

13

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

82

1

T9

4

T68

5

T235

6

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

57

1

T336

13

T237

6

T337

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

34

1

T7

8

T68

4

T102

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

96

1

T31

6

T70

16

T102

6

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

32

1

T7

4

T338

6

T339

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

19

1

T9

2

T70

4

T330

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

94

1

T9

2

T68

7

T336

11

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

24

1

T67

1

T68

5

T70

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

12

1

T338

5

T340

5

T341

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

7

1

T85

1

T100

3

T342

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

36

1

T236

9

T321

4

T343

5

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

22

1

T131

4

T344

8

T345

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

5

1

T346

5

-

-

-

-

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

80

1

T7

10

T131

14

T100

14

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

10

1

T67

2

T340

2

T347

6

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

30

1

T7

10

T236

6

T86

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

4

1

T131

2

T348

2

-

-

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

20

1

T85

1

T86

1

T324

5

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

9

1

T343

2

T169

2

T341

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

18

1

T336

4

T349

3

T350

7

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

3

1

T351

1

T352

2

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

56

1

T2

14

T236

7

T353

4

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

6

1

T324

6

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

4

1

T2

3

T204

1

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

3

1

T10

1

T336

2

-

-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

119

1

T2

14

T12

6

T21

5

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

133

1

T7

4

T14

2

T31

6

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

89

1

T10

1

T246

4

T102

6

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

100

1

T1

5

T2

3

T21

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

66

1

T3

5

T17

6

T18

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

54

1

T28

6

T67

1

T68

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

36

1

T14

1

T18

1

T78

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

174

1

T9

2

T12

7

T17

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

57

1

T28

7

T182

4

T354

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

62

1

T85

1

T92

3

T80

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

31

1

T7

10

T16

3

T86

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

77

1

T7

8

T9

4

T67

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

25

1

T7

10

T236

6

T128

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

40

1

T1

1

T131

7

T79

5

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

8

1

T126

2

T320

1

T285

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

146

1

T68

5

T70

4

T236

9

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

55

1

T70

8

T336

13

T115

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

119

1

T3

6

T12

4

T16

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

22

1

T106

5

T340

6

T140

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

53

1

T68

7

T235

3

T100

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

14

1

T97

4

T126

3

T139

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

27

1

T9

2

T14

1

T70

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

9

1

T6

2

T355

1

T322

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

70

1

T16

6

T17

1

T97

8

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

18

1

T247

1

T356

4

T323

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

23

1

T3

2

T6

2

T78

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

10

1

T1

1

T96

4

T78

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

43

1

T102

3

T105

6

T238

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

13

1

T28

2

T97

4

T322

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

29

1

T17

2

T18

1

T106

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

3

1

T357

3

-

-

-

-

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded