Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

891

1

T26

10

T41

11

T14

9

auto[1]

839

1

T26

10

T41

9

T14

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

421

1

T26

5

T41

5

T14

4

from_0to1

420

1

T26

6

T41

5

T14

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

880

1

T26

9

T41

14

T14

8

auto[1]

850

1

T26

11

T41

6

T14

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

860

1

T26

12

T41

6

T14

8

auto[1]

870

1

T26

8

T41

14

T14

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

51

1

T41

2

T14

1

T147

1

auto[0]

from_1to0

auto[0]

auto[1]

61

1

T26

1

T41

2

T65

1

auto[0]

from_1to0

auto[1]

auto[0]

56

1

T14

2

T65

1

T147

1

auto[0]

from_1to0

auto[1]

auto[1]

58

1

T14

1

T65

1

T18

1

auto[0]

from_0to1

auto[0]

auto[0]

52

1

T65

1

T18

1

T288

1

auto[0]

from_0to1

auto[0]

auto[1]

60

1

T41

2

T14

1

T18

2

auto[0]

from_0to1

auto[1]

auto[0]

70

1

T26

1

T65

1

T18

2

auto[0]

from_0to1

auto[1]

auto[1]

43

1

T26

2

T41

2

T14

1

auto[1]

from_1to0

auto[0]

auto[0]

60

1

T26

1

T41

1

T65

1

auto[1]

from_1to0

auto[0]

auto[1]

42

1

T26

1

T65

2

T18

1

auto[1]

from_1to0

auto[1]

auto[0]

52

1

T26

1

T147

1

T94

1

auto[1]

from_1to0

auto[1]

auto[1]

41

1

T26

1

T18

1

T21

1

auto[1]

from_0to1

auto[0]

auto[0]

41

1

T26

1

T21

1

T147

2

auto[1]

from_0to1

auto[0]

auto[1]

58

1

T65

2

T21

1

T147

1

auto[1]

from_0to1

auto[1]

auto[0]

49

1

T26

2

T65

1

T18

1

auto[1]

from_0to1

auto[1]

auto[1]

47

1

T41

1

T14

1

T65

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

891

1

T26

10

T41

13

T14

8

auto[1]

839

1

T26

10

T41

7

T14

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

427

1

T26

4

T41

6

T14

4

from_0to1

422

1

T26

3

T41

5

T14

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

879

1

T26

9

T41

11

T14

10

auto[1]

851

1

T26

11

T41

9

T14

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

846

1

T26

13

T41

9

T14

8

auto[1]

884

1

T26

7

T41

11

T14

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

50

1

T26

1

T41

1

T14

1

auto[0]

from_1to0

auto[0]

auto[1]

66

1

T41

1

T18

1

T21

2

auto[0]

from_1to0

auto[1]

auto[0]

65

1

T65

2

T94

1

T288

2

auto[0]

from_1to0

auto[1]

auto[1]

49

1

T26

1

T41

1

T65

1

auto[0]

from_0to1

auto[0]

auto[0]

71

1

T26

1

T14

1

T21

3

auto[0]

from_0to1

auto[0]

auto[1]

54

1

T41

2

T18

2

T21

1

auto[0]

from_0to1

auto[1]

auto[0]

52

1

T26

1

T41

2

T14

1

auto[0]

from_0to1

auto[1]

auto[1]

49

1

T26

1

T65

1

T147

1

auto[1]

from_1to0

auto[0]

auto[0]

50

1

T26

1

T41

1

T14

1

auto[1]

from_1to0

auto[0]

auto[1]

41

1

T41

1

T94

1

T288

1

auto[1]

from_1to0

auto[1]

auto[0]

53

1

T41

1

T65

2

T18

2

auto[1]

from_1to0

auto[1]

auto[1]

53

1

T26

1

T14

2

T18

1

auto[1]

from_0to1

auto[0]

auto[0]

52

1

T41

1

T14

1

T65

2

auto[1]

from_0to1

auto[0]

auto[1]

47

1

T21

1

T147

1

T298

2

auto[1]

from_0to1

auto[1]

auto[0]

41

1

T65

1

T18

1

T147

1

auto[1]

from_0to1

auto[1]

auto[1]

56

1

T18

1

T94

1

T288

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

860

1

T26

10

T41

15

T14

9

auto[1]

870

1

T26

10

T41

5

T14

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

436

1

T26

5

T41

4

T14

5

from_0to1

444

1

T26

6

T41

5

T14

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

877

1

T26

11

T41

11

T14

12

auto[1]

853

1

T26

9

T41

9

T14

5

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

829

1

T26

13

T41

11

T14

7

auto[1]

901

1

T26

7

T41

9

T14

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

61

1

T41

1

T14

1

T65

1

auto[0]

from_1to0

auto[0]

auto[1]

72

1

T26

2

T41

1

T14

2

auto[0]

from_1to0

auto[1]

auto[0]

61

1

T41

1

T65

1

T147

1

auto[0]

from_1to0

auto[1]

auto[1]

47

1

T26

1

T18

1

T21

1

auto[0]

from_0to1

auto[0]

auto[0]

53

1

T26

3

T41

1

T14

2

auto[0]

from_0to1

auto[0]

auto[1]

55

1

T26

1

T18

1

T147

2

auto[0]

from_0to1

auto[1]

auto[0]

50

1

T41

1

T65

2

T18

1

auto[0]

from_0to1

auto[1]

auto[1]

70

1

T41

2

T14

1

T21

1

auto[1]

from_1to0

auto[0]

auto[0]

49

1

T26

1

T14

1

T147

1

auto[1]

from_1to0

auto[0]

auto[1]

54

1

T21

2

T94

2

T288

1

auto[1]

from_1to0

auto[1]

auto[0]

44

1

T26

1

T65

1

T18

3

auto[1]

from_1to0

auto[1]

auto[1]

48

1

T41

1

T14

1

T65

1

auto[1]

from_0to1

auto[0]

auto[0]

43

1

T14

1

T65

4

T21

1

auto[1]

from_0to1

auto[0]

auto[1]

61

1

T18

1

T94

1

T177

2

auto[1]

from_0to1

auto[1]

auto[0]

58

1

T26

1

T41

1

T18

1

auto[1]

from_0to1

auto[1]

auto[1]

54

1

T26

1

T21

1

T147

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

863

1

T26

12

T41

9

T14

7

auto[1]

867

1

T26

8

T41

11

T14

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

421

1

T26

4

T41

5

T14

3

from_0to1

421

1

T26

3

T41

6

T14

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

882

1

T26

9

T41

8

T14

8

auto[1]

848

1

T26

11

T41

12

T14

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

874

1

T26

8

T41

11

T14

9

auto[1]

856

1

T26

12

T41

9

T14

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

54

1

T26

1

T65

2

T94

1

auto[0]

from_1to0

auto[0]

auto[1]

53

1

T26

1

T18

1

T21

1

auto[0]

from_1to0

auto[1]

auto[0]

56

1

T14

1

T65

1

T21

2

auto[0]

from_1to0

auto[1]

auto[1]

53

1

T41

1

T21

2

T147

1

auto[0]

from_0to1

auto[0]

auto[0]

54

1

T18

1

T288

2

T298

3

auto[0]

from_0to1

auto[0]

auto[1]

48

1

T26

1

T41

1

T18

1

auto[0]

from_0to1

auto[1]

auto[0]

50

1

T26

1

T41

1

T65

3

auto[0]

from_0to1

auto[1]

auto[1]

53

1

T26

1

T41

1

T14

1

auto[1]

from_1to0

auto[0]

auto[0]

57

1

T41

2

T14

1

T65

1

auto[1]

from_1to0

auto[0]

auto[1]

53

1

T26

1

T41

1

T18

1

auto[1]

from_1to0

auto[1]

auto[0]

44

1

T41

1

T18

1

T94

1

auto[1]

from_1to0

auto[1]

auto[1]

51

1

T26

1

T14

1

T18

1

auto[1]

from_0to1

auto[0]

auto[0]

56

1

T41

1

T14

1

T65

1

auto[1]

from_0to1

auto[0]

auto[1]

57

1

T147

1

T94

1

T288

1

auto[1]

from_0to1

auto[1]

auto[0]

54

1

T41

2

T18

1

T147

1

auto[1]

from_0to1

auto[1]

auto[1]

49

1

T14

1

T18

1

T21

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

865

1

T26

8

T41

13

T14

10

auto[1]

865

1

T26

12

T41

7

T14

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

416

1

T26

5

T41

4

T14

4

from_0to1

416

1

T26

4

T41

4

T14

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

900

1

T26

11

T41

8

T14

9

auto[1]

830

1

T26

9

T41

12

T14

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

859

1

T26

9

T41

9

T14

7

auto[1]

871

1

T26

11

T41

11

T14

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

58

1

T65

2

T18

1

T21

1

auto[0]

from_1to0

auto[0]

auto[1]

56

1

T41

1

T14

1

T21

1

auto[0]

from_1to0

auto[1]

auto[0]

56

1

T26

1

T288

1

T177

1

auto[0]

from_1to0

auto[1]

auto[1]

53

1

T41

1

T14

2

T18

1

auto[0]

from_0to1

auto[0]

auto[0]

48

1

T41

1

T14

1

T94

2

auto[0]

from_0to1

auto[0]

auto[1]

64

1

T18

1

T147

2

T94

1

auto[0]

from_0to1

auto[1]

auto[0]

43

1

T26

1

T41

2

T65

1

auto[0]

from_0to1

auto[1]

auto[1]

54

1

T26

2

T65

2

T18

2

auto[1]

from_1to0

auto[0]

auto[0]

46

1

T26

2

T65

1

T18

2

auto[1]

from_1to0

auto[0]

auto[1]

51

1

T26

1

T41

1

T65

1

auto[1]

from_1to0

auto[1]

auto[0]

50

1

T26

1

T14

1

T94

2

auto[1]

from_1to0

auto[1]

auto[1]

46

1

T41

1

T65

1

T18

1

auto[1]

from_0to1

auto[0]

auto[0]

54

1

T21

2

T181

1

T298

2

auto[1]

from_0to1

auto[0]

auto[1]

57

1

T26

1

T41

1

T65

1

auto[1]

from_0to1

auto[1]

auto[0]

47

1

T14

1

T147

1

T94

1

auto[1]

from_0to1

auto[1]

auto[1]

49

1

T14

1

T21

1

T147

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

851

1

T26

10

T41

10

T14

8

auto[1]

879

1

T26

10

T41

10

T14

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

428

1

T26

3

T41

6

T14

4

from_0to1

426

1

T26

4

T41

5

T14

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

846

1

T26

10

T41

12

T14

6

auto[1]

884

1

T26

10

T41

8

T14

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

892

1

T26

10

T41

7

T14

10

auto[1]

838

1

T26

10

T41

13

T14

7

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

59

1

T26

1

T14

1

T65

1

auto[0]

from_1to0

auto[0]

auto[1]

49

1

T26

1

T41

1

T18

1

auto[0]

from_1to0

auto[1]

auto[0]

67

1

T65

1

T21

1

T147

1

auto[0]

from_1to0

auto[1]

auto[1]

43

1

T14

1

T21

1

T181

1

auto[0]

from_0to1

auto[0]

auto[0]

45

1

T210

2

T367

1

T150

1

auto[0]

from_0to1

auto[0]

auto[1]

51

1

T26

1

T41

1

T14

1

auto[0]

from_0to1

auto[1]

auto[0]

43

1

T41

1

T65

1

T94

1

auto[0]

from_0to1

auto[1]

auto[1]

55

1

T26

1

T14

2

T21

2

auto[1]

from_1to0

auto[0]

auto[0]

42

1

T41

1

T65

1

T21

1

auto[1]

from_1to0

auto[0]

auto[1]

55

1

T41

2

T14

1

T18

1

auto[1]

from_1to0

auto[1]

auto[0]

62

1

T41

1

T14

1

T18

2

auto[1]

from_1to0

auto[1]

auto[1]

51

1

T26

1

T41

1

T288

2

auto[1]

from_0to1

auto[0]

auto[0]

57

1

T18

1

T147

2

T94

1

auto[1]

from_0to1

auto[0]

auto[1]

52

1

T41

1

T18

1

T21

2

auto[1]

from_0to1

auto[1]

auto[0]

66

1

T26

1

T41

1

T18

1

auto[1]

from_0to1

auto[1]

auto[1]

57

1

T26

1

T41

1

T65

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

873

1

T26

10

T41

10

T14

4

auto[1]

857

1

T26

10

T41

10

T14

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

413

1

T26

5

T41

5

T14

4

from_0to1

412

1

T26

5

T41

4

T14

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

885

1

T26

7

T41

12

T14

10

auto[1]

845

1

T26

13

T41

8

T14

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

854

1

T26

8

T41

10

T14

9

auto[1]

876

1

T26

12

T41

10

T14

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

56

1

T26

1

T41

1

T14

1

auto[0]

from_1to0

auto[0]

auto[1]

57

1

T26

1

T65

1

T18

2

auto[0]

from_1to0

auto[1]

auto[0]

60

1

T65

1

T18

1

T21

1

auto[0]

from_1to0

auto[1]

auto[1]

47

1

T26

1

T147

1

T181

1

auto[0]

from_0to1

auto[0]

auto[0]

55

1

T65

1

T21

1

T147

1

auto[0]

from_0to1

auto[0]

auto[1]

54

1

T26

1

T41

2

T14

1

auto[0]

from_0to1

auto[1]

auto[0]

49

1

T26

1

T21

1

T298

1

auto[0]

from_0to1

auto[1]

auto[1]

53

1

T41

1

T147

1

T94

2

auto[1]

from_1to0

auto[0]

auto[0]

54

1

T41

1

T14

1

T65

1

auto[1]

from_1to0

auto[0]

auto[1]

46

1

T26

1

T41

1

T21

1

auto[1]

from_1to0

auto[1]

auto[0]

55

1

T26

1

T14

1

T65

1

auto[1]

from_1to0

auto[1]

auto[1]

38

1

T41

2

T14

1

T288

2

auto[1]

from_0to1

auto[0]

auto[0]

53

1

T14

1

T65

2

T18

1

auto[1]

from_0to1

auto[0]

auto[1]

48

1

T65

1

T18

2

T94

1

auto[1]

from_0to1

auto[1]

auto[0]

46

1

T26

2

T41

1

T288

1

auto[1]

from_0to1

auto[1]

auto[1]

54

1

T26

1

T14

1

T65

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

890

1

T26

10

T41

13

T14

10

auto[1]

840

1

T26

10

T41

7

T14

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

402

1

T26

6

T41

4

T14

4

from_0to1

400

1

T26

6

T41

4

T14

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

848

1

T26

10

T41

8

T14

7

auto[1]

882

1

T26

10

T41

12

T14

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

843

1

T26

14

T41

5

T14

11

auto[1]

887

1

T26

6

T41

15

T14

6

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

51

1

T26

1

T14

2

T18

1

auto[0]

from_1to0

auto[0]

auto[1]

45

1

T41

1

T65

1

T18

2

auto[0]

from_1to0

auto[1]

auto[0]

62

1

T26

1

T18

1

T21

2

auto[0]

from_1to0

auto[1]

auto[1]

45

1

T26

1

T41

1

T65

2

auto[0]

from_0to1

auto[0]

auto[0]

49

1

T18

1

T147

1

T94

3

auto[0]

from_0to1

auto[0]

auto[1]

49

1

T21

2

T288

2

T181

1

auto[0]

from_0to1

auto[1]

auto[0]

54

1

T26

2

T14

1

T21

2

auto[0]

from_0to1

auto[1]

auto[1]

40

1

T41

2

T65

2

T94

1

auto[1]

from_1to0

auto[0]

auto[0]

40

1

T26

3

T181

2

T210

1

auto[1]

from_1to0

auto[0]

auto[1]

56

1

T41

1

T21

1

T147

1

auto[1]

from_1to0

auto[1]

auto[0]

53

1

T41

1

T14

1

T21

2

auto[1]

from_1to0

auto[1]

auto[1]

50

1

T14

1

T65

1

T298

2

auto[1]

from_0to1

auto[0]

auto[0]

49

1

T26

1

T21

1

T94

1

auto[1]

from_0to1

auto[0]

auto[1]

60

1

T26

1

T41

1

T65

2

auto[1]

from_0to1

auto[1]

auto[0]

51

1

T26

2

T41

1

T14

2

auto[1]

from_0to1

auto[1]

auto[1]

48

1

T14

1

T18

1

T94

1