Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	156004	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

120556

1

T1

258

T4

24

T5

10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	143110	1			T1	401		T4	22		T5	8
values[0x0]	66085	1			T1	69		T4	13		T5	4
values[0x1]	67365	1			T1	54		T4	10		T5	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	126071	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

150489

1

T1

306

T4

29

T5

12

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1021	1			T2	1		T3	3		T6	2
valid_sources[0x01]	963	1			T26	7		T2	10		T3	1
valid_sources[0x02]	768	1			T2	9		T3	3		T6	2
valid_sources[0x03]	962	1			T24	1		T3	4		T6	1
valid_sources[0x04]	998	1			T2	2		T6	3		T9	2
valid_sources[0x05]	1055	1			T2	29		T3	3		T9	6
valid_sources[0x06]	917	1			T6	1		T9	2		T41	1
valid_sources[0x07]	2026	1			T7	1147		T47	2		T8	1
valid_sources[0x08]	1018	1			T3	2		T40	1		T9	3
valid_sources[0x09]	1014	1			T3	5		T9	4		T10	2
valid_sources[0x0a]	1020	1			T9	10		T41	2		T10	3
valid_sources[0x0b]	1055	1			T2	10		T3	1		T9	5
valid_sources[0x0c]	873	1			T2	9		T47	1		T9	7
valid_sources[0x0d]	893	1			T26	1		T3	3		T9	5
valid_sources[0x0e]	1032	1			T6	1		T9	9		T41	2
valid_sources[0x0f]	845	1			T2	4		T6	5		T10	6
valid_sources[0x10]	795	1			T2	8		T3	1		T8	2
valid_sources[0x11]	776	1			T2	1		T3	5		T6	2
valid_sources[0x12]	772	1			T3	2		T47	3		T9	8
valid_sources[0x13]	927	1			T3	6		T6	6		T9	7
valid_sources[0x14]	1167	1			T3	3		T9	4		T41	1
valid_sources[0x15]	1030	1			T3	1		T9	1		T41	2
valid_sources[0x16]	1144	1			T2	4		T3	2		T47	2
valid_sources[0x17]	895	1			T2	2		T3	2		T6	7
valid_sources[0x18]	1374	1			T3	2		T6	2		T9	4
valid_sources[0x19]	857	1			T2	8		T3	2		T10	2
valid_sources[0x1a]	925	1			T2	11		T6	2		T47	1
valid_sources[0x1b]	1070	1			T26	2		T2	7		T3	1
valid_sources[0x1c]	908	1			T24	1		T2	11		T3	1
valid_sources[0x1d]	1019	1			T26	7		T2	1		T3	2
valid_sources[0x1e]	904	1			T3	1		T6	1		T9	6
valid_sources[0x1f]	935	1			T2	30		T3	6		T9	5
valid_sources[0x20]	897	1			T2	5		T6	1		T41	2
valid_sources[0x21]	1155	1			T3	1		T6	7		T9	8
valid_sources[0x22]	1069	1			T24	2		T2	1		T6	5
valid_sources[0x23]	1017	1			T2	2		T47	1		T8	3
valid_sources[0x24]	990	1			T2	1		T6	2		T40	2
valid_sources[0x25]	903	1			T2	20		T9	3		T10	6
valid_sources[0x26]	812	1			T3	8		T9	1		T41	1
valid_sources[0x27]	956	1			T3	1		T9	3		T10	6
valid_sources[0x28]	866	1			T2	3		T3	1		T47	1
valid_sources[0x29]	943	1			T2	3		T3	1		T39	45
valid_sources[0x2a]	928	1			T9	2		T10	5		T17	4
valid_sources[0x2b]	778	1			T2	4		T9	3		T10	3
valid_sources[0x2c]	911	1			T26	2		T3	1		T9	2
valid_sources[0x2d]	1024	1			T24	1		T2	4		T6	8
valid_sources[0x2e]	1553	1			T24	2		T3	1		T9	1
valid_sources[0x2f]	989	1			T2	11		T6	2		T9	1
valid_sources[0x30]	1134	1			T2	10		T3	5		T9	5
valid_sources[0x31]	1468	1			T3	1		T9	3		T10	7
valid_sources[0x32]	1239	1			T2	12		T3	5		T6	4
valid_sources[0x33]	1170	1			T6	1		T9	5		T10	5
valid_sources[0x34]	1417	1			T2	9		T3	1		T47	2
valid_sources[0x35]	974	1			T2	6		T3	1		T9	7
valid_sources[0x36]	778	1			T2	7		T40	1		T9	4
valid_sources[0x37]	1232	1			T3	1		T6	6		T10	1
valid_sources[0x38]	1300	1			T3	5		T6	3		T9	8
valid_sources[0x39]	963	1			T2	4		T9	4		T41	1
valid_sources[0x3a]	1101	1			T2	3		T3	1		T9	2
valid_sources[0x3b]	1436	1			T2	12		T9	1		T41	1
valid_sources[0x3c]	833	1			T26	2		T3	1		T6	1
valid_sources[0x3d]	859	1			T2	1		T3	4		T6	6
valid_sources[0x3e]	894	1			T3	4		T6	5		T40	2
valid_sources[0x3f]	1202	1			T3	3		T6	3		T47	1
valid_sources[0x40]	934	1			T2	5		T3	5		T40	1
valid_sources[0x41]	1763	1			T26	9		T3	1		T47	2
valid_sources[0x42]	1243	1			T3	2		T40	1		T9	9
valid_sources[0x43]	1219	1			T3	2		T6	10		T9	1
valid_sources[0x44]	900	1			T2	9		T6	2		T47	1
valid_sources[0x45]	2207	1			T2	2		T9	7		T10	3
valid_sources[0x46]	747	1			T2	9		T3	2		T40	1
valid_sources[0x47]	1276	1			T2	13		T6	5		T10	3
valid_sources[0x48]	1117	1			T2	4		T3	1		T6	10
valid_sources[0x49]	1035	1			T3	2		T9	3		T10	3
valid_sources[0x4a]	1961	1			T3	1		T6	4		T40	1
valid_sources[0x4b]	844	1			T2	13		T10	2		T30	3
valid_sources[0x4c]	1078	1			T5	7		T2	4		T3	2
valid_sources[0x4d]	1051	1			T2	2		T3	2		T6	5
valid_sources[0x4e]	1051	1			T2	15		T3	2		T6	6
valid_sources[0x4f]	981	1			T26	3		T2	13		T3	3
valid_sources[0x50]	1065	1			T26	1		T3	5		T10	3
valid_sources[0x51]	875	1			T47	5		T9	4		T10	1
valid_sources[0x52]	1125	1			T3	4		T6	5		T9	6
valid_sources[0x53]	781	1			T3	1		T6	1		T40	1
valid_sources[0x54]	832	1			T3	7		T6	10		T9	4
valid_sources[0x55]	1200	1			T2	4		T6	5		T9	5
valid_sources[0x56]	911	1			T3	1		T6	1		T9	1
valid_sources[0x57]	897	1			T3	5		T6	8		T9	1
valid_sources[0x58]	797	1			T25	1		T2	5		T40	1
valid_sources[0x59]	865	1			T26	16		T2	2		T3	2
valid_sources[0x5a]	1037	1			T2	18		T3	1		T40	1
valid_sources[0x5b]	1168	1			T2	17		T3	2		T8	1
valid_sources[0x5c]	1161	1			T3	1		T9	7		T10	4
valid_sources[0x5d]	1371	1			T2	5		T47	4		T9	8
valid_sources[0x5e]	856	1			T2	3		T3	1		T6	2
valid_sources[0x5f]	1739	1			T24	1		T2	4		T3	1
valid_sources[0x60]	1680	1			T3	4		T6	2		T9	9
valid_sources[0x61]	1014	1			T6	1		T40	1		T9	4
valid_sources[0x62]	1053	1			T3	6		T9	4		T10	1
valid_sources[0x63]	821	1			T2	2		T3	1		T9	6
valid_sources[0x64]	1881	1			T2	26		T3	1		T6	1
valid_sources[0x65]	1019	1			T24	2		T3	4		T9	5
valid_sources[0x66]	960	1			T2	2		T3	3		T6	3
valid_sources[0x67]	1477	1			T1	524		T2	1		T3	2
valid_sources[0x68]	976	1			T26	9		T2	2		T3	1
valid_sources[0x69]	860	1			T2	20		T9	5		T41	1
valid_sources[0x6a]	949	1			T26	1		T2	29		T3	2
valid_sources[0x6b]	1597	1			T2	3		T9	6		T41	1
valid_sources[0x6c]	919	1			T26	1		T2	11		T3	5
valid_sources[0x6d]	934	1			T2	12		T3	4		T6	9
valid_sources[0x6e]	958	1			T2	2		T6	1		T9	2
valid_sources[0x6f]	881	1			T3	1		T9	5		T31	12
valid_sources[0x70]	1051	1			T2	5		T6	4		T9	1
valid_sources[0x71]	824	1			T3	6		T47	1		T9	5
valid_sources[0x72]	1193	1			T3	2		T9	1		T10	4
valid_sources[0x73]	1214	1			T3	2		T6	1		T40	1
valid_sources[0x74]	1081	1			T40	1		T9	4		T10	2
valid_sources[0x75]	857	1			T6	9		T9	2		T10	2
valid_sources[0x76]	825	1			T2	1		T3	2		T6	2
valid_sources[0x77]	1041	1			T6	1		T9	5		T41	1
valid_sources[0x78]	1632	1			T3	2		T8	1		T9	2
valid_sources[0x79]	832	1			T2	12		T47	1		T9	2
valid_sources[0x7a]	1163	1			T9	6		T10	2		T42	1
valid_sources[0x7b]	1222	1			T2	9		T3	1		T40	1
valid_sources[0x7c]	1081	1			T9	3		T41	1		T10	7
valid_sources[0x7d]	966	1			T2	8		T9	4		T41	1
valid_sources[0x7e]	2061	1			T3	3		T9	2		T10	3
valid_sources[0x7f]	747	1			T2	3		T3	1		T6	1
valid_sources[0x80]	940	1			T2	10		T3	1		T6	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

64983

1

T1

201

T4

13

T5

5

values[0x0]

all_enables

biggest_size

32554

1

T1

34

T4

8

T5

3

values[0x1]

all_enables

biggest_size

23019

1

T1

23

T4

3

T5

2