Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.93	95.65	95.24		100.00	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.93	95.65	95.24		100.00	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.84	95.65	95.24		100.00	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.84	95.65	95.24		100.00	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T5,T48,T53

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T5,T48,T53

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T5,T48,T53

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T48,T53
1	0	Covered	T1,T4,T5
1	1	Covered	T5,T48,T53

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T48,T53
0	1	Not Covered
1	0	Covered	T82

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T48,T53
0	1	Covered	T5,T48,T53
1	0	Covered	T83

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T48,T53
1	-	Covered	T5,T48,T53

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T48,T53
DetectSt	168	Covered	T5,T48,T53
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T5,T48,T53

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T48,T53
DebounceSt->IdleSt	163	Covered	T5,T21,T94
DetectSt->IdleSt	186	Covered	T82
DetectSt->StableSt	191	Covered	T5,T48,T53
IdleSt->DebounceSt	148	Covered	T5,T48,T53
StableSt->IdleSt	206	Covered	T5,T48,T53

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T48,T53
0	1	Covered	T5,T48,T53
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T48,T53
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T48,T53
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T48,T53
DebounceSt	-	0	1	0	-	-	-	Covered	T5,T21,T94
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T48,T53
DetectSt	-	-	-	-	1	-	-	Covered	T82
DetectSt	-	-	-	-	0	1	-	Covered	T5,T48,T53
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T5,T48,T53
StableSt	-	-	-	-	-	-	0	Covered	T5,T48,T53
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7138329	236	0	0
CntIncr_A	7138329	164254	0	0
CntNoWrap_A	7138329	6515395	0	0
DetectStDropOut_A	7138329	0	0	0
DetectedOut_A	7138329	767	0	0
DetectedPulseOut_A	7138329	107	0	0
DisabledIdleSt_A	7138329	6345544	0	0
DisabledNoDetection_A	7138329	6347863	0	0
EnterDebounceSt_A	7138329	131	0	0
EnterDetectSt_A	7138329	108	0	0
EnterStableSt_A	7138329	107	0	0
PulseIsPulse_A	7138329	107	0	0
StayInStableSt	7138329	660	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7138329	6847	0	0
gen_low_level_sva.LowLevelEvent_A	7138329	6518002	0	0
gen_not_sticky_sva.StableStDropOut_A	7138329	106	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	236	0	0
T2	15963	0	0	0
T3	21356	0	0	0
T5	693	3	0	0
T6	12993	0	0	0
T21	0	5	0	0
T24	449	0	0	0
T25	403	0	0	0
T26	505	0	0	0
T27	406	0	0	0
T28	20119	0	0	0
T29	405	0	0	0
T48	0	4	0	0
T53	0	2	0	0
T54	0	4	0	0
T55	0	2	0	0
T56	0	2	0	0
T57	0	2	0	0
T94	0	1	0	0
T95	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	164254	0	0
T2	15963	0	0	0
T3	21356	0	0	0
T5	693	121	0	0
T6	12993	0	0	0
T21	0	86	0	0
T24	449	0	0	0
T25	403	0	0	0
T26	505	0	0	0
T27	406	0	0	0
T28	20119	0	0	0
T29	405	0	0	0
T48	0	168	0	0
T53	0	50	0	0
T54	0	138	0	0
T55	0	80	0	0
T56	0	56	0	0
T57	0	24	0	0
T94	0	33	0	0
T95	0	97	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6515395	0	0
T1	20092	19645	0	0
T2	15963	15539	0	0
T4	496	95	0	0
T5	693	289	0	0
T24	449	48	0	0
T25	403	2	0	0
T26	505	104	0	0
T27	406	5	0	0
T28	20119	19678	0	0
T29	405	4	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	767	0	0
T2	15963	0	0	0
T3	21356	0	0	0
T5	693	12	0	0
T6	12993	0	0	0
T21	0	9	0	0
T24	449	0	0	0
T25	403	0	0	0
T26	505	0	0	0
T27	406	0	0	0
T28	20119	0	0	0
T29	405	0	0	0
T37	0	30	0	0
T48	0	14	0	0
T53	0	4	0	0
T54	0	14	0	0
T55	0	11	0	0
T56	0	3	0	0
T57	0	9	0	0
T95	0	9	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	107	0	0
T2	15963	0	0	0
T3	21356	0	0	0
T5	693	1	0	0
T6	12993	0	0	0
T21	0	2	0	0
T24	449	0	0	0
T25	403	0	0	0
T26	505	0	0	0
T27	406	0	0	0
T28	20119	0	0	0
T29	405	0	0	0
T37	0	3	0	0
T48	0	2	0	0
T53	0	1	0	0
T54	0	2	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T95	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6345544	0	0
T1	20092	19645	0	0
T2	15963	15539	0	0
T4	496	95	0	0
T5	693	102	0	0
T24	449	48	0	0
T25	403	2	0	0
T26	505	104	0	0
T27	406	5	0	0
T28	20119	19678	0	0
T29	405	4	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6347863	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	102	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	131	0	0
T2	15963	0	0	0
T3	21356	0	0	0
T5	693	2	0	0
T6	12993	0	0	0
T21	0	3	0	0
T24	449	0	0	0
T25	403	0	0	0
T26	505	0	0	0
T27	406	0	0	0
T28	20119	0	0	0
T29	405	0	0	0
T48	0	2	0	0
T53	0	1	0	0
T54	0	2	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T94	0	1	0	0
T95	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	108	0	0
T2	15963	0	0	0
T3	21356	0	0	0
T5	693	1	0	0
T6	12993	0	0	0
T21	0	2	0	0
T24	449	0	0	0
T25	403	0	0	0
T26	505	0	0	0
T27	406	0	0	0
T28	20119	0	0	0
T29	405	0	0	0
T37	0	3	0	0
T48	0	2	0	0
T53	0	1	0	0
T54	0	2	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T95	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	107	0	0
T2	15963	0	0	0
T3	21356	0	0	0
T5	693	1	0	0
T6	12993	0	0	0
T21	0	2	0	0
T24	449	0	0	0
T25	403	0	0	0
T26	505	0	0	0
T27	406	0	0	0
T28	20119	0	0	0
T29	405	0	0	0
T37	0	3	0	0
T48	0	2	0	0
T53	0	1	0	0
T54	0	2	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T95	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	107	0	0
T2	15963	0	0	0
T3	21356	0	0	0
T5	693	1	0	0
T6	12993	0	0	0
T21	0	2	0	0
T24	449	0	0	0
T25	403	0	0	0
T26	505	0	0	0
T27	406	0	0	0
T28	20119	0	0	0
T29	405	0	0	0
T37	0	3	0	0
T48	0	2	0	0
T53	0	1	0	0
T54	0	2	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T95	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	660	0	0
T2	15963	0	0	0
T3	21356	0	0	0
T5	693	11	0	0
T6	12993	0	0	0
T21	0	7	0	0
T24	449	0	0	0
T25	403	0	0	0
T26	505	0	0	0
T27	406	0	0	0
T28	20119	0	0	0
T29	405	0	0	0
T37	0	27	0	0
T48	0	12	0	0
T53	0	3	0	0
T54	0	12	0	0
T55	0	10	0	0
T56	0	2	0	0
T57	0	8	0	0
T95	0	8	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6847	0	0
T1	20092	12	0	0
T2	15963	33	0	0
T3	0	11	0	0
T4	496	8	0	0
T5	693	3	0	0
T6	0	9	0	0
T7	0	28	0	0
T24	449	2	0	0
T25	403	0	0	0
T26	505	5	0	0
T27	406	0	0	0
T28	20119	11	0	0
T29	405	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6518002	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	106	0	0
T2	15963	0	0	0
T3	21356	0	0	0
T5	693	1	0	0
T6	12993	0	0	0
T21	0	2	0	0
T24	449	0	0	0
T25	403	0	0	0
T26	505	0	0	0
T27	406	0	0	0
T28	20119	0	0	0
T29	405	0	0	0
T37	0	3	0	0
T48	0	2	0	0
T53	0	1	0	0
T54	0	2	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T95	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T8,T13,T14

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T8,T13,T14

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T8,T14,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T13,T14
1	0	Covered	T1,T4,T5
1	1	Covered	T8,T13,T14

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T34,T22
0	1	Covered	T8,T92,T93
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T34,T22
0	1	Unreachable
1	0	Covered	T14,T34,T22

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T13,T14
DetectSt	168	Covered	T8,T14,T34
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T14,T34,T22

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T14,T34
DebounceSt->IdleSt	163	Covered	T8,T13,T17
DetectSt->IdleSt	186	Covered	T8,T92,T93
DetectSt->StableSt	191	Covered	T14,T34,T22
IdleSt->DebounceSt	148	Covered	T8,T13,T14
StableSt->IdleSt	206	Covered	T14,T34,T22

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T13,T14
0	1	Covered	T8,T13,T14
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T14,T34
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T13,T14
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T82,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T14,T34
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T13,T17
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T13,T14
DetectSt	-	-	-	-	1	-	-	Covered	T8,T92,T93
DetectSt	-	-	-	-	0	1	-	Covered	T14,T34,T22
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T14,T34,T22
StableSt	-	-	-	-	-	-	0	Covered	T14,T34,T22
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7138329	173	0	0
CntIncr_A	7138329	262941	0	0
CntNoWrap_A	7138329	6515458	0	0
DetectStDropOut_A	7138329	9	0	0
DetectedOut_A	7138329	663765	0	0
DetectedPulseOut_A	7138329	40	0	0
DisabledIdleSt_A	7138329	5337545	0	0
DisabledNoDetection_A	7138329	5339913	0	0
EnterDebounceSt_A	7138329	125	0	0
EnterDetectSt_A	7138329	49	0	0
EnterStableSt_A	7138329	40	0	0
PulseIsPulse_A	7138329	40	0	0
StayInStableSt	7138329	663725	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7138329	6847	0	0
gen_low_level_sva.LowLevelEvent_A	7138329	6518002	0	0
gen_sticky_sva.StableStDropOut_A	7138329	143046	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	173	0	0
T8	1009	5	0	0
T9	18082	0	0	0
T10	9156	0	0	0
T11	504	0	0	0
T12	29286	0	0	0
T13	1437	2	0	0
T14	0	2	0	0
T17	0	2	0	0
T22	0	2	0	0
T34	0	2	0	0
T35	0	4	0	0
T36	0	2	0	0
T37	0	6	0	0
T38	0	2	0	0
T39	492	0	0	0
T40	495	0	0	0
T41	502	0	0	0
T42	453	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	262941	0	0
T8	1009	249	0	0
T9	18082	0	0	0
T10	9156	0	0	0
T11	504	0	0	0
T12	29286	0	0	0
T13	1437	40	0	0
T14	0	42	0	0
T17	0	26	0	0
T22	0	80	0	0
T34	0	16	0	0
T35	0	260	0	0
T36	0	52	0	0
T37	0	47286	0	0
T38	0	40	0	0
T39	492	0	0	0
T40	495	0	0	0
T41	502	0	0	0
T42	453	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6515458	0	0
T1	20092	19645	0	0
T2	15963	15539	0	0
T4	496	95	0	0
T5	693	292	0	0
T24	449	48	0	0
T25	403	2	0	0
T26	505	104	0	0
T27	406	5	0	0
T28	20119	19678	0	0
T29	405	4	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	9	0	0
T8	1009	2	0	0
T9	18082	0	0	0
T10	9156	0	0	0
T11	504	0	0	0
T12	29286	0	0	0
T13	1437	0	0	0
T39	492	0	0	0
T40	495	0	0	0
T41	502	0	0	0
T42	453	0	0	0
T92	0	1	0	0
T93	0	1	0	0
T117	0	1	0	0
T118	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	663765	0	0
T14	16893	133	0	0
T15	654	0	0	0
T16	23347	0	0	0
T17	24696	0	0	0
T22	0	560	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T34	0	81	0	0
T36	0	231	0	0
T37	0	228831	0	0
T38	0	23	0	0
T58	1012	0	0	0
T65	504	0	0	0
T87	0	48	0	0
T111	0	185	0	0
T114	0	68	0	0
T116	0	143	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	40	0	0
T14	16893	1	0	0
T15	654	0	0	0
T16	23347	0	0	0
T17	24696	0	0	0
T22	0	1	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T58	1012	0	0	0
T65	504	0	0	0
T87	0	1	0	0
T111	0	1	0	0
T114	0	1	0	0
T116	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	5337545	0	0
T1	20092	19645	0	0
T2	15963	15539	0	0
T4	496	95	0	0
T5	693	292	0	0
T24	449	48	0	0
T25	403	2	0	0
T26	505	104	0	0
T27	406	5	0	0
T28	20119	19678	0	0
T29	405	4	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	5339913	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	125	0	0
T8	1009	3	0	0
T9	18082	0	0	0
T10	9156	0	0	0
T11	504	0	0	0
T12	29286	0	0	0
T13	1437	2	0	0
T14	0	1	0	0
T17	0	2	0	0
T22	0	1	0	0
T34	0	1	0	0
T35	0	4	0	0
T36	0	1	0	0
T37	0	4	0	0
T38	0	1	0	0
T39	492	0	0	0
T40	495	0	0	0
T41	502	0	0	0
T42	453	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	49	0	0
T8	1009	2	0	0
T9	18082	0	0	0
T10	9156	0	0	0
T11	504	0	0	0
T12	29286	0	0	0
T13	1437	0	0	0
T14	0	1	0	0
T22	0	1	0	0
T34	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T39	492	0	0	0
T40	495	0	0	0
T41	502	0	0	0
T42	453	0	0	0
T87	0	1	0	0
T111	0	1	0	0
T114	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	40	0	0
T14	16893	1	0	0
T15	654	0	0	0
T16	23347	0	0	0
T17	24696	0	0	0
T22	0	1	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T58	1012	0	0	0
T65	504	0	0	0
T87	0	1	0	0
T111	0	1	0	0
T114	0	1	0	0
T116	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	40	0	0
T14	16893	1	0	0
T15	654	0	0	0
T16	23347	0	0	0
T17	24696	0	0	0
T22	0	1	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T58	1012	0	0	0
T65	504	0	0	0
T87	0	1	0	0
T111	0	1	0	0
T114	0	1	0	0
T116	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	663725	0	0
T14	16893	132	0	0
T15	654	0	0	0
T16	23347	0	0	0
T17	24696	0	0	0
T22	0	559	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T34	0	80	0	0
T36	0	230	0	0
T37	0	228829	0	0
T38	0	22	0	0
T58	1012	0	0	0
T65	504	0	0	0
T87	0	47	0	0
T111	0	184	0	0
T114	0	67	0	0
T116	0	142	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6847	0	0
T1	20092	12	0	0
T2	15963	33	0	0
T3	0	11	0	0
T4	496	8	0	0
T5	693	3	0	0
T6	0	9	0	0
T7	0	28	0	0
T24	449	2	0	0
T25	403	0	0	0
T26	505	5	0	0
T27	406	0	0	0
T28	20119	11	0	0
T29	405	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6518002	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	143046	0	0
T14	16893	432	0	0
T15	654	0	0	0
T16	23347	0	0	0
T17	24696	0	0	0
T22	0	73	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T34	0	141	0	0
T36	0	195	0	0
T37	0	186	0	0
T38	0	51	0	0
T58	1012	0	0	0
T65	504	0	0	0
T87	0	24	0	0
T111	0	73	0	0
T114	0	35	0	0
T116	0	231	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T24,T26

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T4,T24,T26
1	1	Covered	T4,T24,T26

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T8,T13,T14

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T8,T13,T14

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T14,T17,T22

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T13,T14
1	0	Covered	T4,T24,T26
1	1	Covered	T8,T13,T14

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T17,T22
0	1	Covered	T89,T90,T91
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T17,T22
0	1	Unreachable
1	0	Covered	T14,T17,T22

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T13,T14
DetectSt	168	Covered	T14,T17,T22
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T14,T17,T22

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T14,T17,T22
DebounceSt->IdleSt	163	Covered	T8,T13,T34
DetectSt->IdleSt	186	Covered	T89,T90,T91
DetectSt->StableSt	191	Covered	T14,T17,T22
IdleSt->DebounceSt	148	Covered	T8,T13,T14
StableSt->IdleSt	206	Covered	T14,T17,T22

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T13,T14
0	1	Covered	T8,T13,T14
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T17,T22
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T13,T14
IdleSt	0	-	-	-	-	-	-	Covered	T4,T24,T26
DebounceSt	-	1	-	-	-	-	-	Covered	T82,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T17,T22
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T13,T34
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T13,T14
DetectSt	-	-	-	-	1	-	-	Covered	T89,T90,T91
DetectSt	-	-	-	-	0	1	-	Covered	T14,T17,T22
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T14,T17,T22
StableSt	-	-	-	-	-	-	0	Covered	T14,T17,T22
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7138329	164	0	0
CntIncr_A	7138329	5652	0	0
CntNoWrap_A	7138329	6515467	0	0
DetectStDropOut_A	7138329	11	0	0
DetectedOut_A	7138329	10132	0	0
DetectedPulseOut_A	7138329	48	0	0
DisabledIdleSt_A	7138329	5337545	0	0
DisabledNoDetection_A	7138329	5339913	0	0
EnterDebounceSt_A	7138329	106	0	0
EnterDetectSt_A	7138329	59	0	0
EnterStableSt_A	7138329	48	0	0
PulseIsPulse_A	7138329	48	0	0
StayInStableSt	7138329	10084	0	0
gen_high_level_sva.HighLevelEvent_A	7138329	6518002	0	0
gen_sticky_sva.StableStDropOut_A	7138329	936025	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	164	0	0
T8	1009	3	0	0
T9	18082	0	0	0
T10	9156	0	0	0
T11	504	0	0	0
T12	29286	0	0	0
T13	1437	2	0	0
T14	0	2	0	0
T17	0	2	0	0
T22	0	2	0	0
T34	0	4	0	0
T35	0	2	0	0
T36	0	5	0	0
T37	0	6	0	0
T38	0	2	0	0
T39	492	0	0	0
T40	495	0	0	0
T41	502	0	0	0
T42	453	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	5652	0	0
T8	1009	108	0	0
T9	18082	0	0	0
T10	9156	0	0	0
T11	504	0	0	0
T12	29286	0	0	0
T13	1437	150	0	0
T14	0	95	0	0
T17	0	63	0	0
T22	0	50	0	0
T34	0	76	0	0
T35	0	43	0	0
T36	0	125	0	0
T37	0	104	0	0
T38	0	37	0	0
T39	492	0	0	0
T40	495	0	0	0
T41	502	0	0	0
T42	453	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6515467	0	0
T1	20092	19645	0	0
T2	15963	15539	0	0
T4	496	95	0	0
T5	693	292	0	0
T24	449	48	0	0
T25	403	2	0	0
T26	505	104	0	0
T27	406	5	0	0
T28	20119	19678	0	0
T29	405	4	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	11	0	0
T75	0	2	0	0
T89	1388	2	0	0
T90	0	1	0	0
T91	0	2	0	0
T119	0	2	0	0
T120	0	2	0	0
T121	451	0	0	0
T122	406	0	0	0
T123	754	0	0	0
T124	7073	0	0	0
T125	503	0	0	0
T126	10322	0	0	0
T127	760	0	0	0
T128	21575	0	0	0
T129	424	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	10132	0	0
T14	16893	416	0	0
T15	654	0	0	0
T16	23347	0	0	0
T17	24696	134	0	0
T22	0	327	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T35	0	250	0	0
T37	0	478	0	0
T38	0	5	0	0
T58	1012	0	0	0
T65	504	0	0	0
T87	0	25	0	0
T111	0	106	0	0
T113	0	536	0	0
T115	0	433	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	48	0	0
T14	16893	1	0	0
T15	654	0	0	0
T16	23347	0	0	0
T17	24696	1	0	0
T22	0	1	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T35	0	1	0	0
T37	0	3	0	0
T38	0	1	0	0
T58	1012	0	0	0
T65	504	0	0	0
T87	0	1	0	0
T111	0	1	0	0
T113	0	1	0	0
T115	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	5337545	0	0
T1	20092	19645	0	0
T2	15963	15539	0	0
T4	496	95	0	0
T5	693	292	0	0
T24	449	48	0	0
T25	403	2	0	0
T26	505	104	0	0
T27	406	5	0	0
T28	20119	19678	0	0
T29	405	4	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	5339913	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	106	0	0
T8	1009	3	0	0
T9	18082	0	0	0
T10	9156	0	0	0
T11	504	0	0	0
T12	29286	0	0	0
T13	1437	2	0	0
T14	0	1	0	0
T17	0	1	0	0
T22	0	1	0	0
T34	0	4	0	0
T35	0	1	0	0
T36	0	5	0	0
T37	0	3	0	0
T38	0	1	0	0
T39	492	0	0	0
T40	495	0	0	0
T41	502	0	0	0
T42	453	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	59	0	0
T14	16893	1	0	0
T15	654	0	0	0
T16	23347	0	0	0
T17	24696	1	0	0
T22	0	1	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T35	0	1	0	0
T37	0	3	0	0
T38	0	1	0	0
T58	1012	0	0	0
T65	504	0	0	0
T87	0	1	0	0
T111	0	1	0	0
T113	0	1	0	0
T115	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	48	0	0
T14	16893	1	0	0
T15	654	0	0	0
T16	23347	0	0	0
T17	24696	1	0	0
T22	0	1	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T35	0	1	0	0
T37	0	3	0	0
T38	0	1	0	0
T58	1012	0	0	0
T65	504	0	0	0
T87	0	1	0	0
T111	0	1	0	0
T113	0	1	0	0
T115	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	48	0	0
T14	16893	1	0	0
T15	654	0	0	0
T16	23347	0	0	0
T17	24696	1	0	0
T22	0	1	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T35	0	1	0	0
T37	0	3	0	0
T38	0	1	0	0
T58	1012	0	0	0
T65	504	0	0	0
T87	0	1	0	0
T111	0	1	0	0
T113	0	1	0	0
T115	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	10084	0	0
T14	16893	415	0	0
T15	654	0	0	0
T16	23347	0	0	0
T17	24696	133	0	0
T22	0	326	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T35	0	249	0	0
T37	0	475	0	0
T38	0	4	0	0
T58	1012	0	0	0
T65	504	0	0	0
T87	0	24	0	0
T111	0	105	0	0
T113	0	535	0	0
T115	0	432	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6518002	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	936025	0	0
T14	16893	78	0	0
T15	654	0	0	0
T16	23347	0	0	0
T17	24696	38	0	0
T22	0	341	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T35	0	256	0	0
T37	0	275782	0	0
T38	0	68	0	0
T58	1012	0	0	0
T65	504	0	0	0
T87	0	42	0	0
T111	0	194	0	0
T113	0	286	0	0
T115	0	175	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T24

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T8,T13,T14

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T8,T13,T14

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T8,T13,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T13,T14
1	0	Covered	T1,T4,T24
1	1	Covered	T8,T13,T14

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T13,T34
0	1	Covered	T36,T87,T88
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T13,T34
0	1	Unreachable
1	0	Covered	T8,T13,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T13,T14
DetectSt	168	Covered	T8,T13,T34
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T8,T13,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T13,T34
DebounceSt->IdleSt	163	Covered	T14,T17,T35
DetectSt->IdleSt	186	Covered	T36,T87,T88
DetectSt->StableSt	191	Covered	T8,T13,T34
IdleSt->DebounceSt	148	Covered	T8,T13,T14
StableSt->IdleSt	206	Covered	T8,T13,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T13,T14
0	1	Covered	T8,T13,T14
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T13,T34
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T13,T14
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T24
DebounceSt	-	1	-	-	-	-	-	Covered	T82,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T13,T34
DebounceSt	-	0	1	0	-	-	-	Covered	T14,T17,T35
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T13,T14
DetectSt	-	-	-	-	1	-	-	Covered	T36,T87,T88
DetectSt	-	-	-	-	0	1	-	Covered	T8,T13,T34
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T13,T34
StableSt	-	-	-	-	-	-	0	Covered	T8,T13,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7138329	170	0	0
CntIncr_A	7138329	231047	0	0
CntNoWrap_A	7138329	6515461	0	0
DetectStDropOut_A	7138329	10	0	0
DetectedOut_A	7138329	93575	0	0
DetectedPulseOut_A	7138329	49	0	0
DisabledIdleSt_A	7138329	5337545	0	0
DisabledNoDetection_A	7138329	5339913	0	0
EnterDebounceSt_A	7138329	112	0	0
EnterDetectSt_A	7138329	59	0	0
EnterStableSt_A	7138329	49	0	0
PulseIsPulse_A	7138329	49	0	0
StayInStableSt	7138329	93526	0	0
gen_high_event_sva.HighLevelEvent_A	7138329	6518002	0	0
gen_high_level_sva.HighLevelEvent_A	7138329	6518002	0	0
gen_sticky_sva.StableStDropOut_A	7138329	847873	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	170	0	0
T8	1009	2	0	0
T9	18082	0	0	0
T10	9156	0	0	0
T11	504	0	0	0
T12	29286	0	0	0
T13	1437	2	0	0
T14	0	3	0	0
T17	0	2	0	0
T22	0	2	0	0
T34	0	2	0	0
T35	0	4	0	0
T36	0	8	0	0
T37	0	6	0	0
T38	0	2	0	0
T39	492	0	0	0
T40	495	0	0	0
T41	502	0	0	0
T42	453	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	231047	0	0
T8	1009	16	0	0
T9	18082	0	0	0
T10	9156	0	0	0
T11	504	0	0	0
T12	29286	0	0	0
T13	1437	89	0	0
T14	0	111	0	0
T17	0	122	0	0
T22	0	32	0	0
T34	0	34	0	0
T35	0	116	0	0
T36	0	188	0	0
T37	0	195	0	0
T38	0	52	0	0
T39	492	0	0	0
T40	495	0	0	0
T41	502	0	0	0
T42	453	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6515461	0	0
T1	20092	19645	0	0
T2	15963	15539	0	0
T4	496	95	0	0
T5	693	292	0	0
T24	449	48	0	0
T25	403	2	0	0
T26	505	104	0	0
T27	406	5	0	0
T28	20119	19678	0	0
T29	405	4	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	10	0	0
T36	1884	3	0	0
T37	292750	0	0	0
T78	8543	0	0	0
T87	0	1	0	0
T88	0	2	0	0
T100	40328	0	0	0
T101	5070	0	0	0
T102	20255	0	0	0
T117	0	1	0	0
T118	0	2	0	0
T130	0	1	0	0
T131	17492	0	0	0
T132	916	0	0	0
T133	522	0	0	0
T134	522	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	93575	0	0
T8	1009	76	0	0
T9	18082	0	0	0
T10	9156	0	0	0
T11	504	0	0	0
T12	29286	0	0	0
T13	1437	258	0	0
T22	0	206	0	0
T34	0	137	0	0
T36	0	49	0	0
T37	0	919	0	0
T38	0	34	0	0
T39	492	0	0	0
T40	495	0	0	0
T41	502	0	0	0
T42	453	0	0	0
T112	0	23	0	0
T114	0	6	0	0
T116	0	301	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	49	0	0
T8	1009	1	0	0
T9	18082	0	0	0
T10	9156	0	0	0
T11	504	0	0	0
T12	29286	0	0	0
T13	1437	1	0	0
T22	0	1	0	0
T34	0	1	0	0
T36	0	1	0	0
T37	0	3	0	0
T38	0	1	0	0
T39	492	0	0	0
T40	495	0	0	0
T41	502	0	0	0
T42	453	0	0	0
T112	0	1	0	0
T114	0	1	0	0
T116	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	5337545	0	0
T1	20092	19645	0	0
T2	15963	15539	0	0
T4	496	95	0	0
T5	693	292	0	0
T24	449	48	0	0
T25	403	2	0	0
T26	505	104	0	0
T27	406	5	0	0
T28	20119	19678	0	0
T29	405	4	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	5339913	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	112	0	0
T8	1009	1	0	0
T9	18082	0	0	0
T10	9156	0	0	0
T11	504	0	0	0
T12	29286	0	0	0
T13	1437	1	0	0
T14	0	3	0	0
T17	0	2	0	0
T22	0	1	0	0
T34	0	1	0	0
T35	0	4	0	0
T36	0	4	0	0
T37	0	3	0	0
T38	0	1	0	0
T39	492	0	0	0
T40	495	0	0	0
T41	502	0	0	0
T42	453	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	59	0	0
T8	1009	1	0	0
T9	18082	0	0	0
T10	9156	0	0	0
T11	504	0	0	0
T12	29286	0	0	0
T13	1437	1	0	0
T22	0	1	0	0
T34	0	1	0	0
T36	0	4	0	0
T37	0	3	0	0
T38	0	1	0	0
T39	492	0	0	0
T40	495	0	0	0
T41	502	0	0	0
T42	453	0	0	0
T87	0	1	0	0
T112	0	1	0	0
T114	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	49	0	0
T8	1009	1	0	0
T9	18082	0	0	0
T10	9156	0	0	0
T11	504	0	0	0
T12	29286	0	0	0
T13	1437	1	0	0
T22	0	1	0	0
T34	0	1	0	0
T36	0	1	0	0
T37	0	3	0	0
T38	0	1	0	0
T39	492	0	0	0
T40	495	0	0	0
T41	502	0	0	0
T42	453	0	0	0
T112	0	1	0	0
T114	0	1	0	0
T116	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	49	0	0
T8	1009	1	0	0
T9	18082	0	0	0
T10	9156	0	0	0
T11	504	0	0	0
T12	29286	0	0	0
T13	1437	1	0	0
T22	0	1	0	0
T34	0	1	0	0
T36	0	1	0	0
T37	0	3	0	0
T38	0	1	0	0
T39	492	0	0	0
T40	495	0	0	0
T41	502	0	0	0
T42	453	0	0	0
T112	0	1	0	0
T114	0	1	0	0
T116	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	93526	0	0
T8	1009	75	0	0
T9	18082	0	0	0
T10	9156	0	0	0
T11	504	0	0	0
T12	29286	0	0	0
T13	1437	257	0	0
T22	0	205	0	0
T34	0	136	0	0
T36	0	48	0	0
T37	0	916	0	0
T38	0	33	0	0
T39	492	0	0	0
T40	495	0	0	0
T41	502	0	0	0
T42	453	0	0	0
T112	0	22	0	0
T114	0	5	0	0
T116	0	300	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6518002	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6518002	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	847873	0	0
T8	1009	240	0	0
T9	18082	0	0	0
T10	9156	0	0	0
T11	504	0	0	0
T12	29286	0	0	0
T13	1437	153	0	0
T22	0	487	0	0
T34	0	72	0	0
T36	0	109	0	0
T37	0	275298	0	0
T38	0	30	0	0
T39	492	0	0	0
T40	495	0	0	0
T41	502	0	0	0
T42	453	0	0	0
T112	0	37	0	0
T114	0	111	0	0
T116	0	40	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T14,T20,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T14,T20,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T14,T20,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T18,T20
1	0	Covered	T1,T4,T5
1	1	Covered	T14,T20,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T20,T21
0	1	Not Covered
1	0	Covered	T82

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T20,T21
0	1	Covered	T21,T50,T115
1	0	Covered	T83

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T20,T21
1	-	Covered	T21,T50,T115

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T14,T20,T21
DetectSt	168	Covered	T14,T20,T21
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T14,T20,T21

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T14,T20,T21
DebounceSt->IdleSt	163	Covered	T135,T136
DetectSt->IdleSt	186	Covered	T82
DetectSt->StableSt	191	Covered	T14,T20,T21
IdleSt->DebounceSt	148	Covered	T14,T20,T21
StableSt->IdleSt	206	Covered	T14,T21,T50

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T20,T21
0	1	Covered	T14,T20,T21
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T20,T21
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T20,T21
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T20,T21
DebounceSt	-	0	1	0	-	-	-	Covered	T135
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T20,T21
DetectSt	-	-	-	-	1	-	-	Covered	T82
DetectSt	-	-	-	-	0	1	-	Covered	T14,T20,T21
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T21,T50,T115
StableSt	-	-	-	-	-	-	0	Covered	T14,T20,T21
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7138329	77	0	0
CntIncr_A	7138329	49299	0	0
CntNoWrap_A	7138329	6515554	0	0
DetectStDropOut_A	7138329	0	0	0
DetectedOut_A	7138329	100846	0	0
DetectedPulseOut_A	7138329	37	0	0
DisabledIdleSt_A	7138329	6094768	0	0
DisabledNoDetection_A	7138329	6097099	0	0
EnterDebounceSt_A	7138329	40	0	0
EnterDetectSt_A	7138329	38	0	0
EnterStableSt_A	7138329	37	0	0
PulseIsPulse_A	7138329	37	0	0
StayInStableSt	7138329	100789	0	0
gen_high_level_sva.HighLevelEvent_A	7138329	6518002	0	0
gen_not_sticky_sva.StableStDropOut_A	7138329	16	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	77	0	0
T14	16893	2	0	0
T15	654	0	0	0
T16	23347	0	0	0
T17	24696	0	0	0
T20	0	2	0	0
T21	0	2	0	0
T23	0	2	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T50	0	4	0	0
T52	0	2	0	0
T58	1012	0	0	0
T65	504	0	0	0
T82	0	2	0	0
T115	0	2	0	0
T135	0	3	0	0
T137	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	49299	0	0
T14	16893	15	0	0
T15	654	0	0	0
T16	23347	0	0	0
T17	24696	0	0	0
T20	0	46919	0	0
T21	0	78	0	0
T23	0	74	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T50	0	94	0	0
T52	0	38	0	0
T58	1012	0	0	0
T65	504	0	0	0
T82	0	44	0	0
T115	0	39	0	0
T135	0	50	0	0
T137	0	67	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6515554	0	0
T1	20092	19645	0	0
T2	15963	15539	0	0
T4	496	95	0	0
T5	693	292	0	0
T24	449	48	0	0
T25	403	2	0	0
T26	505	104	0	0
T27	406	5	0	0
T28	20119	19678	0	0
T29	405	4	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	100846	0	0
T14	16893	40	0	0
T15	654	0	0	0
T16	23347	0	0	0
T17	24696	0	0	0
T20	0	98128	0	0
T21	0	44	0	0
T23	0	230	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T50	0	104	0	0
T52	0	37	0	0
T58	1012	0	0	0
T65	504	0	0	0
T115	0	41	0	0
T135	0	38	0	0
T137	0	37	0	0
T138	0	79	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	37	0	0
T14	16893	1	0	0
T15	654	0	0	0
T16	23347	0	0	0
T17	24696	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T23	0	1	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T50	0	2	0	0
T52	0	1	0	0
T58	1012	0	0	0
T65	504	0	0	0
T115	0	1	0	0
T135	0	1	0	0
T137	0	1	0	0
T138	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6094768	0	0
T1	20092	19645	0	0
T2	15963	15539	0	0
T4	496	95	0	0
T5	693	292	0	0
T24	449	48	0	0
T25	403	2	0	0
T26	505	104	0	0
T27	406	5	0	0
T28	20119	19678	0	0
T29	405	4	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6097099	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	40	0	0
T14	16893	1	0	0
T15	654	0	0	0
T16	23347	0	0	0
T17	24696	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T23	0	1	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T50	0	2	0	0
T52	0	1	0	0
T58	1012	0	0	0
T65	504	0	0	0
T82	0	1	0	0
T115	0	1	0	0
T135	0	2	0	0
T137	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	38	0	0
T14	16893	1	0	0
T15	654	0	0	0
T16	23347	0	0	0
T17	24696	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T23	0	1	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T50	0	2	0	0
T52	0	1	0	0
T58	1012	0	0	0
T65	504	0	0	0
T82	0	1	0	0
T115	0	1	0	0
T135	0	1	0	0
T137	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	37	0	0
T14	16893	1	0	0
T15	654	0	0	0
T16	23347	0	0	0
T17	24696	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T23	0	1	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T50	0	2	0	0
T52	0	1	0	0
T58	1012	0	0	0
T65	504	0	0	0
T115	0	1	0	0
T135	0	1	0	0
T137	0	1	0	0
T138	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	37	0	0
T14	16893	1	0	0
T15	654	0	0	0
T16	23347	0	0	0
T17	24696	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T23	0	1	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T50	0	2	0	0
T52	0	1	0	0
T58	1012	0	0	0
T65	504	0	0	0
T115	0	1	0	0
T135	0	1	0	0
T137	0	1	0	0
T138	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	100789	0	0
T14	16893	38	0	0
T15	654	0	0	0
T16	23347	0	0	0
T17	24696	0	0	0
T20	0	98126	0	0
T21	0	43	0	0
T23	0	228	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T50	0	101	0	0
T52	0	35	0	0
T58	1012	0	0	0
T65	504	0	0	0
T115	0	40	0	0
T135	0	36	0	0
T137	0	35	0	0
T138	0	76	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6518002	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	16	0	0
T21	12011	1	0	0
T50	0	1	0	0
T54	785	0	0	0
T63	491	0	0	0
T64	488	0	0	0
T115	0	1	0	0
T119	0	1	0	0
T138	0	1	0	0
T139	0	1	0	0
T140	0	1	0	0
T141	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0
T144	417	0	0	0
T145	435	0	0	0
T146	410	0	0	0
T147	504	0	0	0
T148	457	0	0	0
T149	802	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T14,T18,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T14,T18,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T18,T20,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T18,T20
1	0	Covered	T1,T4,T24
1	1	Covered	T14,T18,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T18,T21,T23
0	1	Covered	T20
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T18,T21,T23
0	1	Covered	T18,T21,T23
1	0	Covered	T82,T83

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T18,T21,T23
1	-	Covered	T18,T21,T23

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T14,T18,T20
DetectSt	168	Covered	T18,T20,T21
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T18,T21,T23

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T18,T20,T21
DebounceSt->IdleSt	163	Covered	T14,T150,T151
DetectSt->IdleSt	186	Covered	T20
DetectSt->StableSt	191	Covered	T18,T21,T23
IdleSt->DebounceSt	148	Covered	T14,T18,T20
StableSt->IdleSt	206	Covered	T18,T21,T23

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T18,T20
0	1	Covered	T14,T18,T20
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T20,T21
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T18,T20
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T18,T20,T21
DebounceSt	-	0	1	0	-	-	-	Covered	T14,T151,T143
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T18,T20
DetectSt	-	-	-	-	1	-	-	Covered	T20
DetectSt	-	-	-	-	0	1	-	Covered	T18,T21,T23
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T18,T21,T23
StableSt	-	-	-	-	-	-	0	Covered	T18,T21,T23
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7138329	116	0	0
CntIncr_A	7138329	184812	0	0
CntNoWrap_A	7138329	6515515	0	0
DetectStDropOut_A	7138329	1	0	0
DetectedOut_A	7138329	62949	0	0
DetectedPulseOut_A	7138329	55	0	0
DisabledIdleSt_A	7138329	5824861	0	0
DisabledNoDetection_A	7138329	5827183	0	0
EnterDebounceSt_A	7138329	61	0	0
EnterDetectSt_A	7138329	56	0	0
EnterStableSt_A	7138329	55	0	0
PulseIsPulse_A	7138329	55	0	0
StayInStableSt	7138329	62872	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7138329	2386	0	0
gen_low_level_sva.LowLevelEvent_A	7138329	6518002	0	0
gen_not_sticky_sva.StableStDropOut_A	7138329	31	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	116	0	0
T14	16893	1	0	0
T15	654	0	0	0
T16	23347	0	0	0
T17	24696	0	0	0
T18	0	6	0	0
T20	0	2	0	0
T21	0	2	0	0
T23	0	2	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T51	0	2	0	0
T58	1012	0	0	0
T65	504	0	0	0
T87	0	2	0	0
T115	0	4	0	0
T152	0	4	0	0
T153	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	184812	0	0
T14	16893	15	0	0
T15	654	0	0	0
T16	23347	0	0	0
T17	24696	0	0	0
T18	0	138	0	0
T20	0	46919	0	0
T21	0	82	0	0
T23	0	74	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T51	0	75	0	0
T58	1012	0	0	0
T65	504	0	0	0
T87	0	74	0	0
T115	0	78	0	0
T152	0	62	0	0
T153	0	54	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6515515	0	0
T1	20092	19645	0	0
T2	15963	15539	0	0
T4	496	95	0	0
T5	693	292	0	0
T24	449	48	0	0
T25	403	2	0	0
T26	505	104	0	0
T27	406	5	0	0
T28	20119	19678	0	0
T29	405	4	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	1	0	0
T20	192377	1	0	0
T21	12011	0	0	0
T54	785	0	0	0
T62	493	0	0	0
T63	491	0	0	0
T64	488	0	0	0
T144	417	0	0	0
T145	435	0	0	0
T146	410	0	0	0
T147	504	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	62949	0	0
T18	32110	86	0	0
T19	61033	0	0	0
T21	0	62	0	0
T23	0	170	0	0
T51	0	126	0	0
T53	684	0	0	0
T60	493	0	0	0
T61	494	0	0	0
T66	2290	0	0	0
T67	10880	0	0	0
T68	19650	0	0	0
T87	0	146	0	0
T115	0	129	0	0
T150	0	64	0	0
T152	0	78	0	0
T153	0	1	0	0
T154	0	20	0	0
T155	425	0	0	0
T156	439	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	55	0	0
T18	32110	3	0	0
T19	61033	0	0	0
T21	0	1	0	0
T23	0	1	0	0
T51	0	1	0	0
T53	684	0	0	0
T60	493	0	0	0
T61	494	0	0	0
T66	2290	0	0	0
T67	10880	0	0	0
T68	19650	0	0	0
T87	0	1	0	0
T115	0	2	0	0
T150	0	2	0	0
T152	0	2	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	425	0	0	0
T156	439	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	5824861	0	0
T1	20092	19645	0	0
T2	15963	15539	0	0
T4	496	95	0	0
T5	693	292	0	0
T24	449	48	0	0
T25	403	2	0	0
T26	505	104	0	0
T27	406	5	0	0
T28	20119	19678	0	0
T29	405	4	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	5827183	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	61	0	0
T14	16893	1	0	0
T15	654	0	0	0
T16	23347	0	0	0
T17	24696	0	0	0
T18	0	3	0	0
T20	0	1	0	0
T21	0	1	0	0
T23	0	1	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T51	0	1	0	0
T58	1012	0	0	0
T65	504	0	0	0
T87	0	1	0	0
T115	0	2	0	0
T152	0	2	0	0
T153	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	56	0	0
T18	32110	3	0	0
T19	61033	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T23	0	1	0	0
T51	0	1	0	0
T53	684	0	0	0
T60	493	0	0	0
T61	494	0	0	0
T66	2290	0	0	0
T67	10880	0	0	0
T68	19650	0	0	0
T87	0	1	0	0
T115	0	2	0	0
T150	0	2	0	0
T152	0	2	0	0
T153	0	1	0	0
T155	425	0	0	0
T156	439	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	55	0	0
T18	32110	3	0	0
T19	61033	0	0	0
T21	0	1	0	0
T23	0	1	0	0
T51	0	1	0	0
T53	684	0	0	0
T60	493	0	0	0
T61	494	0	0	0
T66	2290	0	0	0
T67	10880	0	0	0
T68	19650	0	0	0
T87	0	1	0	0
T115	0	2	0	0
T150	0	2	0	0
T152	0	2	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	425	0	0	0
T156	439	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	55	0	0
T18	32110	3	0	0
T19	61033	0	0	0
T21	0	1	0	0
T23	0	1	0	0
T51	0	1	0	0
T53	684	0	0	0
T60	493	0	0	0
T61	494	0	0	0
T66	2290	0	0	0
T67	10880	0	0	0
T68	19650	0	0	0
T87	0	1	0	0
T115	0	2	0	0
T150	0	2	0	0
T152	0	2	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	425	0	0	0
T156	439	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	62872	0	0
T18	32110	82	0	0
T19	61033	0	0	0
T21	0	61	0	0
T23	0	169	0	0
T51	0	124	0	0
T53	684	0	0	0
T60	493	0	0	0
T61	494	0	0	0
T66	2290	0	0	0
T67	10880	0	0	0
T68	19650	0	0	0
T87	0	144	0	0
T115	0	126	0	0
T150	0	62	0	0
T152	0	75	0	0
T154	0	19	0	0
T155	425	0	0	0
T156	439	0	0	0
T157	0	55	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	2386	0	0
T2	15963	0	0	0
T3	21356	0	0	0
T4	496	5	0	0
T5	693	0	0	0
T11	0	1	0	0
T12	0	18	0	0
T24	449	6	0	0
T25	403	0	0	0
T26	505	4	0	0
T27	406	0	0	0
T28	20119	0	0	0
T29	405	0	0	0
T39	0	5	0	0
T40	0	6	0	0
T41	0	5	0	0
T42	0	6	0	0
T47	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6518002	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	31	0	0
T18	32110	2	0	0
T19	61033	0	0	0
T21	0	1	0	0
T23	0	1	0	0
T53	684	0	0	0
T60	493	0	0	0
T61	494	0	0	0
T66	2290	0	0	0
T67	10880	0	0	0
T68	19650	0	0	0
T115	0	1	0	0
T136	0	2	0	0
T150	0	2	0	0
T152	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	425	0	0	0
T156	439	0	0	0
T157	0	1	0	0