Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.74	93.48	95.24		100.00	90.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.74	93.48	95.24		100.00	90.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.13	95.65	100.00		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.13	95.65	100.00		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T14,T15,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T14,T15,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T14,T15,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T18
1	0	Covered	T1,T4,T5
1	1	Covered	T14,T15,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T20
0	1	Covered	T158
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T20
0	1	Covered	T15,T92,T159
1	0	Covered	T82,T83

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T15,T20
1	-	Covered	T15,T92,T159

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T14,T15,T20
DetectSt	168	Covered	T14,T15,T20
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T14,T15,T20

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T14,T15,T20
DebounceSt->IdleSt	163	Covered	T137
DetectSt->IdleSt	186	Covered	T158
DetectSt->StableSt	191	Covered	T14,T15,T20
IdleSt->DebounceSt	148	Covered	T14,T15,T20
StableSt->IdleSt	206	Covered	T14,T15,T87

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T15,T20
0	1	Covered	T14,T15,T20
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T20
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T15,T20
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T15,T20
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T15,T20
DetectSt	-	-	-	-	1	-	-	Covered	T158
DetectSt	-	-	-	-	0	1	-	Covered	T14,T15,T20
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T15,T92,T82
StableSt	-	-	-	-	-	-	0	Covered	T14,T15,T20
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7138329	64	0	0
CntIncr_A	7138329	48494	0	0
CntNoWrap_A	7138329	6515567	0	0
DetectStDropOut_A	7138329	1	0	0
DetectedOut_A	7138329	52771	0	0
DetectedPulseOut_A	7138329	31	0	0
DisabledIdleSt_A	7138329	6210958	0	0
DisabledNoDetection_A	7138329	6213282	0	0
EnterDebounceSt_A	7138329	33	0	0
EnterDetectSt_A	7138329	32	0	0
EnterStableSt_A	7138329	31	0	0
PulseIsPulse_A	7138329	31	0	0
StayInStableSt	7138329	52725	0	0
gen_high_level_sva.HighLevelEvent_A	7138329	6518002	0	0
gen_not_sticky_sva.StableStDropOut_A	7138329	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	64	0	0
T14	16893	2	0	0
T15	654	2	0	0
T16	23347	0	0	0
T17	24696	0	0	0
T20	0	2	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T58	1012	0	0	0
T65	504	0	0	0
T82	0	2	0	0
T87	0	2	0	0
T92	0	2	0	0
T137	0	2	0	0
T150	0	2	0	0
T159	0	2	0	0
T160	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	48494	0	0
T14	16893	15	0	0
T15	654	27	0	0
T16	23347	0	0	0
T17	24696	0	0	0
T20	0	46919	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T58	1012	0	0	0
T65	504	0	0	0
T82	0	44	0	0
T87	0	74	0	0
T92	0	100	0	0
T137	0	78	0	0
T150	0	36	0	0
T159	0	53	0	0
T160	0	50	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6515567	0	0
T1	20092	19645	0	0
T2	15963	15539	0	0
T4	496	95	0	0
T5	693	292	0	0
T24	449	48	0	0
T25	403	2	0	0
T26	505	104	0	0
T27	406	5	0	0
T28	20119	19678	0	0
T29	405	4	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	1	0	0
T158	5579	1	0	0
T161	833	0	0	0
T162	3910	0	0	0
T163	704	0	0	0
T164	28757	0	0	0
T165	7370	0	0	0
T166	6758	0	0	0
T167	426	0	0	0
T168	441	0	0	0
T169	10098	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	52771	0	0
T14	16893	41	0	0
T15	654	40	0	0
T16	23347	0	0	0
T17	24696	0	0	0
T20	0	51166	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T58	1012	0	0	0
T65	504	0	0	0
T82	0	1	0	0
T87	0	46	0	0
T92	0	1	0	0
T137	0	38	0	0
T150	0	96	0	0
T159	0	96	0	0
T160	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	31	0	0
T14	16893	1	0	0
T15	654	1	0	0
T16	23347	0	0	0
T17	24696	0	0	0
T20	0	1	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T58	1012	0	0	0
T65	504	0	0	0
T82	0	1	0	0
T87	0	1	0	0
T92	0	1	0	0
T137	0	1	0	0
T150	0	1	0	0
T159	0	1	0	0
T160	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6210958	0	0
T1	20092	19645	0	0
T2	15963	15539	0	0
T4	496	95	0	0
T5	693	292	0	0
T24	449	48	0	0
T25	403	2	0	0
T26	505	104	0	0
T27	406	5	0	0
T28	20119	19678	0	0
T29	405	4	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6213282	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	33	0	0
T14	16893	1	0	0
T15	654	1	0	0
T16	23347	0	0	0
T17	24696	0	0	0
T20	0	1	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T58	1012	0	0	0
T65	504	0	0	0
T82	0	1	0	0
T87	0	1	0	0
T92	0	1	0	0
T137	0	2	0	0
T150	0	1	0	0
T159	0	1	0	0
T160	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	32	0	0
T14	16893	1	0	0
T15	654	1	0	0
T16	23347	0	0	0
T17	24696	0	0	0
T20	0	1	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T58	1012	0	0	0
T65	504	0	0	0
T82	0	1	0	0
T87	0	1	0	0
T92	0	1	0	0
T137	0	1	0	0
T150	0	1	0	0
T159	0	1	0	0
T160	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	31	0	0
T14	16893	1	0	0
T15	654	1	0	0
T16	23347	0	0	0
T17	24696	0	0	0
T20	0	1	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T58	1012	0	0	0
T65	504	0	0	0
T82	0	1	0	0
T87	0	1	0	0
T92	0	1	0	0
T137	0	1	0	0
T150	0	1	0	0
T159	0	1	0	0
T160	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	31	0	0
T14	16893	1	0	0
T15	654	1	0	0
T16	23347	0	0	0
T17	24696	0	0	0
T20	0	1	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T58	1012	0	0	0
T65	504	0	0	0
T82	0	1	0	0
T87	0	1	0	0
T92	0	1	0	0
T137	0	1	0	0
T150	0	1	0	0
T159	0	1	0	0
T160	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	52725	0	0
T14	16893	39	0	0
T15	654	39	0	0
T16	23347	0	0	0
T17	24696	0	0	0
T20	0	51164	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T58	1012	0	0	0
T65	504	0	0	0
T87	0	44	0	0
T137	0	36	0	0
T139	0	35	0	0
T150	0	94	0	0
T151	0	39	0	0
T159	0	95	0	0
T160	0	40	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6518002	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	14	0	0
T15	654	1	0	0
T16	23347	0	0	0
T17	24696	0	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T34	1192	0	0	0
T58	1012	0	0	0
T65	504	0	0	0
T92	0	1	0	0
T141	0	1	0	0
T151	0	1	0	0
T159	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0
T172	0	1	0	0
T173	0	1	0	0
T174	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T14,T18,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T14,T18,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T18,T21,T22

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T17,T18
1	0	Covered	T1,T4,T24
1	1	Covered	T14,T18,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T18,T21,T22
0	1	Covered	T49,T153,T135
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T18,T21,T22
0	1	Covered	T21,T23,T50
1	0	Covered	T82,T83

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T18,T21,T22
1	-	Covered	T21,T23,T50

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T14,T18,T21
DetectSt	168	Covered	T18,T21,T22
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T18,T21,T22

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T18,T21,T22
DebounceSt->IdleSt	163	Covered	T14,T18,T49
DetectSt->IdleSt	186	Covered	T49,T153,T135
DetectSt->StableSt	191	Covered	T18,T21,T22
IdleSt->DebounceSt	148	Covered	T14,T18,T21
StableSt->IdleSt	206	Covered	T18,T21,T22

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T18,T21
0	1	Covered	T14,T18,T21
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T21,T22
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T18,T21
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T18,T21,T22
DebounceSt	-	0	1	0	-	-	-	Covered	T14,T18,T49
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T18,T21
DetectSt	-	-	-	-	1	-	-	Covered	T49,T153,T135
DetectSt	-	-	-	-	0	1	-	Covered	T18,T21,T22
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T21,T23,T50
StableSt	-	-	-	-	-	-	0	Covered	T18,T21,T22
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7138329	151	0	0
CntIncr_A	7138329	3954	0	0
CntNoWrap_A	7138329	6515480	0	0
DetectStDropOut_A	7138329	5	0	0
DetectedOut_A	7138329	4583	0	0
DetectedPulseOut_A	7138329	68	0	0
DisabledIdleSt_A	7138329	6497437	0	0
DisabledNoDetection_A	7138329	6499752	0	0
EnterDebounceSt_A	7138329	79	0	0
EnterDetectSt_A	7138329	73	0	0
EnterStableSt_A	7138329	68	0	0
PulseIsPulse_A	7138329	68	0	0
StayInStableSt	7138329	4487	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7138329	2678	0	0
gen_low_level_sva.LowLevelEvent_A	7138329	6518002	0	0
gen_not_sticky_sva.StableStDropOut_A	7138329	38	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	151	0	0
T14	16893	1	0	0
T15	654	0	0	0
T16	23347	0	0	0
T17	24696	0	0	0
T18	0	5	0	0
T21	0	4	0	0
T22	0	2	0	0
T23	0	2	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T49	0	3	0	0
T50	0	4	0	0
T51	0	4	0	0
T58	1012	0	0	0
T65	504	0	0	0
T115	0	2	0	0
T175	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	3954	0	0
T14	16893	15	0	0
T15	654	0	0	0
T16	23347	0	0	0
T17	24696	0	0	0
T18	0	78	0	0
T21	0	156	0	0
T22	0	13	0	0
T23	0	74	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T49	0	76	0	0
T50	0	94	0	0
T51	0	150	0	0
T58	1012	0	0	0
T65	504	0	0	0
T115	0	39	0	0
T175	0	44	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6515480	0	0
T1	20092	19645	0	0
T2	15963	15539	0	0
T4	496	95	0	0
T5	693	292	0	0
T24	449	48	0	0
T25	403	2	0	0
T26	505	104	0	0
T27	406	5	0	0
T28	20119	19678	0	0
T29	405	4	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	5	0	0
T49	2401	1	0	0
T111	794	0	0	0
T112	572	0	0	0
T135	0	1	0	0
T153	0	1	0	0
T170	0	1	0	0
T176	0	1	0	0
T177	504	0	0	0
T178	6317	0	0	0
T179	659	0	0	0
T180	552	0	0	0
T181	503	0	0	0
T182	27703	0	0	0
T183	522	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	4583	0	0
T18	32110	298	0	0
T19	61033	0	0	0
T21	0	101	0	0
T22	0	41	0	0
T23	0	125	0	0
T50	0	184	0	0
T51	0	28	0	0
T53	684	0	0	0
T60	493	0	0	0
T61	494	0	0	0
T66	2290	0	0	0
T67	10880	0	0	0
T68	19650	0	0	0
T87	0	24	0	0
T115	0	68	0	0
T150	0	80	0	0
T155	425	0	0	0
T156	439	0	0	0
T175	0	46	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	68	0	0
T18	32110	2	0	0
T19	61033	0	0	0
T21	0	2	0	0
T22	0	1	0	0
T23	0	1	0	0
T50	0	2	0	0
T51	0	2	0	0
T53	684	0	0	0
T60	493	0	0	0
T61	494	0	0	0
T66	2290	0	0	0
T67	10880	0	0	0
T68	19650	0	0	0
T87	0	1	0	0
T115	0	1	0	0
T150	0	1	0	0
T155	425	0	0	0
T156	439	0	0	0
T175	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6497437	0	0
T1	20092	19645	0	0
T2	15963	15539	0	0
T4	496	95	0	0
T5	693	292	0	0
T24	449	48	0	0
T25	403	2	0	0
T26	505	104	0	0
T27	406	5	0	0
T28	20119	19678	0	0
T29	405	4	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6499752	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	79	0	0
T14	16893	1	0	0
T15	654	0	0	0
T16	23347	0	0	0
T17	24696	0	0	0
T18	0	3	0	0
T21	0	2	0	0
T22	0	1	0	0
T23	0	1	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T49	0	2	0	0
T50	0	2	0	0
T51	0	2	0	0
T58	1012	0	0	0
T65	504	0	0	0
T115	0	1	0	0
T175	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	73	0	0
T18	32110	2	0	0
T19	61033	0	0	0
T21	0	2	0	0
T22	0	1	0	0
T23	0	1	0	0
T49	0	1	0	0
T50	0	2	0	0
T51	0	2	0	0
T53	684	0	0	0
T60	493	0	0	0
T61	494	0	0	0
T66	2290	0	0	0
T67	10880	0	0	0
T68	19650	0	0	0
T115	0	1	0	0
T153	0	1	0	0
T155	425	0	0	0
T156	439	0	0	0
T175	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	68	0	0
T18	32110	2	0	0
T19	61033	0	0	0
T21	0	2	0	0
T22	0	1	0	0
T23	0	1	0	0
T50	0	2	0	0
T51	0	2	0	0
T53	684	0	0	0
T60	493	0	0	0
T61	494	0	0	0
T66	2290	0	0	0
T67	10880	0	0	0
T68	19650	0	0	0
T87	0	1	0	0
T115	0	1	0	0
T150	0	1	0	0
T155	425	0	0	0
T156	439	0	0	0
T175	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	68	0	0
T18	32110	2	0	0
T19	61033	0	0	0
T21	0	2	0	0
T22	0	1	0	0
T23	0	1	0	0
T50	0	2	0	0
T51	0	2	0	0
T53	684	0	0	0
T60	493	0	0	0
T61	494	0	0	0
T66	2290	0	0	0
T67	10880	0	0	0
T68	19650	0	0	0
T87	0	1	0	0
T115	0	1	0	0
T150	0	1	0	0
T155	425	0	0	0
T156	439	0	0	0
T175	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	4487	0	0
T18	32110	294	0	0
T19	61033	0	0	0
T21	0	98	0	0
T22	0	39	0	0
T23	0	124	0	0
T50	0	181	0	0
T51	0	26	0	0
T53	684	0	0	0
T60	493	0	0	0
T61	494	0	0	0
T66	2290	0	0	0
T67	10880	0	0	0
T68	19650	0	0	0
T87	0	23	0	0
T115	0	66	0	0
T150	0	79	0	0
T155	425	0	0	0
T156	439	0	0	0
T175	0	44	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	2678	0	0
T2	15963	0	0	0
T3	21356	0	0	0
T4	496	5	0	0
T5	693	0	0	0
T11	0	1	0	0
T12	0	21	0	0
T24	449	3	0	0
T25	403	0	0	0
T26	505	5	0	0
T27	406	0	0	0
T28	20119	0	0	0
T29	405	0	0	0
T39	0	6	0	0
T40	0	6	0	0
T41	0	6	0	0
T42	0	6	0	0
T47	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6518002	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	38	0	0
T21	12011	1	0	0
T23	0	1	0	0
T50	0	1	0	0
T51	0	2	0	0
T54	785	0	0	0
T63	491	0	0	0
T64	488	0	0	0
T87	0	1	0	0
T139	0	1	0	0
T144	417	0	0	0
T145	435	0	0	0
T146	410	0	0	0
T147	504	0	0	0
T148	457	0	0	0
T149	802	0	0	0
T150	0	1	0	0
T157	0	1	0	0
T160	0	1	0	0
T184	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T24

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T24
1	1	Covered	T1,T4,T24

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T15,T18,T19

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T15,T18,T19

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T15,T18,T19

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T18,T19
1	0	Covered	T1,T4,T24
1	1	Covered	T15,T18,T19

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T18,T19
0	1	Covered	T20,T119,T143
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T18,T19
0	1	Covered	T18,T185,T157
1	0	Covered	T82,T83

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T15,T18,T19
1	-	Covered	T18,T185,T157

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T15,T18,T19
DetectSt	168	Covered	T15,T18,T19
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T15,T18,T19

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T15,T18,T19
DebounceSt->IdleSt	163	Covered	T15,T186
DetectSt->IdleSt	186	Covered	T20,T119,T143
DetectSt->StableSt	191	Covered	T15,T18,T19
IdleSt->DebounceSt	148	Covered	T15,T18,T19
StableSt->IdleSt	206	Covered	T18,T87,T92

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T15,T18,T19
0	1	Covered	T15,T18,T19
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T18,T19
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T15,T18,T19
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T24
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T18,T19
DebounceSt	-	0	1	0	-	-	-	Covered	T15,T186
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T18,T19
DetectSt	-	-	-	-	1	-	-	Covered	T20,T119,T143
DetectSt	-	-	-	-	0	1	-	Covered	T15,T18,T19
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T18,T185,T157
StableSt	-	-	-	-	-	-	0	Covered	T15,T18,T19
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7138329	100	0	0
CntIncr_A	7138329	196157	0	0
CntNoWrap_A	7138329	6515531	0	0
DetectStDropOut_A	7138329	3	0	0
DetectedOut_A	7138329	4934	0	0
DetectedPulseOut_A	7138329	46	0	0
DisabledIdleSt_A	7138329	6009115	0	0
DisabledNoDetection_A	7138329	6011441	0	0
EnterDebounceSt_A	7138329	51	0	0
EnterDetectSt_A	7138329	49	0	0
EnterStableSt_A	7138329	46	0	0
PulseIsPulse_A	7138329	46	0	0
StayInStableSt	7138329	4865	0	0
gen_high_level_sva.HighLevelEvent_A	7138329	6518002	0	0
gen_not_sticky_sva.StableStDropOut_A	7138329	21	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	100	0	0
T15	654	3	0	0
T16	23347	0	0	0
T17	24696	0	0	0
T18	0	8	0	0
T19	0	2	0	0
T20	0	4	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T34	1192	0	0	0
T58	1012	0	0	0
T65	504	0	0	0
T87	0	2	0	0
T92	0	2	0	0
T137	0	2	0	0
T157	0	4	0	0
T185	0	2	0	0
T187	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	196157	0	0
T15	654	54	0	0
T16	23347	0	0	0
T17	24696	0	0	0
T18	0	124	0	0
T19	0	53138	0	0
T20	0	93838	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T34	1192	0	0	0
T58	1012	0	0	0
T65	504	0	0	0
T87	0	74	0	0
T92	0	100	0	0
T137	0	67	0	0
T157	0	78	0	0
T185	0	94	0	0
T187	0	19	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6515531	0	0
T1	20092	19645	0	0
T2	15963	15539	0	0
T4	496	95	0	0
T5	693	292	0	0
T24	449	48	0	0
T25	403	2	0	0
T26	505	104	0	0
T27	406	5	0	0
T28	20119	19678	0	0
T29	405	4	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	3	0	0
T20	192377	1	0	0
T21	12011	0	0	0
T54	785	0	0	0
T62	493	0	0	0
T63	491	0	0	0
T64	488	0	0	0
T119	0	1	0	0
T143	0	1	0	0
T144	417	0	0	0
T145	435	0	0	0
T146	410	0	0	0
T147	504	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	4934	0	0
T15	654	146	0	0
T16	23347	0	0	0
T17	24696	0	0	0
T18	0	328	0	0
T19	0	42	0	0
T20	0	40	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T34	1192	0	0	0
T58	1012	0	0	0
T65	504	0	0	0
T87	0	261	0	0
T92	0	368	0	0
T137	0	162	0	0
T157	0	212	0	0
T185	0	327	0	0
T187	0	67	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	46	0	0
T15	654	1	0	0
T16	23347	0	0	0
T17	24696	0	0	0
T18	0	4	0	0
T19	0	1	0	0
T20	0	1	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T34	1192	0	0	0
T58	1012	0	0	0
T65	504	0	0	0
T87	0	1	0	0
T92	0	1	0	0
T137	0	1	0	0
T157	0	2	0	0
T185	0	1	0	0
T187	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6009115	0	0
T1	20092	19645	0	0
T2	15963	15539	0	0
T4	496	95	0	0
T5	693	292	0	0
T24	449	48	0	0
T25	403	2	0	0
T26	505	104	0	0
T27	406	5	0	0
T28	20119	19678	0	0
T29	405	4	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6011441	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	51	0	0
T15	654	2	0	0
T16	23347	0	0	0
T17	24696	0	0	0
T18	0	4	0	0
T19	0	1	0	0
T20	0	2	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T34	1192	0	0	0
T58	1012	0	0	0
T65	504	0	0	0
T87	0	1	0	0
T92	0	1	0	0
T137	0	1	0	0
T157	0	2	0	0
T185	0	1	0	0
T187	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	49	0	0
T15	654	1	0	0
T16	23347	0	0	0
T17	24696	0	0	0
T18	0	4	0	0
T19	0	1	0	0
T20	0	2	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T34	1192	0	0	0
T58	1012	0	0	0
T65	504	0	0	0
T87	0	1	0	0
T92	0	1	0	0
T137	0	1	0	0
T157	0	2	0	0
T185	0	1	0	0
T187	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	46	0	0
T15	654	1	0	0
T16	23347	0	0	0
T17	24696	0	0	0
T18	0	4	0	0
T19	0	1	0	0
T20	0	1	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T34	1192	0	0	0
T58	1012	0	0	0
T65	504	0	0	0
T87	0	1	0	0
T92	0	1	0	0
T137	0	1	0	0
T157	0	2	0	0
T185	0	1	0	0
T187	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	46	0	0
T15	654	1	0	0
T16	23347	0	0	0
T17	24696	0	0	0
T18	0	4	0	0
T19	0	1	0	0
T20	0	1	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T34	1192	0	0	0
T58	1012	0	0	0
T65	504	0	0	0
T87	0	1	0	0
T92	0	1	0	0
T137	0	1	0	0
T157	0	2	0	0
T185	0	1	0	0
T187	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	4865	0	0
T15	654	144	0	0
T16	23347	0	0	0
T17	24696	0	0	0
T18	0	323	0	0
T19	0	40	0	0
T20	0	38	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T34	1192	0	0	0
T58	1012	0	0	0
T65	504	0	0	0
T87	0	259	0	0
T92	0	366	0	0
T137	0	160	0	0
T157	0	209	0	0
T185	0	326	0	0
T187	0	65	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6518002	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	21	0	0
T18	32110	3	0	0
T19	61033	0	0	0
T53	684	0	0	0
T60	493	0	0	0
T61	494	0	0	0
T66	2290	0	0	0
T67	10880	0	0	0
T68	19650	0	0	0
T136	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0
T155	425	0	0	0
T156	439	0	0	0
T157	0	1	0	0
T159	0	1	0	0
T172	0	1	0	0
T185	0	1	0	0
T188	0	1	0	0
T189	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T24
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T24
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T14,T18,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T14,T18,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T14,T18,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T18,T19
1	0	Covered	T1,T4,T24
1	1	Covered	T14,T18,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T18,T20
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T18,T20
0	1	Covered	T18,T20,T23
1	0	Covered	T82,T83

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T18,T20
1	-	Covered	T18,T20,T23

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T14,T18,T20
DetectSt	168	Covered	T14,T18,T20
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T14,T18,T20

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T14,T18,T20
DebounceSt->IdleSt	163	Covered	T18,T137
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T14,T18,T20
IdleSt->DebounceSt	148	Covered	T14,T18,T20
StableSt->IdleSt	206	Covered	T14,T18,T20

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T18,T20
0	1	Covered	T14,T18,T20
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T18,T20
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T18,T20
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T18,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T18
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T18,T20
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T14,T18,T20
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T18,T20,T23
StableSt	-	-	-	-	-	-	0	Covered	T14,T18,T20
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7138329	55	0	0
CntIncr_A	7138329	48244	0	0
CntNoWrap_A	7138329	6515576	0	0
DetectStDropOut_A	7138329	0	0	0
DetectedOut_A	7138329	53450	0	0
DetectedPulseOut_A	7138329	27	0	0
DisabledIdleSt_A	7138329	5999966	0	0
DisabledNoDetection_A	7138329	6002280	0	0
EnterDebounceSt_A	7138329	29	0	0
EnterDetectSt_A	7138329	27	0	0
EnterStableSt_A	7138329	27	0	0
PulseIsPulse_A	7138329	27	0	0
StayInStableSt	7138329	53409	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7138329	6558	0	0
gen_low_level_sva.LowLevelEvent_A	7138329	6518002	0	0
gen_not_sticky_sva.StableStDropOut_A	7138329	11	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	55	0	0
T14	16893	2	0	0
T15	654	0	0	0
T16	23347	0	0	0
T17	24696	0	0	0
T18	0	5	0	0
T20	0	2	0	0
T21	0	2	0	0
T23	0	2	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T51	0	2	0	0
T58	1012	0	0	0
T65	504	0	0	0
T82	0	2	0	0
T115	0	2	0	0
T152	0	2	0	0
T159	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	48244	0	0
T14	16893	15	0	0
T15	654	0	0	0
T16	23347	0	0	0
T17	24696	0	0	0
T18	0	78	0	0
T20	0	46919	0	0
T21	0	78	0	0
T23	0	74	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T51	0	75	0	0
T58	1012	0	0	0
T65	504	0	0	0
T82	0	44	0	0
T115	0	39	0	0
T137	0	12	0	0
T152	0	31	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6515576	0	0
T1	20092	19645	0	0
T2	15963	15539	0	0
T4	496	95	0	0
T5	693	292	0	0
T24	449	48	0	0
T25	403	2	0	0
T26	505	104	0	0
T27	406	5	0	0
T28	20119	19678	0	0
T29	405	4	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	53450	0	0
T14	16893	41	0	0
T15	654	0	0	0
T16	23347	0	0	0
T17	24696	0	0	0
T18	0	49	0	0
T20	0	51169	0	0
T21	0	59	0	0
T23	0	126	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T51	0	246	0	0
T58	1012	0	0	0
T65	504	0	0	0
T82	0	2	0	0
T115	0	109	0	0
T152	0	39	0	0
T159	0	1	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	27	0	0
T14	16893	1	0	0
T15	654	0	0	0
T16	23347	0	0	0
T17	24696	0	0	0
T18	0	2	0	0
T20	0	1	0	0
T21	0	1	0	0
T23	0	1	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T51	0	1	0	0
T58	1012	0	0	0
T65	504	0	0	0
T82	0	1	0	0
T115	0	1	0	0
T152	0	1	0	0
T159	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	5999966	0	0
T1	20092	19645	0	0
T2	15963	15539	0	0
T4	496	95	0	0
T5	693	292	0	0
T24	449	48	0	0
T25	403	2	0	0
T26	505	104	0	0
T27	406	5	0	0
T28	20119	19678	0	0
T29	405	4	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6002280	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	29	0	0
T14	16893	1	0	0
T15	654	0	0	0
T16	23347	0	0	0
T17	24696	0	0	0
T18	0	3	0	0
T20	0	1	0	0
T21	0	1	0	0
T23	0	1	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T51	0	1	0	0
T58	1012	0	0	0
T65	504	0	0	0
T82	0	1	0	0
T115	0	1	0	0
T137	0	1	0	0
T152	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	27	0	0
T14	16893	1	0	0
T15	654	0	0	0
T16	23347	0	0	0
T17	24696	0	0	0
T18	0	2	0	0
T20	0	1	0	0
T21	0	1	0	0
T23	0	1	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T51	0	1	0	0
T58	1012	0	0	0
T65	504	0	0	0
T82	0	1	0	0
T115	0	1	0	0
T152	0	1	0	0
T159	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	27	0	0
T14	16893	1	0	0
T15	654	0	0	0
T16	23347	0	0	0
T17	24696	0	0	0
T18	0	2	0	0
T20	0	1	0	0
T21	0	1	0	0
T23	0	1	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T51	0	1	0	0
T58	1012	0	0	0
T65	504	0	0	0
T82	0	1	0	0
T115	0	1	0	0
T152	0	1	0	0
T159	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	27	0	0
T14	16893	1	0	0
T15	654	0	0	0
T16	23347	0	0	0
T17	24696	0	0	0
T18	0	2	0	0
T20	0	1	0	0
T21	0	1	0	0
T23	0	1	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T51	0	1	0	0
T58	1012	0	0	0
T65	504	0	0	0
T82	0	1	0	0
T115	0	1	0	0
T152	0	1	0	0
T159	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	53409	0	0
T14	16893	39	0	0
T15	654	0	0	0
T16	23347	0	0	0
T17	24696	0	0	0
T18	0	46	0	0
T20	0	51168	0	0
T21	0	57	0	0
T23	0	125	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T51	0	244	0	0
T58	1012	0	0	0
T65	504	0	0	0
T82	0	1	0	0
T115	0	107	0	0
T152	0	38	0	0
T188	0	257	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6558	0	0
T1	20092	10	0	0
T2	15963	24	0	0
T3	0	8	0	0
T4	496	6	0	0
T5	693	0	0	0
T6	0	12	0	0
T7	0	29	0	0
T24	449	4	0	0
T25	403	0	0	0
T26	505	4	0	0
T27	406	0	0	0
T28	20119	11	0	0
T29	405	0	0	0
T47	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6518002	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	11	0	0
T18	32110	1	0	0
T19	61033	0	0	0
T20	0	1	0	0
T23	0	1	0	0
T53	684	0	0	0
T60	493	0	0	0
T61	494	0	0	0
T66	2290	0	0	0
T67	10880	0	0	0
T68	19650	0	0	0
T143	0	1	0	0
T152	0	1	0	0
T155	425	0	0	0
T156	439	0	0	0
T158	0	1	0	0
T159	0	1	0	0
T174	0	1	0	0
T190	0	1	0	0
T191	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T24

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T24
1	1	Covered	T1,T4,T24

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T15,T21,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T15,T21,T23

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T15,T21,T23

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T15,T21
1	0	Covered	T1,T4,T24
1	1	Covered	T15,T21,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T21,T23
0	1	Covered	T158,T143
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T21,T23
0	1	Covered	T23,T52,T187
1	0	Covered	T82,T83

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T15,T21,T23
1	-	Covered	T23,T52,T187

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T15,T21,T23
DetectSt	168	Covered	T15,T21,T23
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T15,T21,T23

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T15,T21,T23
DebounceSt->IdleSt	163	Covered	T176,T158
DetectSt->IdleSt	186	Covered	T158,T143
DetectSt->StableSt	191	Covered	T15,T21,T23
IdleSt->DebounceSt	148	Covered	T15,T21,T23
StableSt->IdleSt	206	Covered	T21,T23,T52

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T15,T21,T23
0	1	Covered	T15,T21,T23
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T21,T23
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T15,T21,T23
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T24
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T21,T23
DebounceSt	-	0	1	0	-	-	-	Covered	T176,T158
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T21,T23
DetectSt	-	-	-	-	1	-	-	Covered	T158,T143
DetectSt	-	-	-	-	0	1	-	Covered	T15,T21,T23
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T23,T52,T187
StableSt	-	-	-	-	-	-	0	Covered	T15,T21,T23
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7138329	98	0	0
CntIncr_A	7138329	2875	0	0
CntNoWrap_A	7138329	6515533	0	0
DetectStDropOut_A	7138329	2	0	0
DetectedOut_A	7138329	4248	0	0
DetectedPulseOut_A	7138329	46	0	0
DisabledIdleSt_A	7138329	6493747	0	0
DisabledNoDetection_A	7138329	6496076	0	0
EnterDebounceSt_A	7138329	50	0	0
EnterDetectSt_A	7138329	48	0	0
EnterStableSt_A	7138329	46	0	0
PulseIsPulse_A	7138329	46	0	0
StayInStableSt	7138329	4186	0	0
gen_high_level_sva.HighLevelEvent_A	7138329	6518002	0	0
gen_not_sticky_sva.StableStDropOut_A	7138329	28	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	98	0	0
T15	654	2	0	0
T16	23347	0	0	0
T17	24696	0	0	0
T21	0	2	0	0
T23	0	4	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T34	1192	0	0	0
T52	0	2	0	0
T58	1012	0	0	0
T65	504	0	0	0
T87	0	2	0	0
T115	0	4	0	0
T137	0	2	0	0
T150	0	2	0	0
T185	0	2	0	0
T187	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	2875	0	0
T15	654	27	0	0
T16	23347	0	0	0
T17	24696	0	0	0
T21	0	78	0	0
T23	0	148	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T34	1192	0	0	0
T52	0	38	0	0
T58	1012	0	0	0
T65	504	0	0	0
T87	0	74	0	0
T115	0	78	0	0
T137	0	67	0	0
T150	0	58	0	0
T185	0	94	0	0
T187	0	19	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6515533	0	0
T1	20092	19645	0	0
T2	15963	15539	0	0
T4	496	95	0	0
T5	693	292	0	0
T24	449	48	0	0
T25	403	2	0	0
T26	505	104	0	0
T27	406	5	0	0
T28	20119	19678	0	0
T29	405	4	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	2	0	0
T143	0	1	0	0
T158	5579	1	0	0
T161	833	0	0	0
T162	3910	0	0	0
T163	704	0	0	0
T164	28757	0	0	0
T165	7370	0	0	0
T166	6758	0	0	0
T167	426	0	0	0
T168	441	0	0	0
T169	10098	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	4248	0	0
T15	654	38	0	0
T16	23347	0	0	0
T17	24696	0	0	0
T21	0	468	0	0
T23	0	162	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T34	1192	0	0	0
T52	0	24	0	0
T58	1012	0	0	0
T65	504	0	0	0
T87	0	115	0	0
T115	0	22	0	0
T137	0	57	0	0
T150	0	146	0	0
T185	0	472	0	0
T187	0	63	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	46	0	0
T15	654	1	0	0
T16	23347	0	0	0
T17	24696	0	0	0
T21	0	1	0	0
T23	0	2	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T34	1192	0	0	0
T52	0	1	0	0
T58	1012	0	0	0
T65	504	0	0	0
T87	0	1	0	0
T115	0	2	0	0
T137	0	1	0	0
T150	0	1	0	0
T185	0	1	0	0
T187	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6493747	0	0
T1	20092	19645	0	0
T2	15963	15539	0	0
T4	496	95	0	0
T5	693	292	0	0
T24	449	48	0	0
T25	403	2	0	0
T26	505	104	0	0
T27	406	5	0	0
T28	20119	19678	0	0
T29	405	4	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6496076	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	50	0	0
T15	654	1	0	0
T16	23347	0	0	0
T17	24696	0	0	0
T21	0	1	0	0
T23	0	2	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T34	1192	0	0	0
T52	0	1	0	0
T58	1012	0	0	0
T65	504	0	0	0
T87	0	1	0	0
T115	0	2	0	0
T137	0	1	0	0
T150	0	1	0	0
T185	0	1	0	0
T187	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	48	0	0
T15	654	1	0	0
T16	23347	0	0	0
T17	24696	0	0	0
T21	0	1	0	0
T23	0	2	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T34	1192	0	0	0
T52	0	1	0	0
T58	1012	0	0	0
T65	504	0	0	0
T87	0	1	0	0
T115	0	2	0	0
T137	0	1	0	0
T150	0	1	0	0
T185	0	1	0	0
T187	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	46	0	0
T15	654	1	0	0
T16	23347	0	0	0
T17	24696	0	0	0
T21	0	1	0	0
T23	0	2	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T34	1192	0	0	0
T52	0	1	0	0
T58	1012	0	0	0
T65	504	0	0	0
T87	0	1	0	0
T115	0	2	0	0
T137	0	1	0	0
T150	0	1	0	0
T185	0	1	0	0
T187	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	46	0	0
T15	654	1	0	0
T16	23347	0	0	0
T17	24696	0	0	0
T21	0	1	0	0
T23	0	2	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T34	1192	0	0	0
T52	0	1	0	0
T58	1012	0	0	0
T65	504	0	0	0
T87	0	1	0	0
T115	0	2	0	0
T137	0	1	0	0
T150	0	1	0	0
T185	0	1	0	0
T187	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	4186	0	0
T15	654	36	0	0
T16	23347	0	0	0
T17	24696	0	0	0
T21	0	466	0	0
T23	0	160	0	0
T30	7066	0	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T34	1192	0	0	0
T52	0	23	0	0
T58	1012	0	0	0
T65	504	0	0	0
T87	0	114	0	0
T115	0	20	0	0
T137	0	56	0	0
T150	0	145	0	0
T185	0	470	0	0
T187	0	62	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6518002	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	28	0	0
T23	959	2	0	0
T52	0	1	0	0
T79	31265	0	0	0
T87	0	1	0	0
T103	5857	0	0	0
T115	0	2	0	0
T137	0	1	0	0
T138	0	1	0	0
T150	0	1	0	0
T151	0	1	0	0
T159	0	1	0	0
T187	0	1	0	0
T192	404	0	0	0
T193	1959	0	0	0
T194	491	0	0	0
T195	813	0	0	0
T196	1444	0	0	0
T197	408	0	0	0
T198	935	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T24
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T24
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T17,T18,T49

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T17,T18,T49

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T17,T18,T49

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T17
1	0	Covered	T1,T4,T24
1	1	Covered	T17,T18,T49

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T17,T18,T49
0	1	Covered	T188
1	0	Covered	T82

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T17,T18,T49
0	1	Covered	T50,T115,T184
1	0	Covered	T83

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T17,T18,T49
1	-	Covered	T50,T115,T184

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T17,T18,T49
DetectSt	168	Covered	T17,T18,T49
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T17,T18,T49

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T17,T18,T49
DebounceSt->IdleSt	163	Covered	T18,T199,T200
DetectSt->IdleSt	186	Covered	T82,T188
DetectSt->StableSt	191	Covered	T17,T18,T49
IdleSt->DebounceSt	148	Covered	T17,T18,T49
StableSt->IdleSt	206	Covered	T18,T49,T50

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T17,T18,T49
0	1	Covered	T17,T18,T49
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T17,T18,T49
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T17,T18,T49
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T17,T18,T49
DebounceSt	-	0	1	0	-	-	-	Covered	T18,T199,T200
DebounceSt	-	0	0	-	-	-	-	Covered	T17,T18,T49
DetectSt	-	-	-	-	1	-	-	Covered	T82,T188
DetectSt	-	-	-	-	0	1	-	Covered	T17,T18,T49
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T50,T115,T184
StableSt	-	-	-	-	-	-	0	Covered	T17,T18,T49
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7138329	78	0	0
CntIncr_A	7138329	2344	0	0
CntNoWrap_A	7138329	6515553	0	0
DetectStDropOut_A	7138329	1	0	0
DetectedOut_A	7138329	2530	0	0
DetectedPulseOut_A	7138329	35	0	0
DisabledIdleSt_A	7138329	6499515	0	0
DisabledNoDetection_A	7138329	6501839	0	0
EnterDebounceSt_A	7138329	41	0	0
EnterDetectSt_A	7138329	37	0	0
EnterStableSt_A	7138329	35	0	0
PulseIsPulse_A	7138329	35	0	0
StayInStableSt	7138329	2473	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7138329	6065	0	0
gen_low_level_sva.LowLevelEvent_A	7138329	6518002	0	0
gen_not_sticky_sva.StableStDropOut_A	7138329	12	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	78	0	0
T17	24696	2	0	0
T18	32110	5	0	0
T34	1192	0	0	0
T48	2506	0	0	0
T49	0	2	0	0
T50	0	2	0	0
T51	0	2	0	0
T58	1012	0	0	0
T59	489	0	0	0
T65	504	0	0	0
T66	2290	0	0	0
T67	10880	0	0	0
T110	416	0	0	0
T115	0	4	0	0
T137	0	2	0	0
T150	0	2	0	0
T184	0	4	0	0
T187	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	2344	0	0
T17	24696	68	0	0
T18	32110	102	0	0
T34	1192	0	0	0
T48	2506	0	0	0
T49	0	38	0	0
T50	0	47	0	0
T51	0	75	0	0
T58	1012	0	0	0
T59	489	0	0	0
T65	504	0	0	0
T66	2290	0	0	0
T67	10880	0	0	0
T110	416	0	0	0
T115	0	78	0	0
T137	0	67	0	0
T150	0	58	0	0
T184	0	162	0	0
T187	0	19	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6515553	0	0
T1	20092	19645	0	0
T2	15963	15539	0	0
T4	496	95	0	0
T5	693	292	0	0
T24	449	48	0	0
T25	403	2	0	0
T26	505	104	0	0
T27	406	5	0	0
T28	20119	19678	0	0
T29	405	4	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	1	0	0
T83	8235	0	0	0
T140	13054	0	0	0
T188	952	1	0	0
T201	406	0	0	0
T202	6155	0	0	0
T203	523	0	0	0
T204	22243	0	0	0
T205	403	0	0	0
T206	16649	0	0	0
T207	413	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	2530	0	0
T17	24696	75	0	0
T18	32110	125	0	0
T34	1192	0	0	0
T48	2506	0	0	0
T49	0	130	0	0
T50	0	156	0	0
T51	0	246	0	0
T58	1012	0	0	0
T59	489	0	0	0
T65	504	0	0	0
T66	2290	0	0	0
T67	10880	0	0	0
T110	416	0	0	0
T115	0	107	0	0
T137	0	37	0	0
T150	0	89	0	0
T184	0	96	0	0
T187	0	66	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	35	0	0
T17	24696	1	0	0
T18	32110	2	0	0
T34	1192	0	0	0
T48	2506	0	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T58	1012	0	0	0
T59	489	0	0	0
T65	504	0	0	0
T66	2290	0	0	0
T67	10880	0	0	0
T110	416	0	0	0
T115	0	2	0	0
T137	0	1	0	0
T150	0	1	0	0
T184	0	2	0	0
T187	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6499515	0	0
T1	20092	19645	0	0
T2	15963	15539	0	0
T4	496	95	0	0
T5	693	292	0	0
T24	449	48	0	0
T25	403	2	0	0
T26	505	104	0	0
T27	406	5	0	0
T28	20119	19678	0	0
T29	405	4	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6501839	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	41	0	0
T17	24696	1	0	0
T18	32110	3	0	0
T34	1192	0	0	0
T48	2506	0	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T58	1012	0	0	0
T59	489	0	0	0
T65	504	0	0	0
T66	2290	0	0	0
T67	10880	0	0	0
T110	416	0	0	0
T115	0	2	0	0
T137	0	1	0	0
T150	0	1	0	0
T184	0	2	0	0
T187	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	37	0	0
T17	24696	1	0	0
T18	32110	2	0	0
T34	1192	0	0	0
T48	2506	0	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T58	1012	0	0	0
T59	489	0	0	0
T65	504	0	0	0
T66	2290	0	0	0
T67	10880	0	0	0
T110	416	0	0	0
T115	0	2	0	0
T137	0	1	0	0
T150	0	1	0	0
T184	0	2	0	0
T187	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	35	0	0
T17	24696	1	0	0
T18	32110	2	0	0
T34	1192	0	0	0
T48	2506	0	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T58	1012	0	0	0
T59	489	0	0	0
T65	504	0	0	0
T66	2290	0	0	0
T67	10880	0	0	0
T110	416	0	0	0
T115	0	2	0	0
T137	0	1	0	0
T150	0	1	0	0
T184	0	2	0	0
T187	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	35	0	0
T17	24696	1	0	0
T18	32110	2	0	0
T34	1192	0	0	0
T48	2506	0	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T58	1012	0	0	0
T59	489	0	0	0
T65	504	0	0	0
T66	2290	0	0	0
T67	10880	0	0	0
T110	416	0	0	0
T115	0	2	0	0
T137	0	1	0	0
T150	0	1	0	0
T184	0	2	0	0
T187	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	2473	0	0
T17	24696	73	0	0
T18	32110	121	0	0
T34	1192	0	0	0
T48	2506	0	0	0
T49	0	128	0	0
T50	0	155	0	0
T51	0	244	0	0
T58	1012	0	0	0
T59	489	0	0	0
T65	504	0	0	0
T66	2290	0	0	0
T67	10880	0	0	0
T110	416	0	0	0
T115	0	104	0	0
T137	0	35	0	0
T150	0	87	0	0
T184	0	94	0	0
T187	0	64	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6065	0	0
T1	20092	7	0	0
T2	15963	35	0	0
T3	0	14	0	0
T4	496	8	0	0
T5	693	0	0	0
T6	0	10	0	0
T7	0	32	0	0
T24	449	4	0	0
T25	403	0	0	0
T26	505	3	0	0
T27	406	0	0	0
T28	20119	12	0	0
T29	405	0	0	0
T47	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6518002	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	12	0	0
T50	765	1	0	0
T106	34074	0	0	0
T107	9078	0	0	0
T113	3000	0	0	0
T115	0	1	0	0
T142	0	1	0	0
T157	0	2	0	0
T158	0	1	0	0
T159	0	1	0	0
T175	544	0	0	0
T184	0	2	0	0
T189	0	1	0	0
T208	0	1	0	0
T209	0	1	0	0
T210	506	0	0	0
T211	5624	0	0	0
T212	524	0	0	0
T213	620	0	0	0
T214	521	0	0	0