Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T7,T9
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T7,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T7,T9

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T7,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T9
1	0	Covered	T2,T7,T9
1	1	Covered	T2,T7,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T9
0	1	Covered	T30,T31,T69
1	0	Covered	T31,T67,T100

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T9
0	1	Covered	T2,T7,T9
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T7,T9
1	-	Covered	T2,T7,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T7,T9
DetectSt	168	Covered	T2,T7,T9
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T2,T7,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T7,T9
DebounceSt->IdleSt	163	Covered	T82,T83,T234
DetectSt->IdleSt	186	Covered	T30,T31,T67
DetectSt->StableSt	191	Covered	T2,T7,T9
IdleSt->DebounceSt	148	Covered	T2,T7,T9
StableSt->IdleSt	206	Covered	T2,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T7,T9
0	1	Covered	T2,T7,T9
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T9
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T2,T7,T9
IdleSt	0	-	-	-	-	-	-	Covered	T2,T7,T9
DebounceSt	-	1	-	-	-	-	-	Covered	T82,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T7,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T82,T83,T234
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T7,T9
DetectSt	-	-	-	-	1	-	-	Covered	T30,T31,T67
DetectSt	-	-	-	-	0	1	-	Covered	T2,T7,T9
DetectSt	-	-	-	-	0	0	-	Covered	T2,T7,T9
StableSt	-	-	-	-	-	-	1	Covered	T2,T7,T9
StableSt	-	-	-	-	-	-	0	Covered	T2,T7,T9
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7138329	2935	0	0
CntIncr_A	7138329	100042	0	0
CntNoWrap_A	7138329	6512696	0	0
DetectStDropOut_A	7138329	461	0	0
DetectedOut_A	7138329	71679	0	0
DetectedPulseOut_A	7138329	767	0	0
DisabledIdleSt_A	7138329	6055874	0	0
DisabledNoDetection_A	7138329	6058030	0	0
EnterDebounceSt_A	7138329	1473	0	0
EnterDetectSt_A	7138329	1462	0	0
EnterStableSt_A	7138329	767	0	0
PulseIsPulse_A	7138329	767	0	0
StayInStableSt	7138329	70789	0	0
gen_high_event_sva.HighLevelEvent_A	7138329	6518002	0	0
gen_high_level_sva.HighLevelEvent_A	7138329	6518002	0	0
gen_not_sticky_sva.StableStDropOut_A	7138329	644	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	2935	0	0
T2	15963	16	0	0
T3	21356	0	0	0
T6	12993	0	0	0
T7	27514	38	0	0
T8	1009	0	0	0
T9	18082	50	0	0
T10	0	32	0	0
T29	405	0	0	0
T30	0	58	0	0
T31	0	42	0	0
T39	492	0	0	0
T40	495	0	0	0
T47	522	0	0	0
T67	0	12	0	0
T68	0	28	0	0
T69	0	30	0	0
T70	0	24	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	100042	0	0
T2	15963	408	0	0
T3	21356	0	0	0
T6	12993	0	0	0
T7	27514	1501	0	0
T8	1009	0	0	0
T9	18082	1950	0	0
T10	0	912	0	0
T29	405	0	0	0
T30	0	2579	0	0
T31	0	1182	0	0
T39	492	0	0	0
T40	495	0	0	0
T47	522	0	0	0
T67	0	323	0	0
T68	0	1078	0	0
T69	0	792	0	0
T70	0	600	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6512696	0	0
T1	20092	19645	0	0
T2	15963	15523	0	0
T4	496	95	0	0
T5	693	292	0	0
T24	449	48	0	0
T25	403	2	0	0
T26	505	104	0	0
T27	406	5	0	0
T28	20119	19678	0	0
T29	405	4	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	461	0	0
T17	24696	0	0	0
T30	7066	29	0	0
T31	19949	14	0	0
T32	402	0	0	0
T33	523	0	0	0
T34	1192	0	0	0
T58	1012	0	0	0
T59	489	0	0	0
T65	504	0	0	0
T69	0	15	0	0
T99	0	22	0	0
T100	0	13	0	0
T101	0	2	0	0
T102	0	3	0	0
T103	0	19	0	0
T104	0	14	0	0
T107	0	12	0	0
T110	416	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	71679	0	0
T2	15963	440	0	0
T3	21356	0	0	0
T6	12993	0	0	0
T7	27514	2773	0	0
T8	1009	0	0	0
T9	18082	2197	0	0
T10	0	328	0	0
T29	405	0	0	0
T39	492	0	0	0
T40	495	0	0	0
T47	522	0	0	0
T68	0	1591	0	0
T70	0	1013	0	0
T85	0	111	0	0
T131	0	1219	0	0
T235	0	55	0	0
T236	0	1703	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	767	0	0
T2	15963	8	0	0
T3	21356	0	0	0
T6	12993	0	0	0
T7	27514	19	0	0
T8	1009	0	0	0
T9	18082	25	0	0
T10	0	16	0	0
T29	405	0	0	0
T39	492	0	0	0
T40	495	0	0	0
T47	522	0	0	0
T68	0	14	0	0
T70	0	12	0	0
T85	0	6	0	0
T131	0	9	0	0
T235	0	6	0	0
T236	0	15	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6055874	0	0
T1	20092	19645	0	0
T2	15963	11155	0	0
T4	496	95	0	0
T5	693	292	0	0
T24	449	48	0	0
T25	403	2	0	0
T26	505	104	0	0
T27	406	5	0	0
T28	20119	19678	0	0
T29	405	4	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6058030	0	0
T1	20092	19652	0	0
T2	15963	11157	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	1473	0	0
T2	15963	8	0	0
T3	21356	0	0	0
T6	12993	0	0	0
T7	27514	19	0	0
T8	1009	0	0	0
T9	18082	25	0	0
T10	0	16	0	0
T29	405	0	0	0
T30	0	29	0	0
T31	0	21	0	0
T39	492	0	0	0
T40	495	0	0	0
T47	522	0	0	0
T67	0	6	0	0
T68	0	14	0	0
T69	0	15	0	0
T70	0	12	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	1462	0	0
T2	15963	8	0	0
T3	21356	0	0	0
T6	12993	0	0	0
T7	27514	19	0	0
T8	1009	0	0	0
T9	18082	25	0	0
T10	0	16	0	0
T29	405	0	0	0
T30	0	29	0	0
T31	0	21	0	0
T39	492	0	0	0
T40	495	0	0	0
T47	522	0	0	0
T67	0	6	0	0
T68	0	14	0	0
T69	0	15	0	0
T70	0	12	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	767	0	0
T2	15963	8	0	0
T3	21356	0	0	0
T6	12993	0	0	0
T7	27514	19	0	0
T8	1009	0	0	0
T9	18082	25	0	0
T10	0	16	0	0
T29	405	0	0	0
T39	492	0	0	0
T40	495	0	0	0
T47	522	0	0	0
T68	0	14	0	0
T70	0	12	0	0
T85	0	6	0	0
T131	0	9	0	0
T235	0	6	0	0
T236	0	15	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	767	0	0
T2	15963	8	0	0
T3	21356	0	0	0
T6	12993	0	0	0
T7	27514	19	0	0
T8	1009	0	0	0
T9	18082	25	0	0
T10	0	16	0	0
T29	405	0	0	0
T39	492	0	0	0
T40	495	0	0	0
T47	522	0	0	0
T68	0	14	0	0
T70	0	12	0	0
T85	0	6	0	0
T131	0	9	0	0
T235	0	6	0	0
T236	0	15	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	70789	0	0
T2	15963	430	0	0
T3	21356	0	0	0
T6	12993	0	0	0
T7	27514	2749	0	0
T8	1009	0	0	0
T9	18082	2170	0	0
T10	0	312	0	0
T29	405	0	0	0
T39	492	0	0	0
T40	495	0	0	0
T47	522	0	0	0
T68	0	1575	0	0
T70	0	1000	0	0
T85	0	105	0	0
T131	0	1208	0	0
T235	0	49	0	0
T236	0	1684	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6518002	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6518002	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	644	0	0
T2	15963	6	0	0
T3	21356	0	0	0
T6	12993	0	0	0
T7	27514	14	0	0
T8	1009	0	0	0
T9	18082	23	0	0
T10	0	16	0	0
T29	405	0	0	0
T39	492	0	0	0
T40	495	0	0	0
T47	522	0	0	0
T68	0	12	0	0
T70	0	11	0	0
T85	0	6	0	0
T131	0	7	0	0
T235	0	6	0	0
T236	0	11	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T28,T2
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T28,T2
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T28,T2,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T28,T2,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T28,T2,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T28,T2
1	0	Covered	T1,T28,T2
1	1	Covered	T28,T2,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T28,T2,T3
0	1	Covered	T28,T6,T96
1	0	Covered	T82,T83

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T7
0	1	Covered	T3,T7,T10
1	0	Covered	T83

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T7
1	-	Covered	T3,T7,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T28,T2,T3
DetectSt	168	Covered	T28,T2,T3
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T2,T3,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T28,T2,T3
DebounceSt->IdleSt	163	Covered	T28,T7,T10
DetectSt->IdleSt	186	Covered	T28,T6,T96
DetectSt->StableSt	191	Covered	T2,T3,T7
IdleSt->DebounceSt	148	Covered	T28,T2,T3
StableSt->IdleSt	206	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T28,T2,T3
0	1	Covered	T28,T2,T3
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T28,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T28,T2,T3
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T82,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T28,T2,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T28,T7,T10
DebounceSt	-	0	0	-	-	-	-	Covered	T28,T2,T3
DetectSt	-	-	-	-	1	-	-	Covered	T28,T6,T96
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T7
DetectSt	-	-	-	-	0	0	-	Covered	T28,T2,T3
StableSt	-	-	-	-	-	-	1	Covered	T3,T7,T10
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7138329	1056	0	0
CntIncr_A	7138329	50281	0	0
CntNoWrap_A	7138329	6514575	0	0
DetectStDropOut_A	7138329	80	0	0
DetectedOut_A	7138329	16481	0	0
DetectedPulseOut_A	7138329	409	0	0
DisabledIdleSt_A	7138329	6141260	0	0
DisabledNoDetection_A	7138329	6142827	0	0
EnterDebounceSt_A	7138329	564	0	0
EnterDetectSt_A	7138329	493	0	0
EnterStableSt_A	7138329	409	0	0
PulseIsPulse_A	7138329	409	0	0
StayInStableSt	7138329	16025	0	0
gen_high_level_sva.HighLevelEvent_A	7138329	6518002	0	0
gen_not_sticky_sva.StableStDropOut_A	7138329	356	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	1056	0	0
T2	15963	2	0	0
T3	21356	10	0	0
T6	12993	6	0	0
T7	27514	8	0	0
T8	1009	0	0	0
T9	0	2	0	0
T10	0	3	0	0
T12	0	8	0	0
T14	0	4	0	0
T16	0	12	0	0
T28	20119	23	0	0
T29	405	0	0	0
T39	492	0	0	0
T40	495	0	0	0
T47	522	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	50281	0	0
T2	15963	76	0	0
T3	21356	1210	0	0
T6	12993	268	0	0
T7	27514	276	0	0
T8	1009	0	0	0
T9	0	92	0	0
T10	0	122	0	0
T12	0	600	0	0
T14	0	218	0	0
T16	0	936	0	0
T28	20119	1261	0	0
T29	405	0	0	0
T39	492	0	0	0
T40	495	0	0	0
T47	522	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6514575	0	0
T1	20092	19645	0	0
T2	15963	15537	0	0
T4	496	95	0	0
T5	693	292	0	0
T24	449	48	0	0
T25	403	2	0	0
T26	505	104	0	0
T27	406	5	0	0
T28	20119	19655	0	0
T29	405	4	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	80	0	0
T2	15963	0	0	0
T3	21356	0	0	0
T6	12993	3	0	0
T7	27514	0	0	0
T8	1009	0	0	0
T28	20119	11	0	0
T29	405	0	0	0
T39	492	0	0	0
T40	495	0	0	0
T47	522	0	0	0
T78	0	8	0	0
T80	0	4	0	0
T96	0	5	0	0
T98	0	1	0	0
T105	0	5	0	0
T106	0	6	0	0
T108	0	3	0	0
T109	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	16481	0	0
T2	15963	16	0	0
T3	21356	149	0	0
T6	12993	0	0	0
T7	27514	208	0	0
T8	1009	0	0	0
T9	18082	58	0	0
T10	0	49	0	0
T12	0	30	0	0
T14	0	97	0	0
T16	0	66	0	0
T17	0	448	0	0
T18	0	9	0	0
T29	405	0	0	0
T39	492	0	0	0
T40	495	0	0	0
T47	522	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	409	0	0
T2	15963	1	0	0
T3	21356	5	0	0
T6	12993	0	0	0
T7	27514	3	0	0
T8	1009	0	0	0
T9	18082	1	0	0
T10	0	1	0	0
T12	0	4	0	0
T14	0	2	0	0
T16	0	6	0	0
T17	0	6	0	0
T18	0	1	0	0
T29	405	0	0	0
T39	492	0	0	0
T40	495	0	0	0
T47	522	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6141260	0	0
T1	20092	14103	0	0
T2	15963	15101	0	0
T4	496	95	0	0
T5	693	292	0	0
T24	449	48	0	0
T25	403	2	0	0
T26	505	104	0	0
T27	406	5	0	0
T28	20119	16117	0	0
T29	405	4	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6142827	0	0
T1	20092	14103	0	0
T2	15963	15104	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	16117	0	0
T29	405	5	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	564	0	0
T2	15963	1	0	0
T3	21356	5	0	0
T6	12993	3	0	0
T7	27514	5	0	0
T8	1009	0	0	0
T9	0	1	0	0
T10	0	2	0	0
T12	0	4	0	0
T14	0	2	0	0
T16	0	6	0	0
T28	20119	12	0	0
T29	405	0	0	0
T39	492	0	0	0
T40	495	0	0	0
T47	522	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	493	0	0
T2	15963	1	0	0
T3	21356	5	0	0
T6	12993	3	0	0
T7	27514	3	0	0
T8	1009	0	0	0
T9	0	1	0	0
T10	0	1	0	0
T12	0	4	0	0
T14	0	2	0	0
T16	0	6	0	0
T28	20119	11	0	0
T29	405	0	0	0
T39	492	0	0	0
T40	495	0	0	0
T47	522	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	409	0	0
T2	15963	1	0	0
T3	21356	5	0	0
T6	12993	0	0	0
T7	27514	3	0	0
T8	1009	0	0	0
T9	18082	1	0	0
T10	0	1	0	0
T12	0	4	0	0
T14	0	2	0	0
T16	0	6	0	0
T17	0	6	0	0
T18	0	1	0	0
T29	405	0	0	0
T39	492	0	0	0
T40	495	0	0	0
T47	522	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	409	0	0
T2	15963	1	0	0
T3	21356	5	0	0
T6	12993	0	0	0
T7	27514	3	0	0
T8	1009	0	0	0
T9	18082	1	0	0
T10	0	1	0	0
T12	0	4	0	0
T14	0	2	0	0
T16	0	6	0	0
T17	0	6	0	0
T18	0	1	0	0
T29	405	0	0	0
T39	492	0	0	0
T40	495	0	0	0
T47	522	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	16025	0	0
T2	15963	14	0	0
T3	21356	144	0	0
T6	12993	0	0	0
T7	27514	204	0	0
T8	1009	0	0	0
T9	18082	56	0	0
T10	0	48	0	0
T12	0	26	0	0
T14	0	95	0	0
T16	0	60	0	0
T17	0	442	0	0
T18	0	8	0	0
T29	405	0	0	0
T39	492	0	0	0
T40	495	0	0	0
T47	522	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6518002	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	356	0	0
T3	21356	5	0	0
T6	12993	0	0	0
T7	27514	2	0	0
T8	1009	0	0	0
T9	18082	0	0	0
T10	9156	1	0	0
T12	0	4	0	0
T14	0	2	0	0
T16	0	6	0	0
T17	0	6	0	0
T18	0	1	0	0
T21	0	6	0	0
T39	492	0	0	0
T40	495	0	0	0
T41	502	0	0	0
T47	522	0	0	0
T68	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T7,T9
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T7,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T7,T9

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T7,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T9
1	0	Covered	T2,T7,T9
1	1	Covered	T2,T7,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T9
0	1	Covered	T30,T67,T69
1	0	Covered	T31,T67,T103

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T9
0	1	Covered	T2,T7,T9
1	0	Covered	T83

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T7,T9
1	-	Covered	T2,T7,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T7,T9
DetectSt	168	Covered	T2,T7,T9
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T2,T7,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T7,T9
DebounceSt->IdleSt	163	Covered	T82,T83,T234
DetectSt->IdleSt	186	Covered	T30,T31,T67
DetectSt->StableSt	191	Covered	T2,T7,T9
IdleSt->DebounceSt	148	Covered	T2,T7,T9
StableSt->IdleSt	206	Covered	T2,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T7,T9
0	1	Covered	T2,T7,T9
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T9
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T2,T7,T9
IdleSt	0	-	-	-	-	-	-	Covered	T2,T7,T9
DebounceSt	-	1	-	-	-	-	-	Covered	T82,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T7,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T82,T83,T234
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T7,T9
DetectSt	-	-	-	-	1	-	-	Covered	T30,T31,T67
DetectSt	-	-	-	-	0	1	-	Covered	T2,T7,T9
DetectSt	-	-	-	-	0	0	-	Covered	T2,T7,T9
StableSt	-	-	-	-	-	-	1	Covered	T2,T7,T9
StableSt	-	-	-	-	-	-	0	Covered	T2,T7,T9
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7138329	2947	0	0
CntIncr_A	7138329	98753	0	0
CntNoWrap_A	7138329	6512684	0	0
DetectStDropOut_A	7138329	449	0	0
DetectedOut_A	7138329	70324	0	0
DetectedPulseOut_A	7138329	775	0	0
DisabledIdleSt_A	7138329	6051984	0	0
DisabledNoDetection_A	7138329	6054147	0	0
EnterDebounceSt_A	7138329	1477	0	0
EnterDetectSt_A	7138329	1471	0	0
EnterStableSt_A	7138329	775	0	0
PulseIsPulse_A	7138329	775	0	0
StayInStableSt	7138329	69435	0	0
gen_high_event_sva.HighLevelEvent_A	7138329	6518002	0	0
gen_high_level_sva.HighLevelEvent_A	7138329	6518002	0	0
gen_not_sticky_sva.StableStDropOut_A	7138329	660	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	2947	0	0
T2	15963	22	0	0
T3	21356	0	0	0
T6	12993	0	0	0
T7	27514	28	0	0
T8	1009	0	0	0
T9	18082	16	0	0
T10	0	16	0	0
T29	405	0	0	0
T30	0	52	0	0
T31	0	24	0	0
T39	492	0	0	0
T40	495	0	0	0
T47	522	0	0	0
T67	0	54	0	0
T68	0	42	0	0
T69	0	6	0	0
T70	0	38	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	98753	0	0
T2	15963	781	0	0
T3	21356	0	0	0
T6	12993	0	0	0
T7	27514	1148	0	0
T8	1009	0	0	0
T9	18082	744	0	0
T10	0	320	0	0
T29	405	0	0	0
T30	0	2314	0	0
T31	0	680	0	0
T39	492	0	0	0
T40	495	0	0	0
T47	522	0	0	0
T67	0	1443	0	0
T68	0	1533	0	0
T69	0	158	0	0
T70	0	1178	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6512684	0	0
T1	20092	19645	0	0
T2	15963	15517	0	0
T4	496	95	0	0
T5	693	292	0	0
T24	449	48	0	0
T25	403	2	0	0
T26	505	104	0	0
T27	406	5	0	0
T28	20119	19678	0	0
T29	405	4	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	449	0	0
T17	24696	0	0	0
T30	7066	26	0	0
T31	19949	0	0	0
T32	402	0	0	0
T33	523	0	0	0
T34	1192	0	0	0
T58	1012	0	0	0
T59	489	0	0	0
T65	504	0	0	0
T67	0	20	0	0
T69	0	3	0	0
T99	0	17	0	0
T101	0	25	0	0
T103	0	27	0	0
T104	0	6	0	0
T110	416	0	0	0
T211	0	9	0	0
T236	0	12	0	0
T237	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	70324	0	0
T2	15963	898	0	0
T3	21356	0	0	0
T6	12993	0	0	0
T7	27514	1311	0	0
T8	1009	0	0	0
T9	18082	82	0	0
T10	0	1460	0	0
T29	405	0	0	0
T39	492	0	0	0
T40	495	0	0	0
T47	522	0	0	0
T68	0	2709	0	0
T70	0	1592	0	0
T85	0	1628	0	0
T100	0	505	0	0
T131	0	227	0	0
T235	0	312	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	775	0	0
T2	15963	11	0	0
T3	21356	0	0	0
T6	12993	0	0	0
T7	27514	14	0	0
T8	1009	0	0	0
T9	18082	8	0	0
T10	0	8	0	0
T29	405	0	0	0
T39	492	0	0	0
T40	495	0	0	0
T47	522	0	0	0
T68	0	21	0	0
T70	0	19	0	0
T85	0	13	0	0
T100	0	6	0	0
T131	0	6	0	0
T235	0	11	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6051984	0	0
T1	20092	19645	0	0
T2	15963	10565	0	0
T4	496	95	0	0
T5	693	292	0	0
T24	449	48	0	0
T25	403	2	0	0
T26	505	104	0	0
T27	406	5	0	0
T28	20119	19678	0	0
T29	405	4	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6054147	0	0
T1	20092	19652	0	0
T2	15963	10565	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	1477	0	0
T2	15963	11	0	0
T3	21356	0	0	0
T6	12993	0	0	0
T7	27514	14	0	0
T8	1009	0	0	0
T9	18082	8	0	0
T10	0	8	0	0
T29	405	0	0	0
T30	0	26	0	0
T31	0	12	0	0
T39	492	0	0	0
T40	495	0	0	0
T47	522	0	0	0
T67	0	27	0	0
T68	0	21	0	0
T69	0	3	0	0
T70	0	19	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	1471	0	0
T2	15963	11	0	0
T3	21356	0	0	0
T6	12993	0	0	0
T7	27514	14	0	0
T8	1009	0	0	0
T9	18082	8	0	0
T10	0	8	0	0
T29	405	0	0	0
T30	0	26	0	0
T31	0	12	0	0
T39	492	0	0	0
T40	495	0	0	0
T47	522	0	0	0
T67	0	27	0	0
T68	0	21	0	0
T69	0	3	0	0
T70	0	19	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	775	0	0
T2	15963	11	0	0
T3	21356	0	0	0
T6	12993	0	0	0
T7	27514	14	0	0
T8	1009	0	0	0
T9	18082	8	0	0
T10	0	8	0	0
T29	405	0	0	0
T39	492	0	0	0
T40	495	0	0	0
T47	522	0	0	0
T68	0	21	0	0
T70	0	19	0	0
T85	0	13	0	0
T100	0	6	0	0
T131	0	6	0	0
T235	0	11	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	775	0	0
T2	15963	11	0	0
T3	21356	0	0	0
T6	12993	0	0	0
T7	27514	14	0	0
T8	1009	0	0	0
T9	18082	8	0	0
T10	0	8	0	0
T29	405	0	0	0
T39	492	0	0	0
T40	495	0	0	0
T47	522	0	0	0
T68	0	21	0	0
T70	0	19	0	0
T85	0	13	0	0
T100	0	6	0	0
T131	0	6	0	0
T235	0	11	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	69435	0	0
T2	15963	883	0	0
T3	21356	0	0	0
T6	12993	0	0	0
T7	27514	1293	0	0
T8	1009	0	0	0
T9	18082	74	0	0
T10	0	1451	0	0
T29	405	0	0	0
T39	492	0	0	0
T40	495	0	0	0
T47	522	0	0	0
T68	0	2686	0	0
T70	0	1569	0	0
T85	0	1614	0	0
T100	0	496	0	0
T131	0	220	0	0
T235	0	301	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6518002	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6518002	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	660	0	0
T2	15963	7	0	0
T3	21356	0	0	0
T6	12993	0	0	0
T7	27514	10	0	0
T8	1009	0	0	0
T9	18082	8	0	0
T10	0	7	0	0
T29	405	0	0	0
T39	492	0	0	0
T40	495	0	0	0
T47	522	0	0	0
T68	0	19	0	0
T70	0	15	0	0
T85	0	12	0	0
T100	0	3	0	0
T131	0	5	0	0
T235	0	11	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T28,T2
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T28,T2
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T28,T2

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T28,T2

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T28,T2

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T28,T2
1	0	Covered	T1,T28,T2
1	1	Covered	T1,T28,T2

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T28,T2
0	1	Covered	T97,T238,T80
1	0	Covered	T82,T83

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T28,T2
0	1	Covered	T1,T28,T2
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T28,T2
1	-	Covered	T1,T28,T2

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T28,T2
DetectSt	168	Covered	T1,T28,T2
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T28,T2

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T28,T2
DebounceSt->IdleSt	163	Covered	T28,T16,T17
DetectSt->IdleSt	186	Covered	T97,T238,T80
DetectSt->StableSt	191	Covered	T1,T28,T2
IdleSt->DebounceSt	148	Covered	T1,T28,T2
StableSt->IdleSt	206	Covered	T1,T28,T2

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T28,T2
0	1	Covered	T1,T28,T2
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T28,T2
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T28,T2
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T82,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T28,T2
DebounceSt	-	0	1	0	-	-	-	Covered	T28,T16,T17
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T28,T2
DetectSt	-	-	-	-	1	-	-	Covered	T97,T238,T80
DetectSt	-	-	-	-	0	1	-	Covered	T1,T28,T2
DetectSt	-	-	-	-	0	0	-	Covered	T1,T28,T2
StableSt	-	-	-	-	-	-	1	Covered	T1,T28,T2
StableSt	-	-	-	-	-	-	0	Covered	T1,T28,T2
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7138329	928	0	0
CntIncr_A	7138329	47306	0	0
CntNoWrap_A	7138329	6514703	0	0
DetectStDropOut_A	7138329	67	0	0
DetectedOut_A	7138329	16052	0	0
DetectedPulseOut_A	7138329	370	0	0
DisabledIdleSt_A	7138329	6149635	0	0
DisabledNoDetection_A	7138329	6151270	0	0
EnterDebounceSt_A	7138329	489	0	0
EnterDetectSt_A	7138329	441	0	0
EnterStableSt_A	7138329	370	0	0
PulseIsPulse_A	7138329	370	0	0
StayInStableSt	7138329	15651	0	0
gen_high_level_sva.HighLevelEvent_A	7138329	6518002	0	0
gen_not_sticky_sva.StableStDropOut_A	7138329	338	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	928	0	0
T1	20092	2	0	0
T2	15963	6	0	0
T3	0	12	0	0
T4	496	0	0	0
T5	693	0	0	0
T6	0	4	0	0
T7	0	8	0	0
T10	0	2	0	0
T12	0	8	0	0
T14	0	2	0	0
T16	0	11	0	0
T24	449	0	0	0
T25	403	0	0	0
T26	505	0	0	0
T27	406	0	0	0
T28	20119	13	0	0
T29	405	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	47306	0	0
T1	20092	132	0	0
T2	15963	159	0	0
T3	0	1584	0	0
T4	496	0	0	0
T5	693	0	0	0
T6	0	106	0	0
T7	0	368	0	0
T10	0	53	0	0
T12	0	588	0	0
T14	0	85	0	0
T16	0	660	0	0
T24	449	0	0	0
T25	403	0	0	0
T26	505	0	0	0
T27	406	0	0	0
T28	20119	666	0	0
T29	405	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6514703	0	0
T1	20092	19643	0	0
T2	15963	15533	0	0
T4	496	95	0	0
T5	693	292	0	0
T24	449	48	0	0
T25	403	2	0	0
T26	505	104	0	0
T27	406	5	0	0
T28	20119	19665	0	0
T29	405	4	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	67	0	0
T22	3714	0	0	0
T35	1426	0	0	0
T56	23755	0	0	0
T57	646	0	0	0
T80	0	11	0	0
T97	20603	5	0	0
T98	12932	0	0	0
T108	0	5	0	0
T171	0	6	0	0
T216	0	7	0	0
T238	0	8	0	0
T239	0	1	0	0
T240	0	4	0	0
T241	0	3	0	0
T242	0	4	0	0
T243	411	0	0	0
T244	417	0	0	0
T245	489	0	0	0
T246	21249	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	16052	0	0
T1	20092	79	0	0
T2	15963	117	0	0
T3	0	48	0	0
T4	496	0	0	0
T5	693	0	0	0
T6	0	72	0	0
T7	0	159	0	0
T10	0	89	0	0
T12	0	42	0	0
T14	0	72	0	0
T16	0	227	0	0
T24	449	0	0	0
T25	403	0	0	0
T26	505	0	0	0
T27	406	0	0	0
T28	20119	55	0	0
T29	405	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	370	0	0
T1	20092	1	0	0
T2	15963	3	0	0
T3	0	6	0	0
T4	496	0	0	0
T5	693	0	0	0
T6	0	2	0	0
T7	0	4	0	0
T10	0	1	0	0
T12	0	4	0	0
T14	0	1	0	0
T16	0	4	0	0
T24	449	0	0	0
T25	403	0	0	0
T26	505	0	0	0
T27	406	0	0	0
T28	20119	6	0	0
T29	405	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6149635	0	0
T1	20092	14103	0	0
T2	15963	14645	0	0
T4	496	95	0	0
T5	693	292	0	0
T24	449	48	0	0
T25	403	2	0	0
T26	505	104	0	0
T27	406	5	0	0
T28	20119	16117	0	0
T29	405	4	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6151270	0	0
T1	20092	14103	0	0
T2	15963	14646	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	16117	0	0
T29	405	5	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	489	0	0
T1	20092	1	0	0
T2	15963	3	0	0
T3	0	6	0	0
T4	496	0	0	0
T5	693	0	0	0
T6	0	2	0	0
T7	0	4	0	0
T10	0	1	0	0
T12	0	4	0	0
T14	0	1	0	0
T16	0	7	0	0
T24	449	0	0	0
T25	403	0	0	0
T26	505	0	0	0
T27	406	0	0	0
T28	20119	7	0	0
T29	405	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	441	0	0
T1	20092	1	0	0
T2	15963	3	0	0
T3	0	6	0	0
T4	496	0	0	0
T5	693	0	0	0
T6	0	2	0	0
T7	0	4	0	0
T10	0	1	0	0
T12	0	4	0	0
T14	0	1	0	0
T16	0	4	0	0
T24	449	0	0	0
T25	403	0	0	0
T26	505	0	0	0
T27	406	0	0	0
T28	20119	6	0	0
T29	405	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	370	0	0
T1	20092	1	0	0
T2	15963	3	0	0
T3	0	6	0	0
T4	496	0	0	0
T5	693	0	0	0
T6	0	2	0	0
T7	0	4	0	0
T10	0	1	0	0
T12	0	4	0	0
T14	0	1	0	0
T16	0	4	0	0
T24	449	0	0	0
T25	403	0	0	0
T26	505	0	0	0
T27	406	0	0	0
T28	20119	6	0	0
T29	405	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	370	0	0
T1	20092	1	0	0
T2	15963	3	0	0
T3	0	6	0	0
T4	496	0	0	0
T5	693	0	0	0
T6	0	2	0	0
T7	0	4	0	0
T10	0	1	0	0
T12	0	4	0	0
T14	0	1	0	0
T16	0	4	0	0
T24	449	0	0	0
T25	403	0	0	0
T26	505	0	0	0
T27	406	0	0	0
T28	20119	6	0	0
T29	405	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	15651	0	0
T1	20092	78	0	0
T2	15963	114	0	0
T3	0	42	0	0
T4	496	0	0	0
T5	693	0	0	0
T6	0	70	0	0
T7	0	155	0	0
T10	0	88	0	0
T12	0	38	0	0
T14	0	71	0	0
T16	0	223	0	0
T24	449	0	0	0
T25	403	0	0	0
T26	505	0	0	0
T27	406	0	0	0
T28	20119	49	0	0
T29	405	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6518002	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	338	0	0
T1	20092	1	0	0
T2	15963	3	0	0
T3	0	6	0	0
T4	496	0	0	0
T5	693	0	0	0
T6	0	2	0	0
T7	0	4	0	0
T10	0	1	0	0
T12	0	4	0	0
T14	0	1	0	0
T16	0	4	0	0
T24	449	0	0	0
T25	403	0	0	0
T26	505	0	0	0
T27	406	0	0	0
T28	20119	6	0	0
T29	405	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T7,T9
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T7,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T7,T9

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T7,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T9
1	0	Covered	T2,T7,T9
1	1	Covered	T2,T7,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T9
0	1	Covered	T30,T31,T69
1	0	Covered	T10,T31,T100

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T9
0	1	Covered	T2,T7,T9
1	0	Covered	T85,T86,T82

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T7,T9
1	-	Covered	T2,T7,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T7,T9
DetectSt	168	Covered	T2,T7,T9
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T2,T7,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T7,T9
DebounceSt->IdleSt	163	Covered	T82,T83,T234
DetectSt->IdleSt	186	Covered	T10,T30,T31
DetectSt->StableSt	191	Covered	T2,T7,T9
IdleSt->DebounceSt	148	Covered	T2,T7,T9
StableSt->IdleSt	206	Covered	T2,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T7,T9
0	1	Covered	T2,T7,T9
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T9
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T2,T7,T9
IdleSt	0	-	-	-	-	-	-	Covered	T2,T7,T9
DebounceSt	-	1	-	-	-	-	-	Covered	T82,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T7,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T82,T83,T234
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T7,T9
DetectSt	-	-	-	-	1	-	-	Covered	T10,T30,T31
DetectSt	-	-	-	-	0	1	-	Covered	T2,T7,T9
DetectSt	-	-	-	-	0	0	-	Covered	T2,T7,T9
StableSt	-	-	-	-	-	-	1	Covered	T2,T7,T9
StableSt	-	-	-	-	-	-	0	Covered	T2,T7,T9
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7138329	3312	0	0
CntIncr_A	7138329	110764	0	0
CntNoWrap_A	7138329	6512319	0	0
DetectStDropOut_A	7138329	482	0	0
DetectedOut_A	7138329	87015	0	0
DetectedPulseOut_A	7138329	940	0	0
DisabledIdleSt_A	7138329	6043757	0	0
DisabledNoDetection_A	7138329	6045897	0	0
EnterDebounceSt_A	7138329	1664	0	0
EnterDetectSt_A	7138329	1649	0	0
EnterStableSt_A	7138329	940	0	0
PulseIsPulse_A	7138329	940	0	0
StayInStableSt	7138329	85938	0	0
gen_high_event_sva.HighLevelEvent_A	7138329	6518002	0	0
gen_high_level_sva.HighLevelEvent_A	7138329	6518002	0	0
gen_not_sticky_sva.StableStDropOut_A	7138329	788	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	3312	0	0
T2	15963	22	0	0
T3	21356	0	0	0
T6	12993	0	0	0
T7	27514	62	0	0
T8	1009	0	0	0
T9	18082	58	0	0
T10	0	32	0	0
T29	405	0	0	0
T30	0	52	0	0
T31	0	52	0	0
T39	492	0	0	0
T40	495	0	0	0
T47	522	0	0	0
T67	0	20	0	0
T68	0	58	0	0
T69	0	18	0	0
T70	0	38	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	110764	0	0
T2	15963	451	0	0
T3	21356	0	0	0
T6	12993	0	0	0
T7	27514	2387	0	0
T8	1009	0	0	0
T9	18082	2320	0	0
T10	0	922	0	0
T29	405	0	0	0
T30	0	2315	0	0
T31	0	1470	0	0
T39	492	0	0	0
T40	495	0	0	0
T47	522	0	0	0
T67	0	470	0	0
T68	0	2117	0	0
T69	0	473	0	0
T70	0	1197	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6512319	0	0
T1	20092	19645	0	0
T2	15963	15517	0	0
T4	496	95	0	0
T5	693	292	0	0
T24	449	48	0	0
T25	403	2	0	0
T26	505	104	0	0
T27	406	5	0	0
T28	20119	19678	0	0
T29	405	4	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	482	0	0
T17	24696	0	0	0
T30	7066	26	0	0
T31	19949	14	0	0
T32	402	0	0	0
T33	523	0	0	0
T34	1192	0	0	0
T58	1012	0	0	0
T59	489	0	0	0
T65	504	0	0	0
T69	0	9	0	0
T86	0	17	0	0
T99	0	10	0	0
T101	0	25	0	0
T102	0	7	0	0
T103	0	24	0	0
T104	0	14	0	0
T110	416	0	0	0
T211	0	26	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	87015	0	0
T2	15963	1228	0	0
T3	21356	0	0	0
T6	12993	0	0	0
T7	27514	3409	0	0
T8	1009	0	0	0
T9	18082	1645	0	0
T29	405	0	0	0
T39	492	0	0	0
T40	495	0	0	0
T47	522	0	0	0
T67	0	1358	0	0
T68	0	3383	0	0
T70	0	1573	0	0
T85	0	533	0	0
T131	0	2378	0	0
T235	0	2575	0	0
T236	0	1556	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	940	0	0
T2	15963	11	0	0
T3	21356	0	0	0
T6	12993	0	0	0
T7	27514	31	0	0
T8	1009	0	0	0
T9	18082	29	0	0
T29	405	0	0	0
T39	492	0	0	0
T40	495	0	0	0
T47	522	0	0	0
T67	0	10	0	0
T68	0	29	0	0
T70	0	19	0	0
T85	0	13	0	0
T131	0	24	0	0
T235	0	22	0	0
T236	0	15	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6043757	0	0
T1	20092	19645	0	0
T2	15963	10565	0	0
T4	496	95	0	0
T5	693	292	0	0
T24	449	48	0	0
T25	403	2	0	0
T26	505	104	0	0
T27	406	5	0	0
T28	20119	19678	0	0
T29	405	4	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6045897	0	0
T1	20092	19652	0	0
T2	15963	10565	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	1664	0	0
T2	15963	11	0	0
T3	21356	0	0	0
T6	12993	0	0	0
T7	27514	31	0	0
T8	1009	0	0	0
T9	18082	29	0	0
T10	0	16	0	0
T29	405	0	0	0
T30	0	26	0	0
T31	0	26	0	0
T39	492	0	0	0
T40	495	0	0	0
T47	522	0	0	0
T67	0	10	0	0
T68	0	29	0	0
T69	0	9	0	0
T70	0	19	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	1649	0	0
T2	15963	11	0	0
T3	21356	0	0	0
T6	12993	0	0	0
T7	27514	31	0	0
T8	1009	0	0	0
T9	18082	29	0	0
T10	0	16	0	0
T29	405	0	0	0
T30	0	26	0	0
T31	0	26	0	0
T39	492	0	0	0
T40	495	0	0	0
T47	522	0	0	0
T67	0	10	0	0
T68	0	29	0	0
T69	0	9	0	0
T70	0	19	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	940	0	0
T2	15963	11	0	0
T3	21356	0	0	0
T6	12993	0	0	0
T7	27514	31	0	0
T8	1009	0	0	0
T9	18082	29	0	0
T29	405	0	0	0
T39	492	0	0	0
T40	495	0	0	0
T47	522	0	0	0
T67	0	10	0	0
T68	0	29	0	0
T70	0	19	0	0
T85	0	13	0	0
T131	0	24	0	0
T235	0	22	0	0
T236	0	15	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	940	0	0
T2	15963	11	0	0
T3	21356	0	0	0
T6	12993	0	0	0
T7	27514	31	0	0
T8	1009	0	0	0
T9	18082	29	0	0
T29	405	0	0	0
T39	492	0	0	0
T40	495	0	0	0
T47	522	0	0	0
T67	0	10	0	0
T68	0	29	0	0
T70	0	19	0	0
T85	0	13	0	0
T131	0	24	0	0
T235	0	22	0	0
T236	0	15	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	85938	0	0
T2	15963	1213	0	0
T3	21356	0	0	0
T6	12993	0	0	0
T7	27514	3373	0	0
T8	1009	0	0	0
T9	18082	1613	0	0
T29	405	0	0	0
T39	492	0	0	0
T40	495	0	0	0
T47	522	0	0	0
T67	0	1347	0	0
T68	0	3350	0	0
T70	0	1550	0	0
T85	0	520	0	0
T131	0	2350	0	0
T235	0	2550	0	0
T236	0	1539	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6518002	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6518002	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	788	0	0
T2	15963	7	0	0
T3	21356	0	0	0
T6	12993	0	0	0
T7	27514	26	0	0
T8	1009	0	0	0
T9	18082	26	0	0
T29	405	0	0	0
T39	492	0	0	0
T40	495	0	0	0
T47	522	0	0	0
T67	0	9	0	0
T68	0	25	0	0
T70	0	15	0	0
T85	0	3	0	0
T131	0	20	0	0
T235	0	19	0	0
T236	0	13	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T28,T2
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T28,T2
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T28,T2

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T28,T2

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T28,T2

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T28,T2
1	0	Covered	T1,T28,T2
1	1	Covered	T1,T28,T2

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T28,T2
0	1	Covered	T6,T14,T18
1	0	Covered	T82,T83

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T28,T2
0	1	Covered	T1,T28,T2
1	0	Covered	T83,T84

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T28,T2
1	-	Covered	T1,T28,T2

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T28,T2
DetectSt	168	Covered	T1,T28,T2
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T28,T2

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T28,T2
DebounceSt->IdleSt	163	Covered	T28,T3,T7
DetectSt->IdleSt	186	Covered	T6,T14,T18
DetectSt->StableSt	191	Covered	T1,T28,T2
IdleSt->DebounceSt	148	Covered	T1,T28,T2
StableSt->IdleSt	206	Covered	T1,T28,T2

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T28,T2
0	1	Covered	T1,T28,T2
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T28,T2
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T28,T2
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T82,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T28,T2
DebounceSt	-	0	1	0	-	-	-	Covered	T28,T3,T7
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T28,T2
DetectSt	-	-	-	-	1	-	-	Covered	T6,T14,T18
DetectSt	-	-	-	-	0	1	-	Covered	T1,T28,T2
DetectSt	-	-	-	-	0	0	-	Covered	T1,T28,T2
StableSt	-	-	-	-	-	-	1	Covered	T1,T28,T2
StableSt	-	-	-	-	-	-	0	Covered	T1,T28,T2
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7138329	944	0	0
CntIncr_A	7138329	48666	0	0
CntNoWrap_A	7138329	6514687	0	0
DetectStDropOut_A	7138329	48	0	0
DetectedOut_A	7138329	16840	0	0
DetectedPulseOut_A	7138329	402	0	0
DisabledIdleSt_A	7138329	6138601	0	0
DisabledNoDetection_A	7138329	6140227	0	0
EnterDebounceSt_A	7138329	492	0	0
EnterDetectSt_A	7138329	453	0	0
EnterStableSt_A	7138329	402	0	0
PulseIsPulse_A	7138329	402	0	0
StayInStableSt	7138329	16393	0	0
gen_high_level_sva.HighLevelEvent_A	7138329	6518002	0	0
gen_not_sticky_sva.StableStDropOut_A	7138329	351	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	944	0	0
T1	20092	2	0	0
T2	15963	6	0	0
T3	0	6	0	0
T4	496	0	0	0
T5	693	0	0	0
T6	0	2	0	0
T7	0	11	0	0
T9	0	6	0	0
T12	0	14	0	0
T14	0	6	0	0
T17	0	8	0	0
T24	449	0	0	0
T25	403	0	0	0
T26	505	0	0	0
T27	406	0	0	0
T28	20119	16	0	0
T29	405	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	48666	0	0
T1	20092	205	0	0
T2	15963	111	0	0
T3	0	826	0	0
T4	496	0	0	0
T5	693	0	0	0
T6	0	89	0	0
T7	0	425	0	0
T9	0	252	0	0
T12	0	730	0	0
T14	0	500	0	0
T17	0	536	0	0
T24	449	0	0	0
T25	403	0	0	0
T26	505	0	0	0
T27	406	0	0	0
T28	20119	875	0	0
T29	405	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6514687	0	0
T1	20092	19643	0	0
T2	15963	15533	0	0
T4	496	95	0	0
T5	693	292	0	0
T24	449	48	0	0
T25	403	2	0	0
T26	505	104	0	0
T27	406	5	0	0
T28	20119	19662	0	0
T29	405	4	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	48	0	0
T6	12993	1	0	0
T7	27514	0	0	0
T8	1009	0	0	0
T9	18082	0	0	0
T10	9156	0	0	0
T14	0	1	0	0
T18	0	7	0	0
T39	492	0	0	0
T40	495	0	0	0
T41	502	0	0	0
T42	453	0	0	0
T47	522	0	0	0
T80	0	6	0	0
T82	0	1	0	0
T83	0	1	0	0
T96	0	2	0	0
T247	0	2	0	0
T248	0	7	0	0
T249	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	16840	0	0
T1	20092	6	0	0
T2	15963	165	0	0
T3	0	45	0	0
T4	496	0	0	0
T5	693	0	0	0
T7	0	277	0	0
T9	0	204	0	0
T12	0	382	0	0
T14	0	15	0	0
T17	0	118	0	0
T24	449	0	0	0
T25	403	0	0	0
T26	505	0	0	0
T27	406	0	0	0
T28	20119	44	0	0
T29	405	0	0	0
T67	0	119	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	402	0	0
T1	20092	1	0	0
T2	15963	3	0	0
T3	0	2	0	0
T4	496	0	0	0
T5	693	0	0	0
T7	0	5	0	0
T9	0	3	0	0
T12	0	6	0	0
T14	0	1	0	0
T17	0	4	0	0
T24	449	0	0	0
T25	403	0	0	0
T26	505	0	0	0
T27	406	0	0	0
T28	20119	7	0	0
T29	405	0	0	0
T67	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6138601	0	0
T1	20092	14103	0	0
T2	15963	14315	0	0
T4	496	95	0	0
T5	693	292	0	0
T24	449	48	0	0
T25	403	2	0	0
T26	505	104	0	0
T27	406	5	0	0
T28	20119	16117	0	0
T29	405	4	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6140227	0	0
T1	20092	14103	0	0
T2	15963	14316	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	16117	0	0
T29	405	5	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	492	0	0
T1	20092	1	0	0
T2	15963	3	0	0
T3	0	4	0	0
T4	496	0	0	0
T5	693	0	0	0
T6	0	1	0	0
T7	0	6	0	0
T9	0	3	0	0
T12	0	8	0	0
T14	0	4	0	0
T17	0	4	0	0
T24	449	0	0	0
T25	403	0	0	0
T26	505	0	0	0
T27	406	0	0	0
T28	20119	9	0	0
T29	405	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	453	0	0
T1	20092	1	0	0
T2	15963	3	0	0
T3	0	2	0	0
T4	496	0	0	0
T5	693	0	0	0
T6	0	1	0	0
T7	0	5	0	0
T9	0	3	0	0
T12	0	6	0	0
T14	0	3	0	0
T17	0	4	0	0
T24	449	0	0	0
T25	403	0	0	0
T26	505	0	0	0
T27	406	0	0	0
T28	20119	7	0	0
T29	405	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	402	0	0
T1	20092	1	0	0
T2	15963	3	0	0
T3	0	2	0	0
T4	496	0	0	0
T5	693	0	0	0
T7	0	5	0	0
T9	0	3	0	0
T12	0	6	0	0
T14	0	1	0	0
T17	0	4	0	0
T24	449	0	0	0
T25	403	0	0	0
T26	505	0	0	0
T27	406	0	0	0
T28	20119	7	0	0
T29	405	0	0	0
T67	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	402	0	0
T1	20092	1	0	0
T2	15963	3	0	0
T3	0	2	0	0
T4	496	0	0	0
T5	693	0	0	0
T7	0	5	0	0
T9	0	3	0	0
T12	0	6	0	0
T14	0	1	0	0
T17	0	4	0	0
T24	449	0	0	0
T25	403	0	0	0
T26	505	0	0	0
T27	406	0	0	0
T28	20119	7	0	0
T29	405	0	0	0
T67	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	16393	0	0
T1	20092	5	0	0
T2	15963	162	0	0
T3	0	43	0	0
T4	496	0	0	0
T5	693	0	0	0
T7	0	269	0	0
T9	0	201	0	0
T12	0	376	0	0
T14	0	14	0	0
T17	0	114	0	0
T24	449	0	0	0
T25	403	0	0	0
T26	505	0	0	0
T27	406	0	0	0
T28	20119	37	0	0
T29	405	0	0	0
T67	0	117	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6518002	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	351	0	0
T1	20092	1	0	0
T2	15963	3	0	0
T3	0	2	0	0
T4	496	0	0	0
T5	693	0	0	0
T7	0	2	0	0
T9	0	3	0	0
T12	0	6	0	0
T14	0	1	0	0
T17	0	4	0	0
T24	449	0	0	0
T25	403	0	0	0
T26	505	0	0	0
T27	406	0	0	0
T28	20119	7	0	0
T29	405	0	0	0
T67	0	2	0	0