Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T7,T9
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T7,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T7,T9

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T7,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T9
1	0	Covered	T2,T7,T9
1	1	Covered	T2,T7,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T9
0	1	Covered	T10,T30,T69
1	0	Covered	T10,T86,T107

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T9
0	1	Covered	T2,T7,T9
1	0	Covered	T250

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T7,T9
1	-	Covered	T2,T7,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T7,T9
DetectSt	168	Covered	T2,T7,T9
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T2,T7,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T7,T9
DebounceSt->IdleSt	163	Covered	T82,T83,T234
DetectSt->IdleSt	186	Covered	T10,T30,T69
DetectSt->StableSt	191	Covered	T2,T7,T9
IdleSt->DebounceSt	148	Covered	T2,T7,T9
StableSt->IdleSt	206	Covered	T2,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T7,T9
0	1	Covered	T2,T7,T9
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T9
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T2,T7,T9
IdleSt	0	-	-	-	-	-	-	Covered	T2,T7,T9
DebounceSt	-	1	-	-	-	-	-	Covered	T82,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T7,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T82,T83,T234
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T7,T9
DetectSt	-	-	-	-	1	-	-	Covered	T10,T30,T69
DetectSt	-	-	-	-	0	1	-	Covered	T2,T7,T9
DetectSt	-	-	-	-	0	0	-	Covered	T2,T7,T9
StableSt	-	-	-	-	-	-	1	Covered	T2,T7,T9
StableSt	-	-	-	-	-	-	0	Covered	T2,T7,T9
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7138329	3144	0	0
CntIncr_A	7138329	111558	0	0
CntNoWrap_A	7138329	6512487	0	0
DetectStDropOut_A	7138329	421	0	0
DetectedOut_A	7138329	81841	0	0
DetectedPulseOut_A	7138329	833	0	0
DisabledIdleSt_A	7138329	6048934	0	0
DisabledNoDetection_A	7138329	6051088	0	0
EnterDebounceSt_A	7138329	1579	0	0
EnterDetectSt_A	7138329	1565	0	0
EnterStableSt_A	7138329	833	0	0
PulseIsPulse_A	7138329	833	0	0
StayInStableSt	7138329	80884	0	0
gen_high_event_sva.HighLevelEvent_A	7138329	6518002	0	0
gen_high_level_sva.HighLevelEvent_A	7138329	6518002	0	0
gen_not_sticky_sva.StableStDropOut_A	7138329	708	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	3144	0	0
T2	15963	16	0	0
T3	21356	0	0	0
T6	12993	0	0	0
T7	27514	22	0	0
T8	1009	0	0	0
T9	18082	22	0	0
T10	0	30	0	0
T29	405	0	0	0
T30	0	36	0	0
T31	0	44	0	0
T39	492	0	0	0
T40	495	0	0	0
T47	522	0	0	0
T67	0	22	0	0
T68	0	14	0	0
T69	0	12	0	0
T70	0	24	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	111558	0	0
T2	15963	544	0	0
T3	21356	0	0	0
T6	12993	0	0	0
T7	27514	902	0	0
T8	1009	0	0	0
T9	18082	1045	0	0
T10	0	857	0	0
T29	405	0	0	0
T30	0	1594	0	0
T31	0	1012	0	0
T39	492	0	0	0
T40	495	0	0	0
T47	522	0	0	0
T67	0	539	0	0
T68	0	476	0	0
T69	0	313	0	0
T70	0	804	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6512487	0	0
T1	20092	19645	0	0
T2	15963	15523	0	0
T4	496	95	0	0
T5	693	292	0	0
T24	449	48	0	0
T25	403	2	0	0
T26	505	104	0	0
T27	406	5	0	0
T28	20119	19678	0	0
T29	405	4	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	421	0	0
T10	9156	6	0	0
T11	504	0	0	0
T12	29286	0	0	0
T13	1437	0	0	0
T14	16893	0	0	0
T15	654	0	0	0
T16	23347	0	0	0
T30	7066	18	0	0
T31	19949	0	0	0
T42	453	0	0	0
T69	0	6	0	0
T86	0	15	0	0
T99	0	7	0	0
T101	0	11	0	0
T104	0	2	0	0
T107	0	11	0	0
T211	0	29	0	0
T251	0	9	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	81841	0	0
T2	15963	583	0	0
T3	21356	0	0	0
T6	12993	0	0	0
T7	27514	1031	0	0
T8	1009	0	0	0
T9	18082	258	0	0
T29	405	0	0	0
T31	0	2609	0	0
T39	492	0	0	0
T40	495	0	0	0
T47	522	0	0	0
T67	0	705	0	0
T68	0	636	0	0
T70	0	607	0	0
T85	0	427	0	0
T131	0	1850	0	0
T235	0	2795	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	833	0	0
T2	15963	8	0	0
T3	21356	0	0	0
T6	12993	0	0	0
T7	27514	11	0	0
T8	1009	0	0	0
T9	18082	11	0	0
T29	405	0	0	0
T31	0	22	0	0
T39	492	0	0	0
T40	495	0	0	0
T47	522	0	0	0
T67	0	11	0	0
T68	0	7	0	0
T70	0	12	0	0
T85	0	9	0	0
T131	0	24	0	0
T235	0	22	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6048934	0	0
T1	20092	19645	0	0
T2	15963	10874	0	0
T4	496	95	0	0
T5	693	292	0	0
T24	449	48	0	0
T25	403	2	0	0
T26	505	104	0	0
T27	406	5	0	0
T28	20119	19678	0	0
T29	405	4	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6051088	0	0
T1	20092	19652	0	0
T2	15963	10878	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	1579	0	0
T2	15963	8	0	0
T3	21356	0	0	0
T6	12993	0	0	0
T7	27514	11	0	0
T8	1009	0	0	0
T9	18082	11	0	0
T10	0	15	0	0
T29	405	0	0	0
T30	0	18	0	0
T31	0	22	0	0
T39	492	0	0	0
T40	495	0	0	0
T47	522	0	0	0
T67	0	11	0	0
T68	0	7	0	0
T69	0	6	0	0
T70	0	12	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	1565	0	0
T2	15963	8	0	0
T3	21356	0	0	0
T6	12993	0	0	0
T7	27514	11	0	0
T8	1009	0	0	0
T9	18082	11	0	0
T10	0	15	0	0
T29	405	0	0	0
T30	0	18	0	0
T31	0	22	0	0
T39	492	0	0	0
T40	495	0	0	0
T47	522	0	0	0
T67	0	11	0	0
T68	0	7	0	0
T69	0	6	0	0
T70	0	12	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	833	0	0
T2	15963	8	0	0
T3	21356	0	0	0
T6	12993	0	0	0
T7	27514	11	0	0
T8	1009	0	0	0
T9	18082	11	0	0
T29	405	0	0	0
T31	0	22	0	0
T39	492	0	0	0
T40	495	0	0	0
T47	522	0	0	0
T67	0	11	0	0
T68	0	7	0	0
T70	0	12	0	0
T85	0	9	0	0
T131	0	24	0	0
T235	0	22	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	833	0	0
T2	15963	8	0	0
T3	21356	0	0	0
T6	12993	0	0	0
T7	27514	11	0	0
T8	1009	0	0	0
T9	18082	11	0	0
T29	405	0	0	0
T31	0	22	0	0
T39	492	0	0	0
T40	495	0	0	0
T47	522	0	0	0
T67	0	11	0	0
T68	0	7	0	0
T70	0	12	0	0
T85	0	9	0	0
T131	0	24	0	0
T235	0	22	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	80884	0	0
T2	15963	575	0	0
T3	21356	0	0	0
T6	12993	0	0	0
T7	27514	1018	0	0
T8	1009	0	0	0
T9	18082	246	0	0
T29	405	0	0	0
T31	0	2581	0	0
T39	492	0	0	0
T40	495	0	0	0
T47	522	0	0	0
T67	0	692	0	0
T68	0	628	0	0
T70	0	593	0	0
T85	0	417	0	0
T131	0	1822	0	0
T235	0	2770	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6518002	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6518002	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	708	0	0
T2	15963	8	0	0
T3	21356	0	0	0
T6	12993	0	0	0
T7	27514	9	0	0
T8	1009	0	0	0
T9	18082	10	0	0
T29	405	0	0	0
T31	0	16	0	0
T39	492	0	0	0
T40	495	0	0	0
T47	522	0	0	0
T67	0	9	0	0
T68	0	6	0	0
T70	0	10	0	0
T85	0	8	0	0
T131	0	20	0	0
T235	0	19	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T28,T2
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T28,T2
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T28,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T28,T6

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T28,T6

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T28,T2
1	0	Covered	T1,T28,T2
1	1	Covered	T1,T28,T6

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T28,T6
0	1	Covered	T21,T98,T115
1	0	Covered	T82,T83

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T28,T6
0	1	Covered	T1,T28,T6
1	0	Covered	T82,T83

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T28,T6
1	-	Covered	T1,T28,T6

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T28,T6
DetectSt	168	Covered	T1,T28,T6
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T28,T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T28,T6
DebounceSt->IdleSt	163	Covered	T1,T14,T16
DetectSt->IdleSt	186	Covered	T21,T98,T115
DetectSt->StableSt	191	Covered	T1,T28,T6
IdleSt->DebounceSt	148	Covered	T1,T28,T6
StableSt->IdleSt	206	Covered	T1,T28,T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T28,T6
0	1	Covered	T1,T28,T6
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T28,T6
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T28,T6
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T82,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T28,T6
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T14,T16
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T28,T6
DetectSt	-	-	-	-	1	-	-	Covered	T21,T98,T115
DetectSt	-	-	-	-	0	1	-	Covered	T1,T28,T6
DetectSt	-	-	-	-	0	0	-	Covered	T1,T28,T6
StableSt	-	-	-	-	-	-	1	Covered	T1,T28,T6
StableSt	-	-	-	-	-	-	0	Covered	T1,T28,T6
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7138329	899	0	0
CntIncr_A	7138329	47353	0	0
CntNoWrap_A	7138329	6514732	0	0
DetectStDropOut_A	7138329	54	0	0
DetectedOut_A	7138329	17589	0	0
DetectedPulseOut_A	7138329	369	0	0
DisabledIdleSt_A	7138329	6141655	0	0
DisabledNoDetection_A	7138329	6143291	0	0
EnterDebounceSt_A	7138329	472	0	0
EnterDetectSt_A	7138329	427	0	0
EnterStableSt_A	7138329	369	0	0
PulseIsPulse_A	7138329	369	0	0
StayInStableSt	7138329	17190	0	0
gen_high_level_sva.HighLevelEvent_A	7138329	6518002	0	0
gen_not_sticky_sva.StableStDropOut_A	7138329	337	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	899	0	0
T1	20092	12	0	0
T2	15963	0	0	0
T4	496	0	0	0
T5	693	0	0	0
T6	0	4	0	0
T7	0	2	0	0
T9	0	2	0	0
T12	0	14	0	0
T14	0	1	0	0
T16	0	9	0	0
T17	0	12	0	0
T24	449	0	0	0
T25	403	0	0	0
T26	505	0	0	0
T27	406	0	0	0
T28	20119	4	0	0
T29	405	0	0	0
T31	0	12	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	47353	0	0
T1	20092	947	0	0
T2	15963	0	0	0
T4	496	0	0	0
T5	693	0	0	0
T6	0	102	0	0
T7	0	65	0	0
T9	0	68	0	0
T12	0	735	0	0
T14	0	54	0	0
T16	0	588	0	0
T17	0	642	0	0
T24	449	0	0	0
T25	403	0	0	0
T26	505	0	0	0
T27	406	0	0	0
T28	20119	188	0	0
T29	405	0	0	0
T31	0	324	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6514732	0	0
T1	20092	19633	0	0
T2	15963	15539	0	0
T4	496	95	0	0
T5	693	292	0	0
T24	449	48	0	0
T25	403	2	0	0
T26	505	104	0	0
T27	406	5	0	0
T28	20119	19674	0	0
T29	405	4	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	54	0	0
T21	12011	1	0	0
T54	785	0	0	0
T63	491	0	0	0
T64	488	0	0	0
T80	0	3	0	0
T92	0	2	0	0
T98	0	1	0	0
T108	0	3	0	0
T115	0	6	0	0
T126	0	2	0	0
T144	417	0	0	0
T145	435	0	0	0
T146	410	0	0	0
T147	504	0	0	0
T148	457	0	0	0
T149	802	0	0	0
T247	0	3	0	0
T248	0	5	0	0
T252	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	17589	0	0
T1	20092	277	0	0
T2	15963	0	0	0
T4	496	0	0	0
T5	693	0	0	0
T6	0	76	0	0
T7	0	67	0	0
T9	0	85	0	0
T12	0	374	0	0
T16	0	129	0	0
T17	0	364	0	0
T18	0	39	0	0
T24	449	0	0	0
T25	403	0	0	0
T26	505	0	0	0
T27	406	0	0	0
T28	20119	24	0	0
T29	405	0	0	0
T31	0	531	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	369	0	0
T1	20092	5	0	0
T2	15963	0	0	0
T4	496	0	0	0
T5	693	0	0	0
T6	0	2	0	0
T7	0	1	0	0
T9	0	1	0	0
T12	0	7	0	0
T16	0	3	0	0
T17	0	6	0	0
T18	0	1	0	0
T24	449	0	0	0
T25	403	0	0	0
T26	505	0	0	0
T27	406	0	0	0
T28	20119	2	0	0
T29	405	0	0	0
T31	0	6	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6141655	0	0
T1	20092	14103	0	0
T2	15963	14956	0	0
T4	496	95	0	0
T5	693	292	0	0
T24	449	48	0	0
T25	403	2	0	0
T26	505	104	0	0
T27	406	5	0	0
T28	20119	16117	0	0
T29	405	4	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6143291	0	0
T1	20092	14103	0	0
T2	15963	14961	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	16117	0	0
T29	405	5	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	472	0	0
T1	20092	7	0	0
T2	15963	0	0	0
T4	496	0	0	0
T5	693	0	0	0
T6	0	2	0	0
T7	0	1	0	0
T9	0	1	0	0
T12	0	7	0	0
T14	0	1	0	0
T16	0	6	0	0
T17	0	6	0	0
T24	449	0	0	0
T25	403	0	0	0
T26	505	0	0	0
T27	406	0	0	0
T28	20119	2	0	0
T29	405	0	0	0
T31	0	6	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	427	0	0
T1	20092	5	0	0
T2	15963	0	0	0
T4	496	0	0	0
T5	693	0	0	0
T6	0	2	0	0
T7	0	1	0	0
T9	0	1	0	0
T12	0	7	0	0
T16	0	3	0	0
T17	0	6	0	0
T18	0	1	0	0
T24	449	0	0	0
T25	403	0	0	0
T26	505	0	0	0
T27	406	0	0	0
T28	20119	2	0	0
T29	405	0	0	0
T31	0	6	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	369	0	0
T1	20092	5	0	0
T2	15963	0	0	0
T4	496	0	0	0
T5	693	0	0	0
T6	0	2	0	0
T7	0	1	0	0
T9	0	1	0	0
T12	0	7	0	0
T16	0	3	0	0
T17	0	6	0	0
T18	0	1	0	0
T24	449	0	0	0
T25	403	0	0	0
T26	505	0	0	0
T27	406	0	0	0
T28	20119	2	0	0
T29	405	0	0	0
T31	0	6	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	369	0	0
T1	20092	5	0	0
T2	15963	0	0	0
T4	496	0	0	0
T5	693	0	0	0
T6	0	2	0	0
T7	0	1	0	0
T9	0	1	0	0
T12	0	7	0	0
T16	0	3	0	0
T17	0	6	0	0
T18	0	1	0	0
T24	449	0	0	0
T25	403	0	0	0
T26	505	0	0	0
T27	406	0	0	0
T28	20119	2	0	0
T29	405	0	0	0
T31	0	6	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	17190	0	0
T1	20092	272	0	0
T2	15963	0	0	0
T4	496	0	0	0
T5	693	0	0	0
T6	0	74	0	0
T7	0	66	0	0
T9	0	84	0	0
T12	0	367	0	0
T16	0	126	0	0
T17	0	358	0	0
T18	0	38	0	0
T24	449	0	0	0
T25	403	0	0	0
T26	505	0	0	0
T27	406	0	0	0
T28	20119	22	0	0
T29	405	0	0	0
T31	0	519	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	6518002	0	0
T1	20092	19652	0	0
T2	15963	15544	0	0
T4	496	96	0	0
T5	693	293	0	0
T24	449	49	0	0
T25	403	3	0	0
T26	505	105	0	0
T27	406	6	0	0
T28	20119	19686	0	0
T29	405	5	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138329	337	0	0
T1	20092	5	0	0
T2	15963	0	0	0
T4	496	0	0	0
T5	693	0	0	0
T6	0	2	0	0
T7	0	1	0	0
T9	0	1	0	0
T12	0	7	0	0
T16	0	3	0	0
T17	0	6	0	0
T18	0	1	0	0
T24	449	0	0	0
T25	403	0	0	0
T26	505	0	0	0
T27	406	0	0	0
T28	20119	2	0	0
T29	405	0	0	0
T68	0	1	0	0