Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.34	100.00	96.72	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1254870617	11421	0	0
auto_block_debounce_ctl_rd_A	1254870617	1737	0	0
auto_block_out_ctl_rd_A	1254870617	3224	0	0
com_det_ctl_0_rd_A	1254870617	4020	0	0
com_det_ctl_1_rd_A	1254870617	4120	0	0
com_det_ctl_2_rd_A	1254870617	4041	0	0
com_det_ctl_3_rd_A	1254870617	4069	0	0
com_out_ctl_0_rd_A	1254870617	4726	0	0
com_out_ctl_1_rd_A	1254870617	4961	0	0
com_out_ctl_2_rd_A	1254870617	4833	0	0
com_out_ctl_3_rd_A	1254870617	5051	0	0
com_pre_det_ctl_0_rd_A	1254870617	1109	0	0
com_pre_det_ctl_1_rd_A	1254870617	1157	0	0
com_pre_det_ctl_2_rd_A	1254870617	1330	0	0
com_pre_det_ctl_3_rd_A	1254870617	1165	0	0
com_pre_sel_ctl_0_rd_A	1254870617	5002	0	0
com_pre_sel_ctl_1_rd_A	1254870617	5387	0	0
com_pre_sel_ctl_2_rd_A	1254870617	5297	0	0
com_pre_sel_ctl_3_rd_A	1254870617	5126	0	0
com_sel_ctl_0_rd_A	1254870617	5125	0	0
com_sel_ctl_1_rd_A	1254870617	5399	0	0
com_sel_ctl_2_rd_A	1254870617	5149	0	0
com_sel_ctl_3_rd_A	1254870617	5122	0	0
ec_rst_ctl_rd_A	1254870617	2387	0	0
intr_enable_rd_A	1254870617	1777	0	0
key_intr_ctl_rd_A	1254870617	5104	0	0
key_intr_debounce_ctl_rd_A	1254870617	1295	0	0
key_invert_ctl_rd_A	1254870617	6591	0	0
pin_allowed_ctl_rd_A	1254870617	7926	0	0
pin_out_ctl_rd_A	1254870617	5026	0	0
pin_out_value_rd_A	1254870617	5248	0	0
regwen_rd_A	1254870617	1469	0	0
ulp_ac_debounce_ctl_rd_A	1254870617	1403	0	0
ulp_ctl_rd_A	1254870617	1314	0	0
ulp_lid_debounce_ctl_rd_A	1254870617	1401	0	0
ulp_pwrb_debounce_ctl_rd_A	1254870617	1398	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	11421	0	0
T14	813350	13	0	0
T15	320376	0	0	0
T16	280173	0	0	0
T17	131733	6	0	0
T21	0	11	0	0
T30	342723	0	0	0
T31	957516	0	0	0
T32	197091	0	0	0
T33	130868	0	0	0
T37	0	17	0	0
T49	0	5	0	0
T56	0	25	0	0
T58	103499	0	0	0
T65	63135	0	0	0
T94	0	15	0	0
T95	0	13	0	0
T115	0	3	0	0
T288	0	12	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1737	0	0
T14	813350	34	0	0
T15	320376	0	0	0
T16	280173	0	0	0
T17	131733	6	0	0
T30	342723	0	0	0
T31	957516	0	0	0
T32	197091	0	0	0
T33	130868	0	0	0
T54	0	15	0	0
T55	0	6	0	0
T58	103499	0	0	0
T65	63135	0	0	0
T95	0	46	0	0
T193	0	15	0	0
T288	0	41	0	0
T289	0	8	0	0
T290	0	15	0	0
T291	0	3	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	3224	0	0
T14	813350	32	0	0
T15	320376	0	0	0
T16	280173	0	0	0
T17	131733	9	0	0
T30	342723	0	0	0
T31	957516	0	0	0
T32	197091	0	0	0
T33	130868	0	0	0
T54	0	9	0	0
T55	0	7	0	0
T58	103499	0	0	0
T65	63135	0	0	0
T95	0	23	0	0
T193	0	8	0	0
T288	0	37	0	0
T289	0	10	0	0
T290	0	9	0	0
T291	0	7	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	4020	0	0
T9	867942	38	0	0
T10	228926	0	0	0
T11	118407	0	0	0
T12	143504	54	0	0
T13	56518	0	0	0
T14	813350	65	0	0
T15	320376	0	0	0
T16	280173	0	0	0
T17	0	77	0	0
T41	241424	0	0	0
T42	27208	0	0	0
T68	0	50	0	0
T70	0	70	0	0
T95	0	38	0	0
T98	0	39	0	0
T100	0	86	0	0
T246	0	40	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	4120	0	0
T9	867942	67	0	0
T10	228926	0	0	0
T11	118407	0	0	0
T12	143504	70	0	0
T13	56518	0	0	0
T14	813350	44	0	0
T15	320376	0	0	0
T16	280173	0	0	0
T17	0	66	0	0
T41	241424	0	0	0
T42	27208	0	0	0
T68	0	58	0	0
T70	0	62	0	0
T95	0	29	0	0
T98	0	67	0	0
T100	0	115	0	0
T246	0	67	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	4041	0	0
T9	867942	61	0	0
T10	228926	0	0	0
T11	118407	0	0	0
T12	143504	85	0	0
T13	56518	0	0	0
T14	813350	55	0	0
T15	320376	0	0	0
T16	280173	0	0	0
T17	0	52	0	0
T41	241424	0	0	0
T42	27208	0	0	0
T68	0	60	0	0
T70	0	64	0	0
T95	0	28	0	0
T98	0	82	0	0
T100	0	107	0	0
T246	0	33	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	4069	0	0
T9	867942	49	0	0
T10	228926	0	0	0
T11	118407	0	0	0
T12	143504	81	0	0
T13	56518	0	0	0
T14	813350	57	0	0
T15	320376	0	0	0
T16	280173	0	0	0
T17	0	77	0	0
T41	241424	0	0	0
T42	27208	0	0	0
T68	0	41	0	0
T70	0	88	0	0
T95	0	52	0	0
T98	0	78	0	0
T100	0	88	0	0
T246	0	44	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	4726	0	0
T9	867942	30	0	0
T10	228926	0	0	0
T11	118407	0	0	0
T12	143504	74	0	0
T13	56518	0	0	0
T14	813350	58	0	0
T15	320376	0	0	0
T16	280173	0	0	0
T17	0	74	0	0
T41	241424	0	0	0
T42	27208	0	0	0
T68	0	75	0	0
T70	0	95	0	0
T95	0	37	0	0
T98	0	39	0	0
T100	0	79	0	0
T246	0	30	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	4961	0	0
T9	867942	37	0	0
T10	228926	0	0	0
T11	118407	0	0	0
T12	143504	85	0	0
T13	56518	0	0	0
T14	813350	54	0	0
T15	320376	0	0	0
T16	280173	0	0	0
T17	0	54	0	0
T41	241424	0	0	0
T42	27208	0	0	0
T68	0	48	0	0
T70	0	81	0	0
T95	0	23	0	0
T98	0	68	0	0
T100	0	113	0	0
T246	0	35	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	4833	0	0
T9	867942	48	0	0
T10	228926	0	0	0
T11	118407	0	0	0
T12	143504	64	0	0
T13	56518	0	0	0
T14	813350	66	0	0
T15	320376	0	0	0
T16	280173	0	0	0
T17	0	49	0	0
T41	241424	0	0	0
T42	27208	0	0	0
T68	0	61	0	0
T70	0	72	0	0
T95	0	25	0	0
T98	0	63	0	0
T100	0	105	0	0
T246	0	31	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	5051	0	0
T9	867942	44	0	0
T10	228926	0	0	0
T11	118407	0	0	0
T12	143504	80	0	0
T13	56518	0	0	0
T14	813350	60	0	0
T15	320376	0	0	0
T16	280173	0	0	0
T17	0	65	0	0
T41	241424	0	0	0
T42	27208	0	0	0
T68	0	47	0	0
T70	0	82	0	0
T95	0	25	0	0
T98	0	68	0	0
T100	0	86	0	0
T246	0	27	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1109	0	0
T14	813350	28	0	0
T15	320376	0	0	0
T16	280173	0	0	0
T17	131733	0	0	0
T30	342723	0	0	0
T31	957516	0	0	0
T32	197091	0	0	0
T33	130868	0	0	0
T58	103499	0	0	0
T65	63135	0	0	0
T80	0	25	0	0
T90	0	8	0	0
T95	0	23	0	0
T137	0	21	0	0
T139	0	21	0	0
T176	0	15	0	0
T221	0	4	0	0
T288	0	41	0	0
T292	0	22	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1157	0	0
T14	813350	45	0	0
T15	320376	0	0	0
T16	280173	0	0	0
T17	131733	2	0	0
T30	342723	0	0	0
T31	957516	0	0	0
T32	197091	0	0	0
T33	130868	0	0	0
T58	103499	0	0	0
T65	63135	0	0	0
T80	0	18	0	0
T90	0	3	0	0
T95	0	39	0	0
T137	0	18	0	0
T139	0	19	0	0
T176	0	11	0	0
T288	0	58	0	0
T292	0	13	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1330	0	0
T14	813350	37	0	0
T15	320376	0	0	0
T16	280173	0	0	0
T17	131733	4	0	0
T30	342723	0	0	0
T31	957516	0	0	0
T32	197091	0	0	0
T33	130868	0	0	0
T58	103499	0	0	0
T65	63135	0	0	0
T80	0	16	0	0
T95	0	35	0	0
T137	0	19	0	0
T139	0	8	0	0
T176	0	14	0	0
T221	0	20	0	0
T288	0	43	0	0
T292	0	34	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1165	0	0
T14	813350	53	0	0
T15	320376	0	0	0
T16	280173	0	0	0
T17	131733	21	0	0
T30	342723	0	0	0
T31	957516	0	0	0
T32	197091	0	0	0
T33	130868	0	0	0
T58	103499	0	0	0
T65	63135	0	0	0
T80	0	13	0	0
T95	0	40	0	0
T137	0	14	0	0
T139	0	15	0	0
T176	0	8	0	0
T221	0	7	0	0
T288	0	25	0	0
T292	0	22	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	5002	0	0
T9	867942	44	0	0
T10	228926	0	0	0
T11	118407	0	0	0
T12	143504	67	0	0
T13	56518	0	0	0
T14	813350	51	0	0
T15	320376	0	0	0
T16	280173	0	0	0
T17	0	72	0	0
T41	241424	0	0	0
T42	27208	0	0	0
T68	0	55	0	0
T70	0	61	0	0
T95	0	39	0	0
T98	0	49	0	0
T100	0	94	0	0
T246	0	34	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	5387	0	0
T9	867942	60	0	0
T10	228926	0	0	0
T11	118407	0	0	0
T12	143504	79	0	0
T13	56518	0	0	0
T14	813350	63	0	0
T15	320376	0	0	0
T16	280173	0	0	0
T17	0	100	0	0
T41	241424	0	0	0
T42	27208	0	0	0
T68	0	64	0	0
T70	0	70	0	0
T95	0	32	0	0
T98	0	69	0	0
T100	0	82	0	0
T246	0	63	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	5297	0	0
T9	867942	69	0	0
T10	228926	0	0	0
T11	118407	0	0	0
T12	143504	99	0	0
T13	56518	0	0	0
T14	813350	62	0	0
T15	320376	0	0	0
T16	280173	0	0	0
T17	0	65	0	0
T41	241424	0	0	0
T42	27208	0	0	0
T68	0	46	0	0
T70	0	58	0	0
T95	0	36	0	0
T98	0	75	0	0
T100	0	115	0	0
T246	0	37	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	5126	0	0
T9	867942	48	0	0
T10	228926	0	0	0
T11	118407	0	0	0
T12	143504	68	0	0
T13	56518	0	0	0
T14	813350	52	0	0
T15	320376	0	0	0
T16	280173	0	0	0
T17	0	41	0	0
T41	241424	0	0	0
T42	27208	0	0	0
T68	0	34	0	0
T70	0	67	0	0
T95	0	17	0	0
T98	0	84	0	0
T100	0	73	0	0
T246	0	33	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	5125	0	0
T9	867942	51	0	0
T10	228926	0	0	0
T11	118407	0	0	0
T12	143504	69	0	0
T13	56518	0	0	0
T14	813350	61	0	0
T15	320376	0	0	0
T16	280173	0	0	0
T17	0	47	0	0
T41	241424	0	0	0
T42	27208	0	0	0
T68	0	72	0	0
T70	0	72	0	0
T95	0	41	0	0
T98	0	72	0	0
T100	0	65	0	0
T246	0	40	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	5399	0	0
T9	867942	25	0	0
T10	228926	0	0	0
T11	118407	0	0	0
T12	143504	86	0	0
T13	56518	0	0	0
T14	813350	57	0	0
T15	320376	0	0	0
T16	280173	0	0	0
T17	0	79	0	0
T41	241424	0	0	0
T42	27208	0	0	0
T68	0	47	0	0
T70	0	59	0	0
T95	0	39	0	0
T98	0	70	0	0
T100	0	85	0	0
T246	0	57	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	5149	0	0
T9	867942	46	0	0
T10	228926	0	0	0
T11	118407	0	0	0
T12	143504	97	0	0
T13	56518	0	0	0
T14	813350	46	0	0
T15	320376	0	0	0
T16	280173	0	0	0
T17	0	88	0	0
T41	241424	0	0	0
T42	27208	0	0	0
T68	0	68	0	0
T70	0	60	0	0
T95	0	41	0	0
T98	0	58	0	0
T100	0	85	0	0
T246	0	38	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	5122	0	0
T9	867942	63	0	0
T10	228926	0	0	0
T11	118407	0	0	0
T12	143504	66	0	0
T13	56518	0	0	0
T14	813350	42	0	0
T15	320376	0	0	0
T16	280173	0	0	0
T17	0	38	0	0
T41	241424	0	0	0
T42	27208	0	0	0
T68	0	33	0	0
T70	0	71	0	0
T95	0	29	0	0
T98	0	50	0	0
T100	0	91	0	0
T246	0	50	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	2387	0	0
T9	867942	12	0	0
T10	228926	0	0	0
T11	118407	0	0	0
T12	143504	44	0	0
T13	56518	0	0	0
T14	813350	64	0	0
T15	320376	0	0	0
T16	280173	0	0	0
T17	0	28	0	0
T30	0	3	0	0
T41	241424	0	0	0
T42	27208	0	0	0
T68	0	12	0	0
T70	0	13	0	0
T98	0	4	0	0
T246	0	8	0	0
T293	0	2	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1777	0	0
T14	813350	46	0	0
T15	320376	0	0	0
T16	280173	0	0	0
T17	131733	2	0	0
T30	342723	0	0	0
T31	957516	0	0	0
T32	197091	0	0	0
T33	130868	0	0	0
T58	103499	0	0	0
T65	63135	0	0	0
T80	0	58	0	0
T95	0	52	0	0
T137	0	2	0	0
T139	0	19	0	0
T176	0	5	0	0
T221	0	58	0	0
T288	0	24	0	0
T292	0	56	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	5104	0	0
T14	813350	40	0	0
T15	320376	0	0	0
T16	280173	0	0	0
T17	131733	2	0	0
T30	342723	0	0	0
T31	957516	0	0	0
T32	197091	0	0	0
T33	130868	0	0	0
T58	103499	0	0	0
T65	63135	0	0	0
T80	0	30	0	0
T82	0	50	0	0
T95	0	36	0	0
T137	0	23	0	0
T152	0	5	0	0
T187	0	3	0	0
T288	0	57	0	0
T292	0	24	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1295	0	0
T14	813350	35	0	0
T15	320376	0	0	0
T16	280173	0	0	0
T17	131733	11	0	0
T30	342723	0	0	0
T31	957516	0	0	0
T32	197091	0	0	0
T33	130868	0	0	0
T58	103499	0	0	0
T65	63135	0	0	0
T80	0	27	0	0
T90	0	4	0	0
T95	0	42	0	0
T137	0	22	0	0
T139	0	12	0	0
T176	0	9	0	0
T288	0	41	0	0
T292	0	25	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	6591	0	0
T14	813350	42	0	0
T15	320376	0	0	0
T16	280173	0	0	0
T17	131733	0	0	0
T30	342723	0	0	0
T31	957516	0	0	0
T32	197091	0	0	0
T33	130868	0	0	0
T58	103499	0	0	0
T62	0	84	0	0
T65	63135	0	0	0
T95	0	42	0	0
T193	0	89	0	0
T288	0	46	0	0
T292	0	283	0	0
T294	0	28	0	0
T295	0	59	0	0
T296	0	68	0	0
T297	0	62	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	7926	0	0
T2	766221	0	0	0
T3	102509	0	0	0
T6	311845	0	0	0
T7	130698	0	0	0
T8	60320	0	0	0
T14	0	102	0	0
T26	68248	82	0	0
T27	50719	0	0	0
T28	482863	0	0	0
T29	74995	0	0	0
T41	0	73	0	0
T47	245142	0	0	0
T65	0	72	0	0
T80	0	75	0	0
T95	0	29	0	0
T177	0	68	0	0
T288	0	120	0	0
T292	0	283	0	0
T298	0	125	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	5026	0	0
T2	766221	0	0	0
T3	102509	0	0	0
T6	311845	0	0	0
T7	130698	0	0	0
T8	60320	0	0	0
T14	0	123	0	0
T17	0	1	0	0
T26	68248	70	0	0
T27	50719	0	0	0
T28	482863	0	0	0
T29	74995	0	0	0
T41	0	88	0	0
T47	245142	0	0	0
T65	0	63	0	0
T95	0	34	0	0
T177	0	68	0	0
T288	0	115	0	0
T292	0	210	0	0
T298	0	147	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	5248	0	0
T2	766221	0	0	0
T3	102509	0	0	0
T6	311845	0	0	0
T7	130698	0	0	0
T8	60320	0	0	0
T14	0	77	0	0
T17	0	8	0	0
T26	68248	60	0	0
T27	50719	0	0	0
T28	482863	0	0	0
T29	74995	0	0	0
T41	0	56	0	0
T47	245142	0	0	0
T65	0	53	0	0
T95	0	50	0	0
T177	0	55	0	0
T288	0	125	0	0
T292	0	260	0	0
T298	0	128	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1469	0	0
T14	813350	34	0	0
T15	320376	0	0	0
T16	280173	0	0	0
T17	131733	0	0	0
T30	342723	0	0	0
T31	957516	0	0	0
T32	197091	0	0	0
T33	130868	0	0	0
T58	103499	0	0	0
T65	63135	0	0	0
T80	0	14	0	0
T90	0	5	0	0
T95	0	20	0	0
T137	0	7	0	0
T139	0	13	0	0
T176	0	1	0	0
T221	0	13	0	0
T288	0	40	0	0
T292	0	30	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1403	0	0
T13	56518	6	0	0
T14	813350	35	0	0
T15	320376	0	0	0
T16	280173	0	0	0
T17	131733	7	0	0
T30	342723	0	0	0
T31	957516	0	0	0
T32	197091	0	0	0
T33	130868	0	0	0
T58	103499	4	0	0
T95	0	34	0	0
T113	0	5	0	0
T114	0	3	0	0
T288	0	34	0	0
T299	0	6	0	0
T300	0	3	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1314	0	0
T13	56518	1	0	0
T14	813350	44	0	0
T15	320376	0	0	0
T16	280173	0	0	0
T17	131733	8	0	0
T30	342723	0	0	0
T31	957516	0	0	0
T32	197091	0	0	0
T33	130868	0	0	0
T58	103499	0	0	0
T80	0	28	0	0
T95	0	44	0	0
T113	0	4	0	0
T116	0	12	0	0
T288	0	46	0	0
T292	0	34	0	0
T301	0	12	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1401	0	0
T13	56518	8	0	0
T14	813350	20	0	0
T15	320376	0	0	0
T16	280173	0	0	0
T17	131733	11	0	0
T30	342723	0	0	0
T31	957516	0	0	0
T32	197091	0	0	0
T33	130868	0	0	0
T58	103499	7	0	0
T95	0	34	0	0
T114	0	4	0	0
T116	0	2	0	0
T288	0	36	0	0
T299	0	3	0	0
T300	0	3	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	1398	0	0
T13	56518	4	0	0
T14	813350	33	0	0
T15	320376	0	0	0
T16	280173	0	0	0
T17	131733	14	0	0
T30	342723	0	0	0
T31	957516	0	0	0
T32	197091	0	0	0
T33	130868	0	0	0
T58	103499	2	0	0
T95	0	43	0	0
T113	0	2	0	0
T114	0	10	0	0
T288	0	41	0	0
T299	0	4	0	0
T300	0	8	0	0