Unified Coverage Report :: Module :: sysrst_ctrl_reg_top

Module : sysrst_ctrl_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.61	100.00	94.45			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg	98.61	100.00	94.44			100.00	100.00

---

Module Instance : tb.dut.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.61	100.00	94.44			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.93	99.40	96.43	100.00		98.84	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.34	100.00	96.72	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test	100.00	100.00
u_auto_block_debounce_ctl_auto_block_enable	100.00	100.00	100.00			100.00
u_auto_block_debounce_ctl_cdc	98.33	100.00	93.33			100.00	100.00
u_auto_block_debounce_ctl_debounce_timer	100.00	100.00	100.00			100.00
u_auto_block_out_ctl_cdc	99.17	100.00	96.67			100.00	100.00
u_auto_block_out_ctl_key0_out_sel	100.00	100.00	100.00			100.00
u_auto_block_out_ctl_key0_out_value	100.00	100.00	100.00			100.00
u_auto_block_out_ctl_key1_out_sel	100.00	100.00	100.00			100.00
u_auto_block_out_ctl_key1_out_value	100.00	100.00	100.00			100.00
u_auto_block_out_ctl_key2_out_sel	100.00	100.00	100.00			100.00
u_auto_block_out_ctl_key2_out_value	100.00	100.00	100.00			100.00
u_chk	100.00	100.00		100.00			100.00
u_com_det_ctl_0	100.00	100.00	100.00			100.00
u_com_det_ctl_0_cdc	99.17	100.00	96.67			100.00	100.00
u_com_det_ctl_1	100.00	100.00	100.00			100.00
u_com_det_ctl_1_cdc	99.17	100.00	96.67			100.00	100.00
u_com_det_ctl_2	100.00	100.00	100.00			100.00
u_com_det_ctl_2_cdc	99.17	100.00	96.67			100.00	100.00
u_com_det_ctl_3	100.00	100.00	100.00			100.00
u_com_det_ctl_3_cdc	99.17	100.00	96.67			100.00	100.00
u_com_out_ctl_0_bat_disable_0	100.00	100.00	100.00			100.00
u_com_out_ctl_0_cdc	99.17	100.00	96.67			100.00	100.00
u_com_out_ctl_0_ec_rst_0	100.00	100.00	100.00			100.00
u_com_out_ctl_0_interrupt_0	100.00	100.00	100.00			100.00
u_com_out_ctl_0_rst_req_0	100.00	100.00	100.00			100.00
u_com_out_ctl_1_bat_disable_1	100.00	100.00	100.00			100.00
u_com_out_ctl_1_cdc	99.17	100.00	96.67			100.00	100.00
u_com_out_ctl_1_ec_rst_1	100.00	100.00	100.00			100.00
u_com_out_ctl_1_interrupt_1	100.00	100.00	100.00			100.00
u_com_out_ctl_1_rst_req_1	100.00	100.00	100.00			100.00
u_com_out_ctl_2_bat_disable_2	100.00	100.00	100.00			100.00
u_com_out_ctl_2_cdc	99.17	100.00	96.67			100.00	100.00
u_com_out_ctl_2_ec_rst_2	100.00	100.00	100.00			100.00
u_com_out_ctl_2_interrupt_2	100.00	100.00	100.00			100.00
u_com_out_ctl_2_rst_req_2	100.00	100.00	100.00			100.00
u_com_out_ctl_3_bat_disable_3	100.00	100.00	100.00			100.00
u_com_out_ctl_3_cdc	99.17	100.00	96.67			100.00	100.00
u_com_out_ctl_3_ec_rst_3	100.00	100.00	100.00			100.00
u_com_out_ctl_3_interrupt_3	100.00	100.00	100.00			100.00
u_com_out_ctl_3_rst_req_3	100.00	100.00	100.00			100.00
u_com_pre_det_ctl_0	100.00	100.00	100.00			100.00
u_com_pre_det_ctl_0_cdc	99.17	100.00	96.67			100.00	100.00
u_com_pre_det_ctl_1	100.00	100.00	100.00			100.00
u_com_pre_det_ctl_1_cdc	99.17	100.00	96.67			100.00	100.00
u_com_pre_det_ctl_2	100.00	100.00	100.00			100.00
u_com_pre_det_ctl_2_cdc	99.17	100.00	96.67			100.00	100.00
u_com_pre_det_ctl_3	100.00	100.00	100.00			100.00
u_com_pre_det_ctl_3_cdc	99.17	100.00	96.67			100.00	100.00
u_com_pre_sel_ctl_0_ac_present_sel_0	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_0_cdc	99.17	100.00	96.67			100.00	100.00
u_com_pre_sel_ctl_0_key0_in_sel_0	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_0_key1_in_sel_0	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_0_key2_in_sel_0	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_0_pwrb_in_sel_0	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_1_ac_present_sel_1	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_1_cdc	99.17	100.00	96.67			100.00	100.00
u_com_pre_sel_ctl_1_key0_in_sel_1	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_1_key1_in_sel_1	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_1_key2_in_sel_1	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_1_pwrb_in_sel_1	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_2_ac_present_sel_2	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_2_cdc	99.17	100.00	96.67			100.00	100.00
u_com_pre_sel_ctl_2_key0_in_sel_2	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_2_key1_in_sel_2	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_2_key2_in_sel_2	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_2_pwrb_in_sel_2	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_3_ac_present_sel_3	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_3_cdc	99.17	100.00	96.67			100.00	100.00
u_com_pre_sel_ctl_3_key0_in_sel_3	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_3_key1_in_sel_3	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_3_key2_in_sel_3	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_3_pwrb_in_sel_3	100.00	100.00	100.00			100.00
u_com_sel_ctl_0_ac_present_sel_0	100.00	100.00	100.00			100.00
u_com_sel_ctl_0_cdc	99.17	100.00	96.67			100.00	100.00
u_com_sel_ctl_0_key0_in_sel_0	100.00	100.00	100.00			100.00
u_com_sel_ctl_0_key1_in_sel_0	100.00	100.00	100.00			100.00
u_com_sel_ctl_0_key2_in_sel_0	100.00	100.00	100.00			100.00
u_com_sel_ctl_0_pwrb_in_sel_0	100.00	100.00	100.00			100.00
u_com_sel_ctl_1_ac_present_sel_1	100.00	100.00	100.00			100.00
u_com_sel_ctl_1_cdc	99.17	100.00	96.67			100.00	100.00
u_com_sel_ctl_1_key0_in_sel_1	100.00	100.00	100.00			100.00
u_com_sel_ctl_1_key1_in_sel_1	100.00	100.00	100.00			100.00
u_com_sel_ctl_1_key2_in_sel_1	100.00	100.00	100.00			100.00
u_com_sel_ctl_1_pwrb_in_sel_1	100.00	100.00	100.00			100.00
u_com_sel_ctl_2_ac_present_sel_2	100.00	100.00	100.00			100.00
u_com_sel_ctl_2_cdc	99.17	100.00	96.67			100.00	100.00
u_com_sel_ctl_2_key0_in_sel_2	100.00	100.00	100.00			100.00
u_com_sel_ctl_2_key1_in_sel_2	100.00	100.00	100.00			100.00
u_com_sel_ctl_2_key2_in_sel_2	100.00	100.00	100.00			100.00
u_com_sel_ctl_2_pwrb_in_sel_2	100.00	100.00	100.00			100.00
u_com_sel_ctl_3_ac_present_sel_3	100.00	100.00	100.00			100.00
u_com_sel_ctl_3_cdc	99.17	100.00	96.67			100.00	100.00
u_com_sel_ctl_3_key0_in_sel_3	100.00	100.00	100.00			100.00
u_com_sel_ctl_3_key1_in_sel_3	100.00	100.00	100.00			100.00
u_com_sel_ctl_3_key2_in_sel_3	100.00	100.00	100.00			100.00
u_com_sel_ctl_3_pwrb_in_sel_3	100.00	100.00	100.00			100.00
u_combo_intr_status_cdc	96.76	100.00	88.73			98.31	100.00
u_combo_intr_status_combo0_h2l	100.00	100.00	100.00			100.00
u_combo_intr_status_combo1_h2l	100.00	100.00	100.00			100.00
u_combo_intr_status_combo2_h2l	100.00	100.00	100.00			100.00
u_combo_intr_status_combo3_h2l	100.00	100.00	100.00			100.00
u_ec_rst_ctl	100.00	100.00	100.00			100.00
u_ec_rst_ctl_cdc	98.33	100.00	93.33			100.00	100.00
u_intr_enable	100.00	100.00	100.00			100.00
u_intr_state	100.00	100.00	100.00			100.00
u_intr_test	100.00	100.00
u_key_intr_ctl_ac_present_h2l	100.00	100.00	100.00			100.00
u_key_intr_ctl_ac_present_l2h	100.00	100.00	100.00			100.00
u_key_intr_ctl_cdc	99.17	100.00	96.67			100.00	100.00
u_key_intr_ctl_ec_rst_l_h2l	100.00	100.00	100.00			100.00
u_key_intr_ctl_ec_rst_l_l2h	100.00	100.00	100.00			100.00
u_key_intr_ctl_flash_wp_l_h2l	100.00	100.00	100.00			100.00
u_key_intr_ctl_flash_wp_l_l2h	100.00	100.00	100.00			100.00
u_key_intr_ctl_key0_in_h2l	100.00	100.00	100.00			100.00
u_key_intr_ctl_key0_in_l2h	100.00	100.00	100.00			100.00
u_key_intr_ctl_key1_in_h2l	100.00	100.00	100.00			100.00
u_key_intr_ctl_key1_in_l2h	100.00	100.00	100.00			100.00
u_key_intr_ctl_key2_in_h2l	100.00	100.00	100.00			100.00
u_key_intr_ctl_key2_in_l2h	100.00	100.00	100.00			100.00
u_key_intr_ctl_pwrb_in_h2l	100.00	100.00	100.00			100.00
u_key_intr_ctl_pwrb_in_l2h	100.00	100.00	100.00			100.00
u_key_intr_debounce_ctl	100.00	100.00	100.00			100.00
u_key_intr_debounce_ctl_cdc	98.33	100.00	93.33			100.00	100.00
u_key_intr_status_ac_present_h2l	100.00	100.00	100.00			100.00
u_key_intr_status_ac_present_l2h	100.00	100.00	100.00			100.00
u_key_intr_status_cdc	96.76	100.00	88.73			98.31	100.00
u_key_intr_status_ec_rst_l_h2l	100.00	100.00	100.00			100.00
u_key_intr_status_ec_rst_l_l2h	100.00	100.00	100.00			100.00
u_key_intr_status_flash_wp_l_h2l	100.00	100.00	100.00			100.00
u_key_intr_status_flash_wp_l_l2h	100.00	100.00	100.00			100.00
u_key_intr_status_key0_in_h2l	100.00	100.00	100.00			100.00
u_key_intr_status_key0_in_l2h	100.00	100.00	100.00			100.00
u_key_intr_status_key1_in_h2l	100.00	100.00	100.00			100.00
u_key_intr_status_key1_in_l2h	100.00	100.00	100.00			100.00
u_key_intr_status_key2_in_h2l	100.00	100.00	100.00			100.00
u_key_intr_status_key2_in_l2h	100.00	100.00	100.00			100.00
u_key_intr_status_pwrb_h2l	100.00	100.00	100.00			100.00
u_key_intr_status_pwrb_l2h	100.00	100.00	100.00			100.00
u_key_invert_ctl_ac_present	100.00	100.00	100.00			100.00
u_key_invert_ctl_bat_disable	100.00	100.00	100.00			100.00
u_key_invert_ctl_cdc	99.17	100.00	96.67			100.00	100.00
u_key_invert_ctl_key0_in	100.00	100.00	100.00			100.00
u_key_invert_ctl_key0_out	100.00	100.00	100.00			100.00
u_key_invert_ctl_key1_in	100.00	100.00	100.00			100.00
u_key_invert_ctl_key1_out	100.00	100.00	100.00			100.00
u_key_invert_ctl_key2_in	100.00	100.00	100.00			100.00
u_key_invert_ctl_key2_out	100.00	100.00	100.00			100.00
u_key_invert_ctl_lid_open	100.00	100.00	100.00			100.00
u_key_invert_ctl_pwrb_in	100.00	100.00	100.00			100.00
u_key_invert_ctl_pwrb_out	100.00	100.00	100.00			100.00
u_key_invert_ctl_z3_wakeup	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_bat_disable_0	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_bat_disable_1	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_cdc	99.17	100.00	96.67			100.00	100.00
u_pin_allowed_ctl_ec_rst_l_0	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_ec_rst_l_1	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_flash_wp_l_0	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_flash_wp_l_1	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_key0_out_0	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_key0_out_1	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_key1_out_0	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_key1_out_1	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_key2_out_0	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_key2_out_1	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_pwrb_out_0	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_pwrb_out_1	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_z3_wakeup_0	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_z3_wakeup_1	100.00	100.00	100.00			100.00
u_pin_in_value_ac_present	62.59	77.78	50.00			60.00
u_pin_in_value_ec_rst_l	62.59	77.78	50.00			60.00
u_pin_in_value_flash_wp_l	62.59	77.78	50.00			60.00
u_pin_in_value_key0_in	62.59	77.78	50.00			60.00
u_pin_in_value_key1_in	62.59	77.78	50.00			60.00
u_pin_in_value_key2_in	62.59	77.78	50.00			60.00
u_pin_in_value_lid_open	62.59	77.78	50.00			60.00
u_pin_in_value_pwrb_in	62.59	77.78	50.00			60.00
u_pin_out_ctl_bat_disable	100.00	100.00	100.00			100.00
u_pin_out_ctl_cdc	99.17	100.00	96.67			100.00	100.00
u_pin_out_ctl_ec_rst_l	100.00	100.00	100.00			100.00
u_pin_out_ctl_flash_wp_l	100.00	100.00	100.00			100.00
u_pin_out_ctl_key0_out	100.00	100.00	100.00			100.00
u_pin_out_ctl_key1_out	100.00	100.00	100.00			100.00
u_pin_out_ctl_key2_out	100.00	100.00	100.00			100.00
u_pin_out_ctl_pwrb_out	100.00	100.00	100.00			100.00
u_pin_out_ctl_z3_wakeup	100.00	100.00	100.00			100.00
u_pin_out_value_bat_disable	100.00	100.00	100.00			100.00
u_pin_out_value_cdc	99.17	100.00	96.67			100.00	100.00
u_pin_out_value_ec_rst_l	100.00	100.00	100.00			100.00
u_pin_out_value_flash_wp_l	100.00	100.00	100.00			100.00
u_pin_out_value_key0_out	100.00	100.00	100.00			100.00
u_pin_out_value_key1_out	100.00	100.00	100.00			100.00
u_pin_out_value_key2_out	100.00	100.00	100.00			100.00
u_pin_out_value_pwrb_out	100.00	100.00	100.00			100.00
u_pin_out_value_z3_wakeup	100.00	100.00	100.00			100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	98.69	97.14	97.62			100.00	100.00
u_regwen	100.00	100.00	100.00			100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_ulp_ac_debounce_ctl	100.00	100.00	100.00			100.00
u_ulp_ac_debounce_ctl_cdc	98.33	100.00	93.33			100.00	100.00
u_ulp_ctl	100.00	100.00	100.00			100.00
u_ulp_ctl_cdc	99.22	100.00	96.88			100.00	100.00
u_ulp_lid_debounce_ctl	100.00	100.00	100.00			100.00
u_ulp_lid_debounce_ctl_cdc	98.33	100.00	93.33			100.00	100.00
u_ulp_pwrb_debounce_ctl	100.00	100.00	100.00			100.00
u_ulp_pwrb_debounce_ctl_cdc	98.33	100.00	93.33			100.00	100.00
u_ulp_status	100.00	100.00	100.00			100.00
u_ulp_status_cdc	93.79	96.99	84.93			93.22	100.00
u_wkup_status	100.00	100.00	100.00			100.00
u_wkup_status_cdc	93.79	96.99	84.93			93.22	100.00

Line Coverage for Module : sysrst_ctrl_reg_top

	Line No.	Total	Covered	Percent
TOTAL		532	532	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
ALWAYS	269	2	2	100.00
CONT_ASSIGN	297	1	1	100.00
ALWAYS	308	2	2	100.00
CONT_ASSIGN	336	1	1	100.00
ALWAYS	347	2	2	100.00
CONT_ASSIGN	375	1	1	100.00
ALWAYS	386	2	2	100.00
CONT_ASSIGN	414	1	1	100.00
ALWAYS	424	2	2	100.00
CONT_ASSIGN	452	1	1	100.00
ALWAYS	465	4	4	100.00
CONT_ASSIGN	495	1	1	100.00
ALWAYS	508	4	4	100.00
CONT_ASSIGN	538	1	1	100.00
ALWAYS	560	13	13	100.00
CONT_ASSIGN	599	1	1	100.00
ALWAYS	625	17	17	100.00
CONT_ASSIGN	668	1	1	100.00
ALWAYS	685	9	9	100.00
CONT_ASSIGN	720	1	1	100.00
ALWAYS	737	9	9	100.00
CONT_ASSIGN	772	1	1	100.00
ALWAYS	796	15	15	100.00
CONT_ASSIGN	837	1	1	100.00
ALWAYS	848	2	2	100.00
CONT_ASSIGN	876	1	1	100.00
ALWAYS	888	3	3	100.00
CONT_ASSIGN	917	1	1	100.00
ALWAYS	933	7	7	100.00
CONT_ASSIGN	966	1	1	100.00
ALWAYS	981	6	6	100.00
CONT_ASSIGN	1013	1	1	100.00
ALWAYS	1028	6	6	100.00
CONT_ASSIGN	1060	1	1	100.00
ALWAYS	1075	6	6	100.00
CONT_ASSIGN	1107	1	1	100.00
ALWAYS	1122	6	6	100.00
CONT_ASSIGN	1154	1	1	100.00
ALWAYS	1165	2	2	100.00
CONT_ASSIGN	1193	1	1	100.00
ALWAYS	1204	2	2	100.00
CONT_ASSIGN	1232	1	1	100.00
ALWAYS	1243	2	2	100.00
CONT_ASSIGN	1271	1	1	100.00
ALWAYS	1282	2	2	100.00
CONT_ASSIGN	1310	1	1	100.00
ALWAYS	1325	6	6	100.00
CONT_ASSIGN	1357	1	1	100.00
ALWAYS	1372	6	6	100.00
CONT_ASSIGN	1404	1	1	100.00
ALWAYS	1419	6	6	100.00
CONT_ASSIGN	1451	1	1	100.00
ALWAYS	1466	6	6	100.00
CONT_ASSIGN	1498	1	1	100.00
ALWAYS	1509	2	2	100.00
CONT_ASSIGN	1537	1	1	100.00
ALWAYS	1548	2	2	100.00
CONT_ASSIGN	1576	1	1	100.00
ALWAYS	1587	2	2	100.00
CONT_ASSIGN	1615	1	1	100.00
ALWAYS	1626	2	2	100.00
CONT_ASSIGN	1654	1	1	100.00
ALWAYS	1668	5	5	100.00
CONT_ASSIGN	1699	1	1	100.00
ALWAYS	1713	5	5	100.00
CONT_ASSIGN	1744	1	1	100.00
ALWAYS	1758	5	5	100.00
CONT_ASSIGN	1789	1	1	100.00
ALWAYS	1803	5	5	100.00
CONT_ASSIGN	1834	1	1	100.00
ALWAYS	1853	10	10	100.00
CONT_ASSIGN	1889	1	1	100.00
ALWAYS	1928	30	30	100.00
CONT_ASSIGN	1984	1	1	100.00
CONT_ASSIGN	2047	1	1	100.00
CONT_ASSIGN	2061	1	1	100.00
CONT_ASSIGN	2067	1	1	100.00
CONT_ASSIGN	2081	1	1	100.00
CONT_ASSIGN	2115	1	1	100.00
CONT_ASSIGN	2146	1	1	100.00
CONT_ASSIGN	2178	1	1	100.00
CONT_ASSIGN	2210	1	1	100.00
CONT_ASSIGN	2269	1	1	100.00
CONT_ASSIGN	2299	1	1	100.00
CONT_ASSIGN	2330	1	1	100.00
CONT_ASSIGN	2659	1	1	100.00
CONT_ASSIGN	3750	1	1	100.00
CONT_ASSIGN	4133	1	1	100.00
CONT_ASSIGN	4165	1	1	100.00
CONT_ASSIGN	4225	1	1	100.00
CONT_ASSIGN	4394	1	1	100.00
CONT_ASSIGN	4535	1	1	100.00
CONT_ASSIGN	4676	1	1	100.00
CONT_ASSIGN	4817	1	1	100.00
CONT_ASSIGN	4958	1	1	100.00
CONT_ASSIGN	4990	1	1	100.00
CONT_ASSIGN	5022	1	1	100.00
CONT_ASSIGN	5054	1	1	100.00
CONT_ASSIGN	5086	1	1	100.00
CONT_ASSIGN	5227	1	1	100.00
CONT_ASSIGN	5368	1	1	100.00
CONT_ASSIGN	5509	1	1	100.00
CONT_ASSIGN	5650	1	1	100.00
CONT_ASSIGN	5682	1	1	100.00
CONT_ASSIGN	5714	1	1	100.00
CONT_ASSIGN	5746	1	1	100.00
CONT_ASSIGN	5778	1	1	100.00
CONT_ASSIGN	5892	1	1	100.00
CONT_ASSIGN	6006	1	1	100.00
CONT_ASSIGN	6120	1	1	100.00
CONT_ASSIGN	6232	1	1	100.00
CONT_ASSIGN	6344	1	1	100.00
ALWAYS	6727	44	44	100.00
CONT_ASSIGN	6773	1	1	100.00
ALWAYS	6777	1	1	100.00
CONT_ASSIGN	6824	1	1	100.00
CONT_ASSIGN	6826	1	1	100.00
CONT_ASSIGN	6827	1	1	100.00
CONT_ASSIGN	6829	1	1	100.00
CONT_ASSIGN	6830	1	1	100.00
CONT_ASSIGN	6832	1	1	100.00
CONT_ASSIGN	6833	1	1	100.00
CONT_ASSIGN	6835	1	1	100.00
CONT_ASSIGN	6836	1	1	100.00
CONT_ASSIGN	6838	1	1	100.00
CONT_ASSIGN	6839	1	1	100.00
CONT_ASSIGN	6841	1	1	100.00
CONT_ASSIGN	6843	1	1	100.00
CONT_ASSIGN	6845	1	1	100.00
CONT_ASSIGN	6847	1	1	100.00
CONT_ASSIGN	6849	1	1	100.00
CONT_ASSIGN	6851	1	1	100.00
CONT_ASSIGN	6853	1	1	100.00
CONT_ASSIGN	6866	1	1	100.00
CONT_ASSIGN	6883	1	1	100.00
CONT_ASSIGN	6892	1	1	100.00
CONT_ASSIGN	6901	1	1	100.00
CONT_ASSIGN	6916	1	1	100.00
CONT_ASSIGN	6918	1	1	100.00
CONT_ASSIGN	6921	1	1	100.00
CONT_ASSIGN	6928	1	1	100.00
CONT_ASSIGN	6934	1	1	100.00
CONT_ASSIGN	6940	1	1	100.00
CONT_ASSIGN	6946	1	1	100.00
CONT_ASSIGN	6952	1	1	100.00
CONT_ASSIGN	6954	1	1	100.00
CONT_ASSIGN	6956	1	1	100.00
CONT_ASSIGN	6958	1	1	100.00
CONT_ASSIGN	6960	1	1	100.00
CONT_ASSIGN	6966	1	1	100.00
CONT_ASSIGN	6972	1	1	100.00
CONT_ASSIGN	6978	1	1	100.00
CONT_ASSIGN	6984	1	1	100.00
CONT_ASSIGN	6986	1	1	100.00
CONT_ASSIGN	6988	1	1	100.00
CONT_ASSIGN	6990	1	1	100.00
CONT_ASSIGN	6992	1	1	100.00
CONT_ASSIGN	6997	1	1	100.00
CONT_ASSIGN	7002	1	1	100.00
CONT_ASSIGN	7007	1	1	100.00
CONT_ASSIGN	7012	1	1	100.00
CONT_ASSIGN	7017	1	1	100.00
ALWAYS	7035	44	44	100.00
ALWAYS	7083	52	52	100.00
CONT_ASSIGN	7239	1	1	100.00
ALWAYS	7241	39	39	100.00
CONT_ASSIGN	7367	1	1	100.00
CONT_ASSIGN	7368	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_reg_top.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
79	1	1
91	1	1
92	1	1
120	1	1
121	1	1
269	1	1
270	1	1
297	1	1
308	1	1
309	1	1
336	1	1
347	1	1
348	1	1
375	1	1
386	1	1
387	1	1
414	1	1
424	1	1
425	1	1
452	1	1
465	1	1
466	1	1
467	1	1
468	1	1
495	1	1
508	1	1
509	1	1
510	1	1
511	1	1
538	1	1
560	1	1
561	1	1
562	1	1
563	1	1
564	1	1
565	1	1
566	1	1
567	1	1
568	1	1
569	1	1
570	1	1
571	1	1
572	1	1
599	1	1
625	1	1
626	1	1
627	1	1
628	1	1
629	1	1
630	1	1
631	1	1
632	1	1
633	1	1
634	1	1
635	1	1
636	1	1
637	1	1
638	1	1
639	1	1
640	1	1
641	1	1
668	1	1
685	1	1
686	1	1
687	1	1
688	1	1
689	1	1
690	1	1
691	1	1
692	1	1
693	1	1
720	1	1
737	1	1
738	1	1
739	1	1
740	1	1
741	1	1
742	1	1
743	1	1
744	1	1
745	1	1
772	1	1
796	1	1
797	1	1
798	1	1
799	1	1
800	1	1
801	1	1
802	1	1
803	1	1
804	1	1
805	1	1
806	1	1
807	1	1
808	1	1
809	1	1
810	1	1
837	1	1
848	1	1
849	1	1
876	1	1
888	1	1
889	1	1
890	1	1
917	1	1
933	1	1
934	1	1
935	1	1
936	1	1
937	1	1
938	1	1
939	1	1
966	1	1
981	1	1
982	1	1
983	1	1
984	1	1
985	1	1
986	1	1
1013	1	1
1028	1	1
1029	1	1
1030	1	1
1031	1	1
1032	1	1
1033	1	1
1060	1	1
1075	1	1
1076	1	1
1077	1	1
1078	1	1
1079	1	1
1080	1	1
1107	1	1
1122	1	1
1123	1	1
1124	1	1
1125	1	1
1126	1	1
1127	1	1
1154	1	1
1165	1	1
1166	1	1
1193	1	1
1204	1	1
1205	1	1
1232	1	1
1243	1	1
1244	1	1
1271	1	1
1282	1	1
1283	1	1
1310	1	1
1325	1	1
1326	1	1
1327	1	1
1328	1	1
1329	1	1
1330	1	1
1357	1	1
1372	1	1
1373	1	1
1374	1	1
1375	1	1
1376	1	1
1377	1	1
1404	1	1
1419	1	1
1420	1	1
1421	1	1
1422	1	1
1423	1	1
1424	1	1
1451	1	1
1466	1	1
1467	1	1
1468	1	1
1469	1	1
1470	1	1
1471	1	1
1498	1	1
1509	1	1
1510	1	1
1537	1	1
1548	1	1
1549	1	1
1576	1	1
1587	1	1
1588	1	1
1615	1	1
1626	1	1
1627	1	1
1654	1	1
1668	1	1
1669	1	1
1670	1	1
1671	1	1
1672	1	1
1699	1	1
1713	1	1
1714	1	1
1715	1	1
1716	1	1
1717	1	1
1744	1	1
1758	1	1
1759	1	1
1760	1	1
1761	1	1
1762	1	1
1789	1	1
1803	1	1
1804	1	1
1805	1	1
1806	1	1
1807	1	1
1834	1	1
1853	1	1
1854	1	1
1855	1	1
1856	1	1
1857	1	1
1858	1	1
1859	1	1
1860	1	1
1861	1	1
1862	1	1
1889	1	1
1928	1	1
1929	1	1
1930	1	1
1931	1	1
1932	1	1
1933	1	1
1934	1	1
1935	1	1
1936	1	1
1937	1	1
1938	1	1
1939	1	1
1940	1	1
1941	1	1
1942	1	1
1943	1	1
1944	1	1
1945	1	1
1946	1	1
1947	1	1
1948	1	1
1949	1	1
1950	1	1
1951	1	1
1952	1	1
1953	1	1
1954	1	1
1955	1	1
1956	1	1
1957	1	1
1984	1	1
2047	1	1
2061	1	1
2067	1	1
2081	1	1
2115	1	1
2146	1	1
2178	1	1
2210	1	1
2269	1	1
2299	1	1
2330	1	1
2659	1	1
3750	1	1
4133	1	1
4165	1	1
4225	1	1
4394	1	1
4535	1	1
4676	1	1
4817	1	1
4958	1	1
4990	1	1
5022	1	1
5054	1	1
5086	1	1
5227	1	1
5368	1	1
5509	1	1
5650	1	1
5682	1	1
5714	1	1
5746	1	1
5778	1	1
5892	1	1
6006	1	1
6120	1	1
6232	1	1
6344	1	1
6727	1	1
6728	1	1
6729	1	1
6730	1	1
6731	1	1
6732	1	1
6733	1	1
6734	1	1
6735	1	1
6736	1	1
6737	1	1
6738	1	1
6739	1	1
6740	1	1
6741	1	1
6742	1	1
6743	1	1
6744	1	1
6745	1	1
6746	1	1
6747	1	1
6748	1	1
6749	1	1
6750	1	1
6751	1	1
6752	1	1
6753	1	1
6754	1	1
6755	1	1
6756	1	1
6757	1	1
6758	1	1
6759	1	1
6760	1	1
6761	1	1
6762	1	1
6763	1	1
6764	1	1
6765	1	1
6766	1	1
6767	1	1
6768	1	1
6769	1	1
6770	1	1
6773	1	1
6777	1	1
6824	1	1
6826	1	1
6827	1	1
6829	1	1
6830	1	1
6832	1	1
6833	1	1
6835	1	1
6836	1	1
6838	1	1
6839	1	1
6841	1	1
6843	1	1
6845	1	1
6847	1	1
6849	1	1
6851	1	1
6853	1	1
6866	1	1
6883	1	1
6892	1	1
6901	1	1
6916	1	1
6918	1	1
6921	1	1
6928	1	1
6934	1	1
6940	1	1
6946	1	1
6952	1	1
6954	1	1
6956	1	1
6958	1	1
6960	1	1
6966	1	1
6972	1	1
6978	1	1
6984	1	1
6986	1	1
6988	1	1
6990	1	1
6992	1	1
6997	1	1
7002	1	1
7007	1	1
7012	1	1
7017	1	1
7035	1	1
7036	1	1
7037	1	1
7038	1	1
7039	1	1
7040	1	1
7041	1	1
7042	1	1
7043	1	1
7044	1	1
7045	1	1
7046	1	1
7047	1	1
7048	1	1
7049	1	1
7050	1	1
7051	1	1
7052	1	1
7053	1	1
7054	1	1
7055	1	1
7056	1	1
7057	1	1
7058	1	1
7059	1	1
7060	1	1
7061	1	1
7062	1	1
7063	1	1
7064	1	1
7065	1	1
7066	1	1
7067	1	1
7068	1	1
7069	1	1
7070	1	1
7071	1	1
7072	1	1
7073	1	1
7074	1	1
7075	1	1
7076	1	1
7077	1	1
7078	1	1
7083	1	1
7084	1	1
7086	1	1
7090	1	1
7094	1	1
7098	1	1
7102	1	1
7106	1	1
7109	1	1
7112	1	1
7115	1	1
7118	1	1
7121	1	1
7124	1	1
7127	1	1
7130	1	1
7133	1	1
7136	1	1
7139	1	1
7140	1	1
7141	1	1
7142	1	1
7143	1	1
7144	1	1
7145	1	1
7146	1	1
7150	1	1
7153	1	1
7156	1	1
7159	1	1
7162	1	1
7165	1	1
7168	1	1
7171	1	1
7174	1	1
7177	1	1
7180	1	1
7183	1	1
7186	1	1
7189	1	1
7192	1	1
7195	1	1
7198	1	1
7201	1	1
7204	1	1
7207	1	1
7210	1	1
7213	1	1
7216	1	1
7219	1	1
7222	1	1
7225	1	1
7239	1	1
7241	1	1
7242	1	1
7244	1	1
7247	1	1
7250	1	1
7253	1	1
7256	1	1
7259	1	1
7262	1	1
7265	1	1
7268	1	1
7271	1	1
7274	1	1
7277	1	1
7280	1	1
7283	1	1
7286	1	1
7289	1	1
7292	1	1
7295	1	1
7298	1	1
7301	1	1
7304	1	1
7307	1	1
7310	1	1
7313	1	1
7316	1	1
7319	1	1
7322	1	1
7325	1	1
7328	1	1
7331	1	1
7334	1	1
7337	1	1
7340	1	1
7343	1	1
7346	1	1
7349	1	1
7352	1	1
7367	1	1
7368	1	1

---

Cond Coverage for Module : sysrst_ctrl_reg_top

	Total	Covered	Percent
Conditions	541	511	94.45
Logical	541	511	94.45
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
60-6847	92.70
6849-7239	100.00

---

Branch Coverage for Module : sysrst_ctrl_reg_top

	Line No.	Total	Covered	Percent
Branches		87	87	100.00
TERNARY	6773	2	2	100.00
IF	70	3	3	100.00
CASE	7084	44	44	100.00
CASE	7242	38	38	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_reg_top.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	6773	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T4,T5
0	1	Covered	T256,T257,T258
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	7084	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T4,T5
addr_hit[1]	Covered	T1,T4,T5
addr_hit[2]	Covered	T1,T4,T5
addr_hit[3]	Covered	T1,T4,T5
addr_hit[4]	Covered	T1,T4,T5
addr_hit[5]	Covered	T1,T4,T5
addr_hit[6]	Covered	T1,T4,T5
addr_hit[7]	Covered	T1,T4,T5
addr_hit[8]	Covered	T1,T4,T5
addr_hit[9]	Covered	T1,T4,T5
addr_hit[10]	Covered	T1,T4,T5
addr_hit[11]	Covered	T1,T4,T5
addr_hit[12]	Covered	T1,T4,T5
addr_hit[13]	Covered	T1,T4,T5
addr_hit[14]	Covered	T1,T4,T5
addr_hit[15]	Covered	T1,T4,T5
addr_hit[16]	Covered	T1,T4,T5
addr_hit[17]	Covered	T1,T4,T5
addr_hit[18]	Covered	T1,T4,T5
addr_hit[19]	Covered	T1,T4,T5
addr_hit[20]	Covered	T1,T4,T5
addr_hit[21]	Covered	T1,T4,T5
addr_hit[22]	Covered	T1,T4,T5
addr_hit[23]	Covered	T1,T4,T5
addr_hit[24]	Covered	T1,T4,T5
addr_hit[25]	Covered	T1,T4,T5
addr_hit[26]	Covered	T1,T4,T5
addr_hit[27]	Covered	T1,T4,T5
addr_hit[28]	Covered	T1,T4,T5
addr_hit[29]	Covered	T1,T4,T5
addr_hit[30]	Covered	T1,T4,T5
addr_hit[31]	Covered	T1,T4,T5
addr_hit[32]	Covered	T1,T4,T5
addr_hit[33]	Covered	T1,T4,T5
addr_hit[34]	Covered	T1,T4,T5
addr_hit[35]	Covered	T1,T4,T5
addr_hit[36]	Covered	T1,T4,T5
addr_hit[37]	Covered	T1,T4,T5
addr_hit[38]	Covered	T1,T4,T5
addr_hit[39]	Covered	T1,T4,T5
addr_hit[40]	Covered	T1,T4,T5
addr_hit[41]	Covered	T1,T4,T5
addr_hit[42]	Covered	T1,T4,T5
default	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	7242	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[5]	Covered	T1,T4,T5
addr_hit[6]	Covered	T1,T4,T5
addr_hit[7]	Covered	T1,T4,T5
addr_hit[8]	Covered	T1,T4,T5
addr_hit[9]	Covered	T1,T4,T5
addr_hit[10]	Covered	T1,T4,T5
addr_hit[11]	Covered	T1,T4,T5
addr_hit[12]	Covered	T1,T4,T5
addr_hit[13]	Covered	T1,T4,T5
addr_hit[14]	Covered	T1,T4,T5
addr_hit[15]	Covered	T1,T4,T5
addr_hit[17]	Covered	T1,T4,T5
addr_hit[18]	Covered	T1,T4,T5
addr_hit[19]	Covered	T1,T4,T5
addr_hit[20]	Covered	T1,T4,T5
addr_hit[21]	Covered	T1,T4,T5
addr_hit[22]	Covered	T1,T4,T5
addr_hit[23]	Covered	T1,T4,T5
addr_hit[24]	Covered	T1,T4,T5
addr_hit[25]	Covered	T1,T4,T5
addr_hit[26]	Covered	T1,T4,T5
addr_hit[27]	Covered	T1,T4,T5
addr_hit[28]	Covered	T1,T4,T5
addr_hit[29]	Covered	T1,T4,T5
addr_hit[30]	Covered	T1,T4,T5
addr_hit[31]	Covered	T1,T4,T5
addr_hit[32]	Covered	T1,T4,T5
addr_hit[33]	Covered	T1,T4,T5
addr_hit[34]	Covered	T1,T4,T5
addr_hit[35]	Covered	T1,T4,T5
addr_hit[36]	Covered	T1,T4,T5
addr_hit[37]	Covered	T1,T4,T5
addr_hit[38]	Covered	T1,T4,T5
addr_hit[39]	Covered	T1,T4,T5
addr_hit[40]	Covered	T1,T4,T5
addr_hit[41]	Covered	T1,T4,T5
addr_hit[42]	Covered	T1,T4,T5
default	Covered	T1,T4,T5

---

Assert Coverage for Module : sysrst_ctrl_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	1254870617	267703	0	0
reAfterRv	1254870617	267703	0	0
rePulse	1254870617	140859	0	0
wePulse	1254870617	126844	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	267703	0	0
T1	904145	524	0	0
T2	766221	1028	0	0
T4	176434	45	0	0
T5	346500	16	0	0
T24	222367	50	0	0
T25	82845	3	0	0
T26	68248	122	0	0
T27	50719	8	0	0
T28	482863	510	0	0
T29	74995	13	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	267703	0	0
T1	904145	524	0	0
T2	766221	1028	0	0
T4	176434	45	0	0
T5	346500	16	0	0
T24	222367	50	0	0
T25	82845	3	0	0
T26	68248	122	0	0
T27	50719	8	0	0
T28	482863	510	0	0
T29	74995	13	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	140859	0	0
T1	904145	401	0	0
T2	766221	452	0	0
T4	176434	22	0	0
T5	346500	8	0	0
T24	222367	49	0	0
T25	82845	2	0	0
T26	68248	62	0	0
T27	50719	2	0	0
T28	482863	390	0	0
T29	74995	2	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	126844	0	0
T1	904145	123	0	0
T2	766221	576	0	0
T4	176434	23	0	0
T5	346500	8	0	0
T24	222367	1	0	0
T25	82845	1	0	0
T26	68248	60	0	0
T27	50719	6	0	0
T28	482863	120	0	0
T29	74995	11	0	0

Line Coverage for Instance : tb.dut.u_reg

	Line No.	Total	Covered	Percent
TOTAL		532	532	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
ALWAYS	269	2	2	100.00
CONT_ASSIGN	297	1	1	100.00
ALWAYS	308	2	2	100.00
CONT_ASSIGN	336	1	1	100.00
ALWAYS	347	2	2	100.00
CONT_ASSIGN	375	1	1	100.00
ALWAYS	386	2	2	100.00
CONT_ASSIGN	414	1	1	100.00
ALWAYS	424	2	2	100.00
CONT_ASSIGN	452	1	1	100.00
ALWAYS	465	4	4	100.00
CONT_ASSIGN	495	1	1	100.00
ALWAYS	508	4	4	100.00
CONT_ASSIGN	538	1	1	100.00
ALWAYS	560	13	13	100.00
CONT_ASSIGN	599	1	1	100.00
ALWAYS	625	17	17	100.00
CONT_ASSIGN	668	1	1	100.00
ALWAYS	685	9	9	100.00
CONT_ASSIGN	720	1	1	100.00
ALWAYS	737	9	9	100.00
CONT_ASSIGN	772	1	1	100.00
ALWAYS	796	15	15	100.00
CONT_ASSIGN	837	1	1	100.00
ALWAYS	848	2	2	100.00
CONT_ASSIGN	876	1	1	100.00
ALWAYS	888	3	3	100.00
CONT_ASSIGN	917	1	1	100.00
ALWAYS	933	7	7	100.00
CONT_ASSIGN	966	1	1	100.00
ALWAYS	981	6	6	100.00
CONT_ASSIGN	1013	1	1	100.00
ALWAYS	1028	6	6	100.00
CONT_ASSIGN	1060	1	1	100.00
ALWAYS	1075	6	6	100.00
CONT_ASSIGN	1107	1	1	100.00
ALWAYS	1122	6	6	100.00
CONT_ASSIGN	1154	1	1	100.00
ALWAYS	1165	2	2	100.00
CONT_ASSIGN	1193	1	1	100.00
ALWAYS	1204	2	2	100.00
CONT_ASSIGN	1232	1	1	100.00
ALWAYS	1243	2	2	100.00
CONT_ASSIGN	1271	1	1	100.00
ALWAYS	1282	2	2	100.00
CONT_ASSIGN	1310	1	1	100.00
ALWAYS	1325	6	6	100.00
CONT_ASSIGN	1357	1	1	100.00
ALWAYS	1372	6	6	100.00
CONT_ASSIGN	1404	1	1	100.00
ALWAYS	1419	6	6	100.00
CONT_ASSIGN	1451	1	1	100.00
ALWAYS	1466	6	6	100.00
CONT_ASSIGN	1498	1	1	100.00
ALWAYS	1509	2	2	100.00
CONT_ASSIGN	1537	1	1	100.00
ALWAYS	1548	2	2	100.00
CONT_ASSIGN	1576	1	1	100.00
ALWAYS	1587	2	2	100.00
CONT_ASSIGN	1615	1	1	100.00
ALWAYS	1626	2	2	100.00
CONT_ASSIGN	1654	1	1	100.00
ALWAYS	1668	5	5	100.00
CONT_ASSIGN	1699	1	1	100.00
ALWAYS	1713	5	5	100.00
CONT_ASSIGN	1744	1	1	100.00
ALWAYS	1758	5	5	100.00
CONT_ASSIGN	1789	1	1	100.00
ALWAYS	1803	5	5	100.00
CONT_ASSIGN	1834	1	1	100.00
ALWAYS	1853	10	10	100.00
CONT_ASSIGN	1889	1	1	100.00
ALWAYS	1928	30	30	100.00
CONT_ASSIGN	1984	1	1	100.00
CONT_ASSIGN	2047	1	1	100.00
CONT_ASSIGN	2061	1	1	100.00
CONT_ASSIGN	2067	1	1	100.00
CONT_ASSIGN	2081	1	1	100.00
CONT_ASSIGN	2115	1	1	100.00
CONT_ASSIGN	2146	1	1	100.00
CONT_ASSIGN	2178	1	1	100.00
CONT_ASSIGN	2210	1	1	100.00
CONT_ASSIGN	2269	1	1	100.00
CONT_ASSIGN	2299	1	1	100.00
CONT_ASSIGN	2330	1	1	100.00
CONT_ASSIGN	2659	1	1	100.00
CONT_ASSIGN	3750	1	1	100.00
CONT_ASSIGN	4133	1	1	100.00
CONT_ASSIGN	4165	1	1	100.00
CONT_ASSIGN	4225	1	1	100.00
CONT_ASSIGN	4394	1	1	100.00
CONT_ASSIGN	4535	1	1	100.00
CONT_ASSIGN	4676	1	1	100.00
CONT_ASSIGN	4817	1	1	100.00
CONT_ASSIGN	4958	1	1	100.00
CONT_ASSIGN	4990	1	1	100.00
CONT_ASSIGN	5022	1	1	100.00
CONT_ASSIGN	5054	1	1	100.00
CONT_ASSIGN	5086	1	1	100.00
CONT_ASSIGN	5227	1	1	100.00
CONT_ASSIGN	5368	1	1	100.00
CONT_ASSIGN	5509	1	1	100.00
CONT_ASSIGN	5650	1	1	100.00
CONT_ASSIGN	5682	1	1	100.00
CONT_ASSIGN	5714	1	1	100.00
CONT_ASSIGN	5746	1	1	100.00
CONT_ASSIGN	5778	1	1	100.00
CONT_ASSIGN	5892	1	1	100.00
CONT_ASSIGN	6006	1	1	100.00
CONT_ASSIGN	6120	1	1	100.00
CONT_ASSIGN	6232	1	1	100.00
CONT_ASSIGN	6344	1	1	100.00
ALWAYS	6727	44	44	100.00
CONT_ASSIGN	6773	1	1	100.00
ALWAYS	6777	1	1	100.00
CONT_ASSIGN	6824	1	1	100.00
CONT_ASSIGN	6826	1	1	100.00
CONT_ASSIGN	6827	1	1	100.00
CONT_ASSIGN	6829	1	1	100.00
CONT_ASSIGN	6830	1	1	100.00
CONT_ASSIGN	6832	1	1	100.00
CONT_ASSIGN	6833	1	1	100.00
CONT_ASSIGN	6835	1	1	100.00
CONT_ASSIGN	6836	1	1	100.00
CONT_ASSIGN	6838	1	1	100.00
CONT_ASSIGN	6839	1	1	100.00
CONT_ASSIGN	6841	1	1	100.00
CONT_ASSIGN	6843	1	1	100.00
CONT_ASSIGN	6845	1	1	100.00
CONT_ASSIGN	6847	1	1	100.00
CONT_ASSIGN	6849	1	1	100.00
CONT_ASSIGN	6851	1	1	100.00
CONT_ASSIGN	6853	1	1	100.00
CONT_ASSIGN	6866	1	1	100.00
CONT_ASSIGN	6883	1	1	100.00
CONT_ASSIGN	6892	1	1	100.00
CONT_ASSIGN	6901	1	1	100.00
CONT_ASSIGN	6916	1	1	100.00
CONT_ASSIGN	6918	1	1	100.00
CONT_ASSIGN	6921	1	1	100.00
CONT_ASSIGN	6928	1	1	100.00
CONT_ASSIGN	6934	1	1	100.00
CONT_ASSIGN	6940	1	1	100.00
CONT_ASSIGN	6946	1	1	100.00
CONT_ASSIGN	6952	1	1	100.00
CONT_ASSIGN	6954	1	1	100.00
CONT_ASSIGN	6956	1	1	100.00
CONT_ASSIGN	6958	1	1	100.00
CONT_ASSIGN	6960	1	1	100.00
CONT_ASSIGN	6966	1	1	100.00
CONT_ASSIGN	6972	1	1	100.00
CONT_ASSIGN	6978	1	1	100.00
CONT_ASSIGN	6984	1	1	100.00
CONT_ASSIGN	6986	1	1	100.00
CONT_ASSIGN	6988	1	1	100.00
CONT_ASSIGN	6990	1	1	100.00
CONT_ASSIGN	6992	1	1	100.00
CONT_ASSIGN	6997	1	1	100.00
CONT_ASSIGN	7002	1	1	100.00
CONT_ASSIGN	7007	1	1	100.00
CONT_ASSIGN	7012	1	1	100.00
CONT_ASSIGN	7017	1	1	100.00
ALWAYS	7035	44	44	100.00
ALWAYS	7083	52	52	100.00
CONT_ASSIGN	7239	1	1	100.00
ALWAYS	7241	39	39	100.00
CONT_ASSIGN	7367	1	1	100.00
CONT_ASSIGN	7368	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_reg_top.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
79	1	1
91	1	1
92	1	1
120	1	1
121	1	1
269	1	1
270	1	1
297	1	1
308	1	1
309	1	1
336	1	1
347	1	1
348	1	1
375	1	1
386	1	1
387	1	1
414	1	1
424	1	1
425	1	1
452	1	1
465	1	1
466	1	1
467	1	1
468	1	1
495	1	1
508	1	1
509	1	1
510	1	1
511	1	1
538	1	1
560	1	1
561	1	1
562	1	1
563	1	1
564	1	1
565	1	1
566	1	1
567	1	1
568	1	1
569	1	1
570	1	1
571	1	1
572	1	1
599	1	1
625	1	1
626	1	1
627	1	1
628	1	1
629	1	1
630	1	1
631	1	1
632	1	1
633	1	1
634	1	1
635	1	1
636	1	1
637	1	1
638	1	1
639	1	1
640	1	1
641	1	1
668	1	1
685	1	1
686	1	1
687	1	1
688	1	1
689	1	1
690	1	1
691	1	1
692	1	1
693	1	1
720	1	1
737	1	1
738	1	1
739	1	1
740	1	1
741	1	1
742	1	1
743	1	1
744	1	1
745	1	1
772	1	1
796	1	1
797	1	1
798	1	1
799	1	1
800	1	1
801	1	1
802	1	1
803	1	1
804	1	1
805	1	1
806	1	1
807	1	1
808	1	1
809	1	1
810	1	1
837	1	1
848	1	1
849	1	1
876	1	1
888	1	1
889	1	1
890	1	1
917	1	1
933	1	1
934	1	1
935	1	1
936	1	1
937	1	1
938	1	1
939	1	1
966	1	1
981	1	1
982	1	1
983	1	1
984	1	1
985	1	1
986	1	1
1013	1	1
1028	1	1
1029	1	1
1030	1	1
1031	1	1
1032	1	1
1033	1	1
1060	1	1
1075	1	1
1076	1	1
1077	1	1
1078	1	1
1079	1	1
1080	1	1
1107	1	1
1122	1	1
1123	1	1
1124	1	1
1125	1	1
1126	1	1
1127	1	1
1154	1	1
1165	1	1
1166	1	1
1193	1	1
1204	1	1
1205	1	1
1232	1	1
1243	1	1
1244	1	1
1271	1	1
1282	1	1
1283	1	1
1310	1	1
1325	1	1
1326	1	1
1327	1	1
1328	1	1
1329	1	1
1330	1	1
1357	1	1
1372	1	1
1373	1	1
1374	1	1
1375	1	1
1376	1	1
1377	1	1
1404	1	1
1419	1	1
1420	1	1
1421	1	1
1422	1	1
1423	1	1
1424	1	1
1451	1	1
1466	1	1
1467	1	1
1468	1	1
1469	1	1
1470	1	1
1471	1	1
1498	1	1
1509	1	1
1510	1	1
1537	1	1
1548	1	1
1549	1	1
1576	1	1
1587	1	1
1588	1	1
1615	1	1
1626	1	1
1627	1	1
1654	1	1
1668	1	1
1669	1	1
1670	1	1
1671	1	1
1672	1	1
1699	1	1
1713	1	1
1714	1	1
1715	1	1
1716	1	1
1717	1	1
1744	1	1
1758	1	1
1759	1	1
1760	1	1
1761	1	1
1762	1	1
1789	1	1
1803	1	1
1804	1	1
1805	1	1
1806	1	1
1807	1	1
1834	1	1
1853	1	1
1854	1	1
1855	1	1
1856	1	1
1857	1	1
1858	1	1
1859	1	1
1860	1	1
1861	1	1
1862	1	1
1889	1	1
1928	1	1
1929	1	1
1930	1	1
1931	1	1
1932	1	1
1933	1	1
1934	1	1
1935	1	1
1936	1	1
1937	1	1
1938	1	1
1939	1	1
1940	1	1
1941	1	1
1942	1	1
1943	1	1
1944	1	1
1945	1	1
1946	1	1
1947	1	1
1948	1	1
1949	1	1
1950	1	1
1951	1	1
1952	1	1
1953	1	1
1954	1	1
1955	1	1
1956	1	1
1957	1	1
1984	1	1
2047	1	1
2061	1	1
2067	1	1
2081	1	1
2115	1	1
2146	1	1
2178	1	1
2210	1	1
2269	1	1
2299	1	1
2330	1	1
2659	1	1
3750	1	1
4133	1	1
4165	1	1
4225	1	1
4394	1	1
4535	1	1
4676	1	1
4817	1	1
4958	1	1
4990	1	1
5022	1	1
5054	1	1
5086	1	1
5227	1	1
5368	1	1
5509	1	1
5650	1	1
5682	1	1
5714	1	1
5746	1	1
5778	1	1
5892	1	1
6006	1	1
6120	1	1
6232	1	1
6344	1	1
6727	1	1
6728	1	1
6729	1	1
6730	1	1
6731	1	1
6732	1	1
6733	1	1
6734	1	1
6735	1	1
6736	1	1
6737	1	1
6738	1	1
6739	1	1
6740	1	1
6741	1	1
6742	1	1
6743	1	1
6744	1	1
6745	1	1
6746	1	1
6747	1	1
6748	1	1
6749	1	1
6750	1	1
6751	1	1
6752	1	1
6753	1	1
6754	1	1
6755	1	1
6756	1	1
6757	1	1
6758	1	1
6759	1	1
6760	1	1
6761	1	1
6762	1	1
6763	1	1
6764	1	1
6765	1	1
6766	1	1
6767	1	1
6768	1	1
6769	1	1
6770	1	1
6773	1	1
6777	1	1
6824	1	1
6826	1	1
6827	1	1
6829	1	1
6830	1	1
6832	1	1
6833	1	1
6835	1	1
6836	1	1
6838	1	1
6839	1	1
6841	1	1
6843	1	1
6845	1	1
6847	1	1
6849	1	1
6851	1	1
6853	1	1
6866	1	1
6883	1	1
6892	1	1
6901	1	1
6916	1	1
6918	1	1
6921	1	1
6928	1	1
6934	1	1
6940	1	1
6946	1	1
6952	1	1
6954	1	1
6956	1	1
6958	1	1
6960	1	1
6966	1	1
6972	1	1
6978	1	1
6984	1	1
6986	1	1
6988	1	1
6990	1	1
6992	1	1
6997	1	1
7002	1	1
7007	1	1
7012	1	1
7017	1	1
7035	1	1
7036	1	1
7037	1	1
7038	1	1
7039	1	1
7040	1	1
7041	1	1
7042	1	1
7043	1	1
7044	1	1
7045	1	1
7046	1	1
7047	1	1
7048	1	1
7049	1	1
7050	1	1
7051	1	1
7052	1	1
7053	1	1
7054	1	1
7055	1	1
7056	1	1
7057	1	1
7058	1	1
7059	1	1
7060	1	1
7061	1	1
7062	1	1
7063	1	1
7064	1	1
7065	1	1
7066	1	1
7067	1	1
7068	1	1
7069	1	1
7070	1	1
7071	1	1
7072	1	1
7073	1	1
7074	1	1
7075	1	1
7076	1	1
7077	1	1
7078	1	1
7083	1	1
7084	1	1
7086	1	1
7090	1	1
7094	1	1
7098	1	1
7102	1	1
7106	1	1
7109	1	1
7112	1	1
7115	1	1
7118	1	1
7121	1	1
7124	1	1
7127	1	1
7130	1	1
7133	1	1
7136	1	1
7139	1	1
7140	1	1
7141	1	1
7142	1	1
7143	1	1
7144	1	1
7145	1	1
7146	1	1
7150	1	1
7153	1	1
7156	1	1
7159	1	1
7162	1	1
7165	1	1
7168	1	1
7171	1	1
7174	1	1
7177	1	1
7180	1	1
7183	1	1
7186	1	1
7189	1	1
7192	1	1
7195	1	1
7198	1	1
7201	1	1
7204	1	1
7207	1	1
7210	1	1
7213	1	1
7216	1	1
7219	1	1
7222	1	1
7225	1	1
7239	1	1
7241	1	1
7242	1	1
7244	1	1
7247	1	1
7250	1	1
7253	1	1
7256	1	1
7259	1	1
7262	1	1
7265	1	1
7268	1	1
7271	1	1
7274	1	1
7277	1	1
7280	1	1
7283	1	1
7286	1	1
7289	1	1
7292	1	1
7295	1	1
7298	1	1
7301	1	1
7304	1	1
7307	1	1
7310	1	1
7313	1	1
7316	1	1
7319	1	1
7322	1	1
7325	1	1
7328	1	1
7331	1	1
7334	1	1
7337	1	1
7340	1	1
7343	1	1
7346	1	1
7349	1	1
7352	1	1
7367	1	1
7368	1	1

---

Cond Coverage for Instance : tb.dut.u_reg

	Total	Covered	Percent
Conditions	540	510	94.44
Logical	540	510	94.44
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
60-6847	92.68
6849-7239	100.00

---

Branch Coverage for Instance : tb.dut.u_reg

	Line No.	Total	Covered	Percent
Branches		87	87	100.00
TERNARY	6773	2	2	100.00
IF	70	3	3	100.00
CASE	7084	44	44	100.00
CASE	7242	38	38	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_reg_top.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	6773	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T4,T5
0	1	Covered	T256,T257,T258
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	7084	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T4,T5
addr_hit[1]	Covered	T1,T4,T5
addr_hit[2]	Covered	T1,T4,T5
addr_hit[3]	Covered	T1,T4,T5
addr_hit[4]	Covered	T1,T4,T5
addr_hit[5]	Covered	T1,T4,T5
addr_hit[6]	Covered	T1,T4,T5
addr_hit[7]	Covered	T1,T4,T5
addr_hit[8]	Covered	T1,T4,T5
addr_hit[9]	Covered	T1,T4,T5
addr_hit[10]	Covered	T1,T4,T5
addr_hit[11]	Covered	T1,T4,T5
addr_hit[12]	Covered	T1,T4,T5
addr_hit[13]	Covered	T1,T4,T5
addr_hit[14]	Covered	T1,T4,T5
addr_hit[15]	Covered	T1,T4,T5
addr_hit[16]	Covered	T1,T4,T5
addr_hit[17]	Covered	T1,T4,T5
addr_hit[18]	Covered	T1,T4,T5
addr_hit[19]	Covered	T1,T4,T5
addr_hit[20]	Covered	T1,T4,T5
addr_hit[21]	Covered	T1,T4,T5
addr_hit[22]	Covered	T1,T4,T5
addr_hit[23]	Covered	T1,T4,T5
addr_hit[24]	Covered	T1,T4,T5
addr_hit[25]	Covered	T1,T4,T5
addr_hit[26]	Covered	T1,T4,T5
addr_hit[27]	Covered	T1,T4,T5
addr_hit[28]	Covered	T1,T4,T5
addr_hit[29]	Covered	T1,T4,T5
addr_hit[30]	Covered	T1,T4,T5
addr_hit[31]	Covered	T1,T4,T5
addr_hit[32]	Covered	T1,T4,T5
addr_hit[33]	Covered	T1,T4,T5
addr_hit[34]	Covered	T1,T4,T5
addr_hit[35]	Covered	T1,T4,T5
addr_hit[36]	Covered	T1,T4,T5
addr_hit[37]	Covered	T1,T4,T5
addr_hit[38]	Covered	T1,T4,T5
addr_hit[39]	Covered	T1,T4,T5
addr_hit[40]	Covered	T1,T4,T5
addr_hit[41]	Covered	T1,T4,T5
addr_hit[42]	Covered	T1,T4,T5
default	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	7242	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[5]	Covered	T1,T4,T5
addr_hit[6]	Covered	T1,T4,T5
addr_hit[7]	Covered	T1,T4,T5
addr_hit[8]	Covered	T1,T4,T5
addr_hit[9]	Covered	T1,T4,T5
addr_hit[10]	Covered	T1,T4,T5
addr_hit[11]	Covered	T1,T4,T5
addr_hit[12]	Covered	T1,T4,T5
addr_hit[13]	Covered	T1,T4,T5
addr_hit[14]	Covered	T1,T4,T5
addr_hit[15]	Covered	T1,T4,T5
addr_hit[17]	Covered	T1,T4,T5
addr_hit[18]	Covered	T1,T4,T5
addr_hit[19]	Covered	T1,T4,T5
addr_hit[20]	Covered	T1,T4,T5
addr_hit[21]	Covered	T1,T4,T5
addr_hit[22]	Covered	T1,T4,T5
addr_hit[23]	Covered	T1,T4,T5
addr_hit[24]	Covered	T1,T4,T5
addr_hit[25]	Covered	T1,T4,T5
addr_hit[26]	Covered	T1,T4,T5
addr_hit[27]	Covered	T1,T4,T5
addr_hit[28]	Covered	T1,T4,T5
addr_hit[29]	Covered	T1,T4,T5
addr_hit[30]	Covered	T1,T4,T5
addr_hit[31]	Covered	T1,T4,T5
addr_hit[32]	Covered	T1,T4,T5
addr_hit[33]	Covered	T1,T4,T5
addr_hit[34]	Covered	T1,T4,T5
addr_hit[35]	Covered	T1,T4,T5
addr_hit[36]	Covered	T1,T4,T5
addr_hit[37]	Covered	T1,T4,T5
addr_hit[38]	Covered	T1,T4,T5
addr_hit[39]	Covered	T1,T4,T5
addr_hit[40]	Covered	T1,T4,T5
addr_hit[41]	Covered	T1,T4,T5
addr_hit[42]	Covered	T1,T4,T5
default	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_reg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	1254870617	267703	0	0
reAfterRv	1254870617	267703	0	0
rePulse	1254870617	140859	0	0
wePulse	1254870617	126844	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	267703	0	0
T1	904145	524	0	0
T2	766221	1028	0	0
T4	176434	45	0	0
T5	346500	16	0	0
T24	222367	50	0	0
T25	82845	3	0	0
T26	68248	122	0	0
T27	50719	8	0	0
T28	482863	510	0	0
T29	74995	13	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	267703	0	0
T1	904145	524	0	0
T2	766221	1028	0	0
T4	176434	45	0	0
T5	346500	16	0	0
T24	222367	50	0	0
T25	82845	3	0	0
T26	68248	122	0	0
T27	50719	8	0	0
T28	482863	510	0	0
T29	74995	13	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	140859	0	0
T1	904145	401	0	0
T2	766221	452	0	0
T4	176434	22	0	0
T5	346500	8	0	0
T24	222367	49	0	0
T25	82845	2	0	0
T26	68248	62	0	0
T27	50719	2	0	0
T28	482863	390	0	0
T29	74995	2	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	1254870617	126844	0	0
T1	904145	123	0	0
T2	766221	576	0	0
T4	176434	23	0	0
T5	346500	8	0	0
T24	222367	1	0	0
T25	82845	1	0	0
T26	68248	60	0	0
T27	50719	6	0	0
T28	482863	120	0	0
T29	74995	11	0	0