Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
884 |
1 |
|
|
T25 |
8 |
|
T10 |
8 |
|
T50 |
12 |
| auto[1] |
856 |
1 |
|
|
T25 |
12 |
|
T10 |
12 |
|
T50 |
8 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
897 |
1 |
|
|
T25 |
7 |
|
T10 |
13 |
|
T50 |
11 |
| auto[1] |
843 |
1 |
|
|
T25 |
13 |
|
T10 |
7 |
|
T50 |
9 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
866 |
1 |
|
|
T25 |
12 |
|
T10 |
12 |
|
T50 |
13 |
| auto[1] |
874 |
1 |
|
|
T25 |
8 |
|
T10 |
8 |
|
T50 |
7 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
899 |
1 |
|
|
T25 |
6 |
|
T10 |
11 |
|
T50 |
12 |
| auto[1] |
841 |
1 |
|
|
T25 |
14 |
|
T10 |
9 |
|
T50 |
8 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
876 |
1 |
|
|
T25 |
11 |
|
T10 |
9 |
|
T50 |
11 |
| auto[1] |
864 |
1 |
|
|
T25 |
9 |
|
T10 |
11 |
|
T50 |
9 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
898 |
1 |
|
|
T25 |
7 |
|
T10 |
7 |
|
T50 |
13 |
| auto[1] |
842 |
1 |
|
|
T25 |
13 |
|
T10 |
13 |
|
T50 |
7 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
877 |
1 |
|
|
T25 |
14 |
|
T10 |
7 |
|
T50 |
9 |
| auto[1] |
863 |
1 |
|
|
T25 |
6 |
|
T10 |
13 |
|
T50 |
11 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
851 |
1 |
|
|
T25 |
10 |
|
T10 |
12 |
|
T50 |
10 |
| auto[1] |
889 |
1 |
|
|
T25 |
10 |
|
T10 |
8 |
|
T50 |
10 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
897 |
1 |
|
|
T25 |
16 |
|
T10 |
8 |
|
T50 |
12 |
| auto[1] |
843 |
1 |
|
|
T25 |
4 |
|
T10 |
12 |
|
T50 |
8 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
859 |
1 |
|
|
T25 |
14 |
|
T10 |
11 |
|
T50 |
6 |
| auto[1] |
881 |
1 |
|
|
T25 |
6 |
|
T10 |
9 |
|
T50 |
14 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
894 |
1 |
|
|
T25 |
15 |
|
T10 |
10 |
|
T50 |
8 |
| auto[1] |
846 |
1 |
|
|
T25 |
5 |
|
T10 |
10 |
|
T50 |
12 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
895 |
1 |
|
|
T25 |
12 |
|
T10 |
12 |
|
T50 |
7 |
| auto[1] |
845 |
1 |
|
|
T25 |
8 |
|
T10 |
8 |
|
T50 |
13 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
890 |
1 |
|
|
T25 |
9 |
|
T10 |
10 |
|
T50 |
8 |
| auto[1] |
850 |
1 |
|
|
T25 |
11 |
|
T10 |
10 |
|
T50 |
12 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
897 |
1 |
|
|
T25 |
7 |
|
T10 |
13 |
|
T50 |
11 |
| auto[1] |
843 |
1 |
|
|
T25 |
13 |
|
T10 |
7 |
|
T50 |
9 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
833 |
1 |
|
|
T25 |
12 |
|
T10 |
9 |
|
T50 |
8 |
| auto[1] |
907 |
1 |
|
|
T25 |
8 |
|
T10 |
11 |
|
T50 |
12 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
852 |
1 |
|
|
T25 |
12 |
|
T10 |
12 |
|
T50 |
9 |
| auto[1] |
888 |
1 |
|
|
T25 |
8 |
|
T10 |
8 |
|
T50 |
11 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
850 |
1 |
|
|
T25 |
14 |
|
T10 |
13 |
|
T50 |
10 |
| auto[1] |
890 |
1 |
|
|
T25 |
6 |
|
T10 |
7 |
|
T50 |
10 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
858 |
1 |
|
|
T25 |
14 |
|
T10 |
11 |
|
T50 |
8 |
| auto[1] |
882 |
1 |
|
|
T25 |
6 |
|
T10 |
9 |
|
T50 |
12 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
836 |
1 |
|
|
T25 |
12 |
|
T10 |
12 |
|
T50 |
10 |
| auto[1] |
904 |
1 |
|
|
T25 |
8 |
|
T10 |
8 |
|
T50 |
10 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
904 |
1 |
|
|
T25 |
8 |
|
T10 |
11 |
|
T50 |
11 |
| auto[1] |
836 |
1 |
|
|
T25 |
12 |
|
T10 |
9 |
|
T50 |
9 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
878 |
1 |
|
|
T25 |
11 |
|
T10 |
10 |
|
T50 |
10 |
| auto[1] |
862 |
1 |
|
|
T25 |
9 |
|
T10 |
10 |
|
T50 |
10 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
893 |
1 |
|
|
T25 |
11 |
|
T10 |
11 |
|
T50 |
14 |
| auto[1] |
847 |
1 |
|
|
T25 |
9 |
|
T10 |
9 |
|
T50 |
6 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
874 |
1 |
|
|
T25 |
8 |
|
T10 |
10 |
|
T50 |
16 |
| auto[1] |
866 |
1 |
|
|
T25 |
12 |
|
T10 |
10 |
|
T50 |
4 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
895 |
1 |
|
|
T25 |
12 |
|
T10 |
12 |
|
T50 |
7 |
| auto[1] |
845 |
1 |
|
|
T25 |
8 |
|
T10 |
8 |
|
T50 |
13 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
414 |
1 |
|
|
T25 |
6 |
|
T10 |
6 |
|
T50 |
6 |
| auto[0] |
auto[1] |
419 |
1 |
|
|
T25 |
6 |
|
T10 |
3 |
|
T50 |
2 |
| auto[1] |
auto[0] |
452 |
1 |
|
|
T25 |
6 |
|
T10 |
6 |
|
T50 |
7 |
| auto[1] |
auto[1] |
455 |
1 |
|
|
T25 |
2 |
|
T10 |
5 |
|
T50 |
5 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
440 |
1 |
|
|
T25 |
3 |
|
T10 |
7 |
|
T50 |
6 |
| auto[0] |
auto[1] |
412 |
1 |
|
|
T25 |
9 |
|
T10 |
5 |
|
T50 |
3 |
| auto[1] |
auto[0] |
459 |
1 |
|
|
T25 |
3 |
|
T10 |
4 |
|
T50 |
6 |
| auto[1] |
auto[1] |
429 |
1 |
|
|
T25 |
5 |
|
T10 |
4 |
|
T50 |
5 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
433 |
1 |
|
|
T25 |
8 |
|
T10 |
8 |
|
T50 |
6 |
| auto[0] |
auto[1] |
417 |
1 |
|
|
T25 |
6 |
|
T10 |
5 |
|
T50 |
4 |
| auto[1] |
auto[0] |
443 |
1 |
|
|
T25 |
3 |
|
T10 |
1 |
|
T50 |
5 |
| auto[1] |
auto[1] |
447 |
1 |
|
|
T25 |
3 |
|
T10 |
6 |
|
T50 |
5 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
448 |
1 |
|
|
T25 |
6 |
|
T10 |
6 |
|
T50 |
6 |
| auto[0] |
auto[1] |
410 |
1 |
|
|
T25 |
8 |
|
T10 |
5 |
|
T50 |
2 |
| auto[1] |
auto[0] |
450 |
1 |
|
|
T25 |
1 |
|
T10 |
1 |
|
T50 |
7 |
| auto[1] |
auto[1] |
432 |
1 |
|
|
T25 |
5 |
|
T10 |
8 |
|
T50 |
5 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
425 |
1 |
|
|
T25 |
8 |
|
T10 |
5 |
|
T50 |
3 |
| auto[0] |
auto[1] |
411 |
1 |
|
|
T25 |
4 |
|
T10 |
7 |
|
T50 |
7 |
| auto[1] |
auto[0] |
452 |
1 |
|
|
T25 |
6 |
|
T10 |
2 |
|
T50 |
6 |
| auto[1] |
auto[1] |
452 |
1 |
|
|
T25 |
2 |
|
T10 |
6 |
|
T50 |
4 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
446 |
1 |
|
|
T25 |
4 |
|
T10 |
7 |
|
T50 |
4 |
| auto[0] |
auto[1] |
458 |
1 |
|
|
T25 |
4 |
|
T10 |
4 |
|
T50 |
7 |
| auto[1] |
auto[0] |
405 |
1 |
|
|
T25 |
6 |
|
T10 |
5 |
|
T50 |
6 |
| auto[1] |
auto[1] |
431 |
1 |
|
|
T25 |
6 |
|
T10 |
4 |
|
T50 |
3 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
433 |
1 |
|
|
T25 |
7 |
|
T10 |
6 |
|
T50 |
3 |
| auto[0] |
auto[1] |
460 |
1 |
|
|
T25 |
4 |
|
T10 |
5 |
|
T50 |
11 |
| auto[1] |
auto[0] |
426 |
1 |
|
|
T25 |
7 |
|
T10 |
5 |
|
T50 |
3 |
| auto[1] |
auto[1] |
421 |
1 |
|
|
T25 |
2 |
|
T10 |
4 |
|
T50 |
3 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
441 |
1 |
|
|
T25 |
6 |
|
T10 |
5 |
|
T50 |
5 |
| auto[0] |
auto[1] |
433 |
1 |
|
|
T25 |
2 |
|
T10 |
5 |
|
T50 |
11 |
| auto[1] |
auto[0] |
453 |
1 |
|
|
T25 |
9 |
|
T10 |
5 |
|
T50 |
3 |
| auto[1] |
auto[1] |
413 |
1 |
|
|
T25 |
3 |
|
T10 |
5 |
|
T50 |
1 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
456 |
1 |
|
|
T25 |
4 |
|
T10 |
3 |
|
T50 |
4 |
| auto[0] |
auto[1] |
434 |
1 |
|
|
T25 |
5 |
|
T10 |
7 |
|
T50 |
4 |
| auto[1] |
auto[0] |
428 |
1 |
|
|
T25 |
4 |
|
T10 |
5 |
|
T50 |
8 |
| auto[1] |
auto[1] |
422 |
1 |
|
|
T25 |
7 |
|
T10 |
5 |
|
T50 |
4 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
897 |
1 |
|
|
T25 |
7 |
|
T10 |
13 |
|
T50 |
11 |
| auto[1] |
auto[1] |
843 |
1 |
|
|
T25 |
13 |
|
T10 |
7 |
|
T50 |
9 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
470 |
1 |
|
|
T25 |
9 |
|
T10 |
4 |
|
T50 |
7 |
| auto[0] |
auto[1] |
408 |
1 |
|
|
T25 |
2 |
|
T10 |
6 |
|
T50 |
3 |
| auto[1] |
auto[0] |
427 |
1 |
|
|
T25 |
7 |
|
T10 |
4 |
|
T50 |
5 |
| auto[1] |
auto[1] |
435 |
1 |
|
|
T25 |
2 |
|
T10 |
6 |
|
T50 |
5 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
895 |
1 |
|
|
T25 |
12 |
|
T10 |
12 |
|
T50 |
7 |
| auto[1] |
auto[1] |
845 |
1 |
|
|
T25 |
8 |
|
T10 |
8 |
|
T50 |
13 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
128 |
1 |
|
|
T65 |
13 |
|
T22 |
10 |
|
T154 |
10 |
| auto[1] |
112 |
1 |
|
|
T65 |
7 |
|
T22 |
10 |
|
T154 |
10 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
125 |
1 |
|
|
T65 |
8 |
|
T22 |
17 |
|
T154 |
8 |
| auto[1] |
115 |
1 |
|
|
T65 |
12 |
|
T22 |
3 |
|
T154 |
12 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
122 |
1 |
|
|
T65 |
11 |
|
T22 |
11 |
|
T154 |
6 |
| auto[1] |
118 |
1 |
|
|
T65 |
9 |
|
T22 |
9 |
|
T154 |
14 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
123 |
1 |
|
|
T65 |
6 |
|
T22 |
10 |
|
T154 |
12 |
| auto[1] |
117 |
1 |
|
|
T65 |
14 |
|
T22 |
10 |
|
T154 |
8 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
128 |
1 |
|
|
T65 |
11 |
|
T22 |
13 |
|
T154 |
12 |
| auto[1] |
112 |
1 |
|
|
T65 |
9 |
|
T22 |
7 |
|
T154 |
8 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
122 |
1 |
|
|
T65 |
12 |
|
T22 |
10 |
|
T154 |
9 |
| auto[1] |
118 |
1 |
|
|
T65 |
8 |
|
T22 |
10 |
|
T154 |
11 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
122 |
1 |
|
|
T65 |
10 |
|
T22 |
8 |
|
T154 |
10 |
| auto[1] |
118 |
1 |
|
|
T65 |
10 |
|
T22 |
12 |
|
T154 |
10 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
121 |
1 |
|
|
T65 |
6 |
|
T22 |
12 |
|
T154 |
12 |
| auto[1] |
119 |
1 |
|
|
T65 |
14 |
|
T22 |
8 |
|
T154 |
8 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
130 |
1 |
|
|
T65 |
11 |
|
T22 |
11 |
|
T154 |
10 |
| auto[1] |
110 |
1 |
|
|
T65 |
9 |
|
T22 |
9 |
|
T154 |
10 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
126 |
1 |
|
|
T65 |
11 |
|
T22 |
10 |
|
T154 |
14 |
| auto[1] |
114 |
1 |
|
|
T65 |
9 |
|
T22 |
10 |
|
T154 |
6 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
117 |
1 |
|
|
T65 |
11 |
|
T22 |
11 |
|
T154 |
8 |
| auto[1] |
123 |
1 |
|
|
T65 |
9 |
|
T22 |
9 |
|
T154 |
12 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
118 |
1 |
|
|
T65 |
13 |
|
T22 |
8 |
|
T154 |
8 |
| auto[1] |
122 |
1 |
|
|
T65 |
7 |
|
T22 |
12 |
|
T154 |
12 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
117 |
1 |
|
|
T65 |
13 |
|
T22 |
10 |
|
T154 |
6 |
| auto[1] |
123 |
1 |
|
|
T65 |
7 |
|
T22 |
10 |
|
T154 |
14 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
125 |
1 |
|
|
T65 |
8 |
|
T22 |
17 |
|
T154 |
8 |
| auto[1] |
115 |
1 |
|
|
T65 |
12 |
|
T22 |
3 |
|
T154 |
12 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
120 |
1 |
|
|
T65 |
10 |
|
T22 |
10 |
|
T154 |
8 |
| auto[1] |
120 |
1 |
|
|
T65 |
10 |
|
T22 |
10 |
|
T154 |
12 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
101 |
1 |
|
|
T65 |
9 |
|
T22 |
11 |
|
T154 |
12 |
| auto[1] |
139 |
1 |
|
|
T65 |
11 |
|
T22 |
9 |
|
T154 |
8 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
122 |
1 |
|
|
T65 |
12 |
|
T22 |
13 |
|
T154 |
7 |
| auto[1] |
118 |
1 |
|
|
T65 |
8 |
|
T22 |
7 |
|
T154 |
13 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
128 |
1 |
|
|
T65 |
11 |
|
T22 |
6 |
|
T154 |
12 |
| auto[1] |
112 |
1 |
|
|
T65 |
9 |
|
T22 |
14 |
|
T154 |
8 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
116 |
1 |
|
|
T65 |
12 |
|
T22 |
11 |
|
T154 |
6 |
| auto[1] |
124 |
1 |
|
|
T65 |
8 |
|
T22 |
9 |
|
T154 |
14 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
127 |
1 |
|
|
T65 |
12 |
|
T22 |
11 |
|
T154 |
10 |
| auto[1] |
113 |
1 |
|
|
T65 |
8 |
|
T22 |
9 |
|
T154 |
10 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
108 |
1 |
|
|
T65 |
7 |
|
T22 |
7 |
|
T154 |
7 |
| auto[1] |
132 |
1 |
|
|
T65 |
13 |
|
T22 |
13 |
|
T154 |
13 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
112 |
1 |
|
|
T65 |
9 |
|
T22 |
11 |
|
T154 |
10 |
| auto[1] |
128 |
1 |
|
|
T65 |
11 |
|
T22 |
9 |
|
T154 |
10 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
117 |
1 |
|
|
T65 |
11 |
|
T22 |
8 |
|
T154 |
10 |
| auto[1] |
123 |
1 |
|
|
T65 |
9 |
|
T22 |
12 |
|
T154 |
10 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
118 |
1 |
|
|
T65 |
13 |
|
T22 |
8 |
|
T154 |
8 |
| auto[1] |
122 |
1 |
|
|
T65 |
7 |
|
T22 |
12 |
|
T154 |
12 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
60 |
1 |
|
|
T65 |
5 |
|
T22 |
6 |
|
T154 |
4 |
| auto[0] |
auto[1] |
60 |
1 |
|
|
T65 |
5 |
|
T22 |
4 |
|
T154 |
4 |
| auto[1] |
auto[0] |
62 |
1 |
|
|
T65 |
6 |
|
T22 |
5 |
|
T154 |
2 |
| auto[1] |
auto[1] |
58 |
1 |
|
|
T65 |
4 |
|
T22 |
5 |
|
T154 |
10 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
51 |
1 |
|
|
T65 |
2 |
|
T22 |
6 |
|
T154 |
9 |
| auto[0] |
auto[1] |
50 |
1 |
|
|
T65 |
7 |
|
T22 |
5 |
|
T154 |
3 |
| auto[1] |
auto[0] |
72 |
1 |
|
|
T65 |
4 |
|
T22 |
4 |
|
T154 |
3 |
| auto[1] |
auto[1] |
67 |
1 |
|
|
T65 |
7 |
|
T22 |
5 |
|
T154 |
5 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
66 |
1 |
|
|
T65 |
8 |
|
T22 |
8 |
|
T154 |
5 |
| auto[0] |
auto[1] |
56 |
1 |
|
|
T65 |
4 |
|
T22 |
5 |
|
T154 |
2 |
| auto[1] |
auto[0] |
62 |
1 |
|
|
T65 |
3 |
|
T22 |
5 |
|
T154 |
7 |
| auto[1] |
auto[1] |
56 |
1 |
|
|
T65 |
5 |
|
T22 |
2 |
|
T154 |
6 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
66 |
1 |
|
|
T65 |
8 |
|
T22 |
3 |
|
T154 |
6 |
| auto[0] |
auto[1] |
62 |
1 |
|
|
T65 |
3 |
|
T22 |
3 |
|
T154 |
6 |
| auto[1] |
auto[0] |
56 |
1 |
|
|
T65 |
4 |
|
T22 |
7 |
|
T154 |
3 |
| auto[1] |
auto[1] |
56 |
1 |
|
|
T65 |
5 |
|
T22 |
7 |
|
T154 |
5 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
64 |
1 |
|
|
T65 |
7 |
|
T22 |
4 |
|
T154 |
4 |
| auto[0] |
auto[1] |
52 |
1 |
|
|
T65 |
5 |
|
T22 |
7 |
|
T154 |
2 |
| auto[1] |
auto[0] |
58 |
1 |
|
|
T65 |
3 |
|
T22 |
4 |
|
T154 |
6 |
| auto[1] |
auto[1] |
66 |
1 |
|
|
T65 |
5 |
|
T22 |
5 |
|
T154 |
8 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
69 |
1 |
|
|
T65 |
5 |
|
T22 |
6 |
|
T154 |
7 |
| auto[0] |
auto[1] |
58 |
1 |
|
|
T65 |
7 |
|
T22 |
5 |
|
T154 |
3 |
| auto[1] |
auto[0] |
52 |
1 |
|
|
T65 |
1 |
|
T22 |
6 |
|
T154 |
5 |
| auto[1] |
auto[1] |
61 |
1 |
|
|
T65 |
7 |
|
T22 |
3 |
|
T154 |
5 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
53 |
1 |
|
|
T65 |
6 |
|
T22 |
4 |
|
T154 |
7 |
| auto[0] |
auto[1] |
59 |
1 |
|
|
T65 |
3 |
|
T22 |
7 |
|
T154 |
3 |
| auto[1] |
auto[0] |
73 |
1 |
|
|
T65 |
5 |
|
T22 |
6 |
|
T154 |
7 |
| auto[1] |
auto[1] |
55 |
1 |
|
|
T65 |
6 |
|
T22 |
3 |
|
T154 |
3 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
51 |
1 |
|
|
T65 |
7 |
|
T22 |
3 |
|
T154 |
4 |
| auto[0] |
auto[1] |
66 |
1 |
|
|
T65 |
4 |
|
T22 |
5 |
|
T154 |
6 |
| auto[1] |
auto[0] |
66 |
1 |
|
|
T65 |
4 |
|
T22 |
8 |
|
T154 |
4 |
| auto[1] |
auto[1] |
57 |
1 |
|
|
T65 |
5 |
|
T22 |
4 |
|
T154 |
6 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
63 |
1 |
|
|
T65 |
11 |
|
T22 |
4 |
|
T154 |
3 |
| auto[0] |
auto[1] |
54 |
1 |
|
|
T65 |
2 |
|
T22 |
6 |
|
T154 |
3 |
| auto[1] |
auto[0] |
65 |
1 |
|
|
T65 |
2 |
|
T22 |
6 |
|
T154 |
7 |
| auto[1] |
auto[1] |
58 |
1 |
|
|
T65 |
5 |
|
T22 |
4 |
|
T154 |
7 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
125 |
1 |
|
|
T65 |
8 |
|
T22 |
17 |
|
T154 |
8 |
| auto[1] |
auto[1] |
115 |
1 |
|
|
T65 |
12 |
|
T22 |
3 |
|
T154 |
12 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
61 |
1 |
|
|
T65 |
4 |
|
T22 |
3 |
|
T154 |
3 |
| auto[0] |
auto[1] |
47 |
1 |
|
|
T65 |
3 |
|
T22 |
4 |
|
T154 |
4 |
| auto[1] |
auto[0] |
69 |
1 |
|
|
T65 |
7 |
|
T22 |
8 |
|
T154 |
7 |
| auto[1] |
auto[1] |
63 |
1 |
|
|
T65 |
6 |
|
T22 |
5 |
|
T154 |
6 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
118 |
1 |
|
|
T65 |
13 |
|
T22 |
8 |
|
T154 |
8 |
| auto[1] |
auto[1] |
122 |
1 |
|
|
T65 |
7 |
|
T22 |
12 |
|
T154 |
12 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
75 |
1 |
|
|
T22 |
8 |
|
T93 |
9 |
|
T182 |
14 |
| auto[1] |
85 |
1 |
|
|
T22 |
12 |
|
T93 |
11 |
|
T182 |
6 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
85 |
1 |
|
|
T22 |
11 |
|
T93 |
10 |
|
T182 |
10 |
| auto[1] |
75 |
1 |
|
|
T22 |
9 |
|
T93 |
10 |
|
T182 |
10 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
79 |
1 |
|
|
T22 |
11 |
|
T93 |
12 |
|
T182 |
9 |
| auto[1] |
81 |
1 |
|
|
T22 |
9 |
|
T93 |
8 |
|
T182 |
11 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
76 |
1 |
|
|
T22 |
7 |
|
T93 |
14 |
|
T182 |
6 |
| auto[1] |
84 |
1 |
|
|
T22 |
13 |
|
T93 |
6 |
|
T182 |
14 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
86 |
1 |
|
|
T22 |
11 |
|
T93 |
8 |
|
T182 |
5 |
| auto[1] |
74 |
1 |
|
|
T22 |
9 |
|
T93 |
12 |
|
T182 |
15 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
81 |
1 |
|
|
T22 |
12 |
|
T93 |
12 |
|
T182 |
6 |
| auto[1] |
79 |
1 |
|
|
T22 |
8 |
|
T93 |
8 |
|
T182 |
14 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
87 |
1 |
|
|
T22 |
10 |
|
T93 |
11 |
|
T182 |
13 |
| auto[1] |
73 |
1 |
|
|
T22 |
10 |
|
T93 |
9 |
|
T182 |
7 |