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 LINE       6849
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T4,T3,T7
1	1	0	Covered	T266,T274,T275
1	1	1	Covered	T11,T14,T15

 LINE       6851
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T4,T2,T3
1	1	0	Covered	T266,T274,T275
1	1	1	Covered	T2,T3,T7

 LINE       6853
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T25,T3,T28
1	1	0	Covered	T266,T274,T275
1	1	1	Covered	T25,T10,T50

 LINE       6866
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T4,T6,T25
1	1	0	Covered	T274,T278,T279
1	1	1	Covered	T4,T25,T2

 LINE       6883
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T4,T6,T25
1	1	0	Covered	T266,T275,T278
1	1	1	Covered	T4,T25,T2

 LINE       6892
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T4,T6,T2
1	1	0	Covered	T266,T274,T278
1	1	1	Covered	T4,T2,T26

 LINE       6901
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T6,T1,T3
1	1	0	Covered	T275,T279,T280
1	1	1	Covered	T1,T10,T12

 LINE       6916
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T6,T1,T2
1	1	0	Covered	T275,T279,T281
1	1	1	Covered	T1,T2,T3

 LINE       6918
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T2,T3,T28
1	1	0	Covered	T266,T267,T274
1	1	1	Covered	T2,T28,T51

 LINE       6921
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T2,T3,T28
1	1	0	Covered	T266,T276,T274
1	1	1	Covered	T2,T28,T51

 LINE       6928
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T2,T3,T7
1	1	0	Covered	T266,T274,T278
1	1	1	Covered	T3,T9,T52

 LINE       6934
 EXPRESSION (addr_hit[22] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T2,T3,T7
1	1	0	Covered	T271,T266,T274
1	1	1	Covered	T3,T9,T52

 LINE       6940
 EXPRESSION (addr_hit[23] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T6,T2,T3
1	1	0	Covered	T282,T266,T278
1	1	1	Covered	T3,T9,T52

 LINE       6946
 EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T2,T3,T7
1	1	0	Covered	T275,T278,T283
1	1	1	Covered	T3,T9,T52

 LINE       6952
 EXPRESSION (addr_hit[25] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T3,T7,T30
1	1	0	Covered	T266,T276,T274
1	1	1	Covered	T3,T9,T52

 LINE       6954
 EXPRESSION (addr_hit[26] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T6,T3,T7
1	1	0	Covered	T266,T275,T278
1	1	1	Covered	T3,T9,T52

 LINE       6956
 EXPRESSION (addr_hit[27] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T3,T7,T30
1	1	0	Covered	T266,T275,T279
1	1	1	Covered	T3,T9,T52

 LINE       6958
 EXPRESSION (addr_hit[28] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T6,T3,T7
1	1	0	Covered	T266,T276,T274
1	1	1	Covered	T3,T9,T52

 LINE       6960
 EXPRESSION (addr_hit[29] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T6,T2,T3
1	1	0	Covered	T266,T276,T275
1	1	1	Covered	T2,T3,T7

 LINE       6966
 EXPRESSION (addr_hit[30] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T6,T2,T3
1	1	0	Covered	T276,T274,T275
1	1	1	Covered	T2,T3,T7

 LINE       6972
 EXPRESSION (addr_hit[31] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T6,T2,T3
1	1	0	Covered	T10,T282,T266
1	1	1	Covered	T2,T3,T7

 LINE       6978
 EXPRESSION (addr_hit[32] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T2,T3,T28
1	1	0	Covered	T271,T266,T276
1	1	1	Covered	T2,T3,T7

 LINE       6984
 EXPRESSION (addr_hit[33] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T6,T2,T3
1	1	0	Covered	T275,T278,T277
1	1	1	Covered	T2,T3,T7

 LINE       6986
 EXPRESSION (addr_hit[34] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T2,T3,T7
1	1	0	Covered	T266,T276,T274
1	1	1	Covered	T2,T3,T7

 LINE       6988
 EXPRESSION (addr_hit[35] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T2,T3,T7
1	1	0	Covered	T266,T276,T275
1	1	1	Covered	T2,T3,T7

 LINE       6990
 EXPRESSION (addr_hit[36] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T6,T2,T3
1	1	0	Covered	T266,T274,T275
1	1	1	Covered	T2,T3,T7

 LINE       6992
 EXPRESSION (addr_hit[37] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T6,T2,T3
1	1	0	Covered	T266,T276,T272
1	1	1	Covered	T2,T3,T7

 LINE       6997
 EXPRESSION (addr_hit[38] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T2,T3,T28
1	1	0	Covered	T277,T279,T283
1	1	1	Covered	T2,T3,T7

 LINE       7002
 EXPRESSION (addr_hit[39] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T6,T2,T3
1	1	0	Covered	T266,T267,T275
1	1	1	Covered	T2,T3,T7

 LINE       7007
 EXPRESSION (addr_hit[40] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T2,T3,T28
1	1	0	Covered	T266,T276,T274
1	1	1	Covered	T2,T3,T7

 LINE       7012
 EXPRESSION (addr_hit[41] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T4,T2,T3
1	1	0	Covered	T266,T274,T275
1	1	1	Covered	T2,T3,T7

 LINE       7017
 EXPRESSION (addr_hit[42] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T4,T6,T1
1	1	0	Covered	T276,T275,T278
1	1	1	Covered	T1,T10,T12

 LINE       7239
 EXPRESSION (reg_busy_sel | shadow_busy)
             ------1-----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T4,T1,T25