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 LINE       60
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT265,T266,T267
11CoveredT4,T5,T6

 LINE       72
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----
-1--2-StatusTestsExclude Annotation
00CoveredT4,T5,T6
01ExcludedT268,T269,T270 VC_COV_UNR
10CoveredT271,T267,T272

 LINE       79
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----
-1--2--3-StatusTests
000CoveredT4,T5,T6
001CoveredT268,T269,T270
010CoveredT271,T267,T272
100CoveredT268,T269,T270

 LINE       121
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---
-1--2--3-StatusTests
000CoveredT4,T5,T6
001CoveredT271,T267,T272
010CoveredT10,T265,T46
100CoveredT265,T273,T266

 LINE       2115
 EXPRESSION (aon_ec_rst_ctl_we & aon_ec_rst_ctl_regwen)
             --------1--------   ----------2----------
-1--2-StatusTests
01Not Covered
10CoveredT47,T48,T72
11CoveredT2,T3,T7

 LINE       2146
 EXPRESSION (aon_ulp_ac_debounce_ctl_we & aon_ulp_ac_debounce_ctl_regwen)
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT47,T48,T72
11CoveredT30,T10,T11

 LINE       2178
 EXPRESSION (aon_ulp_lid_debounce_ctl_we & aon_ulp_lid_debounce_ctl_regwen)
             -------------1-------------   ---------------2---------------
-1--2-StatusTests
01Not Covered
10CoveredT47,T48,T49
11CoveredT30,T10,T11

 LINE       2210
 EXPRESSION (aon_ulp_pwrb_debounce_ctl_we & aon_ulp_pwrb_debounce_ctl_regwen)
             --------------1-------------   ----------------2---------------
-1--2-StatusTests
01Not Covered
10CoveredT47,T48,T72
11CoveredT30,T10,T11

 LINE       2330
 EXPRESSION (aon_key_invert_ctl_we & aon_key_invert_ctl_regwen)
             ----------1----------   ------------2------------
-1--2-StatusTests
01Not Covered
10CoveredT47,T48,T49
11CoveredT25,T10,T50

 LINE       2659
 EXPRESSION (aon_pin_allowed_ctl_we & aon_pin_allowed_ctl_regwen)
             -----------1----------   -------------2------------
-1--2-StatusTests
01Not Covered
10CoveredT47,T48,T49
11CoveredT4,T25,T2

 LINE       3750
 EXPRESSION (aon_key_intr_ctl_we & aon_key_intr_ctl_regwen)
             ---------1---------   -----------2-----------
-1--2-StatusTests
01Not Covered
10CoveredT47,T48,T72
11CoveredT1,T10,T12

 LINE       4133
 EXPRESSION (aon_key_intr_debounce_ctl_we & aon_key_intr_debounce_ctl_regwen)
             --------------1-------------   ----------------2---------------
-1--2-StatusTests
01Not Covered
10CoveredT47,T48,T49
11CoveredT1,T2,T3

 LINE       4165
 EXPRESSION (aon_auto_block_debounce_ctl_we & aon_auto_block_debounce_ctl_regwen)
             ---------------1--------------   -----------------2----------------
-1--2-StatusTests
01Not Covered
10CoveredT47,T48,T72
11CoveredT2,T28,T51

 LINE       4225
 EXPRESSION (aon_auto_block_out_ctl_we & aon_auto_block_out_ctl_regwen)
             ------------1------------   --------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT47,T48,T49
11CoveredT2,T28,T51

 LINE       4394
 EXPRESSION (aon_com_pre_sel_ctl_0_we & aon_com_pre_sel_ctl_0_regwen)
             ------------1-----------   --------------2-------------
-1--2-StatusTests
01Not Covered
10CoveredT47,T48,T49
11CoveredT3,T9,T52

 LINE       4535
 EXPRESSION (aon_com_pre_sel_ctl_1_we & aon_com_pre_sel_ctl_1_regwen)
             ------------1-----------   --------------2-------------
-1--2-StatusTests
01Not Covered
10CoveredT47,T48,T49
11CoveredT3,T9,T52

 LINE       4676
 EXPRESSION (aon_com_pre_sel_ctl_2_we & aon_com_pre_sel_ctl_2_regwen)
             ------------1-----------   --------------2-------------
-1--2-StatusTests
01Not Covered
10CoveredT47,T48,T72
11CoveredT3,T9,T52

 LINE       4817
 EXPRESSION (aon_com_pre_sel_ctl_3_we & aon_com_pre_sel_ctl_3_regwen)
             ------------1-----------   --------------2-------------
-1--2-StatusTests
01Not Covered
10CoveredT47,T48,T72
11CoveredT3,T9,T52

 LINE       4958
 EXPRESSION (aon_com_pre_det_ctl_0_we & aon_com_pre_det_ctl_0_regwen)
             ------------1-----------   --------------2-------------
-1--2-StatusTests
01Not Covered
10CoveredT47,T48,T72
11CoveredT3,T9,T52

 LINE       4990
 EXPRESSION (aon_com_pre_det_ctl_1_we & aon_com_pre_det_ctl_1_regwen)
             ------------1-----------   --------------2-------------
-1--2-StatusTests
01Not Covered
10CoveredT47,T48,T72
11CoveredT3,T9,T52

 LINE       5022
 EXPRESSION (aon_com_pre_det_ctl_2_we & aon_com_pre_det_ctl_2_regwen)
             ------------1-----------   --------------2-------------
-1--2-StatusTests
01Not Covered
10CoveredT47,T48,T49
11CoveredT3,T9,T52

 LINE       5054
 EXPRESSION (aon_com_pre_det_ctl_3_we & aon_com_pre_det_ctl_3_regwen)
             ------------1-----------   --------------2-------------
-1--2-StatusTests
01Not Covered
10CoveredT47,T48,T72
11CoveredT3,T9,T52

 LINE       5086
 EXPRESSION (aon_com_sel_ctl_0_we & aon_com_sel_ctl_0_regwen)
             ----------1---------   ------------2-----------
-1--2-StatusTests
01Not Covered
10CoveredT47,T48,T72
11CoveredT2,T3,T7

 LINE       5227
 EXPRESSION (aon_com_sel_ctl_1_we & aon_com_sel_ctl_1_regwen)
             ----------1---------   ------------2-----------
-1--2-StatusTests
01Not Covered
10CoveredT47,T48,T49
11CoveredT2,T3,T7

 LINE       5368
 EXPRESSION (aon_com_sel_ctl_2_we & aon_com_sel_ctl_2_regwen)
             ----------1---------   ------------2-----------
-1--2-StatusTests
01Not Covered
10CoveredT47,T48,T49
11CoveredT2,T3,T7

 LINE       5509
 EXPRESSION (aon_com_sel_ctl_3_we & aon_com_sel_ctl_3_regwen)
             ----------1---------   ------------2-----------
-1--2-StatusTests
01Not Covered
10CoveredT47,T49,T72
11CoveredT2,T3,T7

 LINE       5650
 EXPRESSION (aon_com_det_ctl_0_we & aon_com_det_ctl_0_regwen)
             ----------1---------   ------------2-----------
-1--2-StatusTests
01Not Covered
10CoveredT47,T48,T49
11CoveredT2,T3,T7

 LINE       5682
 EXPRESSION (aon_com_det_ctl_1_we & aon_com_det_ctl_1_regwen)
             ----------1---------   ------------2-----------
-1--2-StatusTests
01Not Covered
10CoveredT47,T72,T271
11CoveredT2,T3,T7

 LINE       5714
 EXPRESSION (aon_com_det_ctl_2_we & aon_com_det_ctl_2_regwen)
             ----------1---------   ------------2-----------
-1--2-StatusTests
01Not Covered
10CoveredT47,T48,T49
11CoveredT2,T3,T7

 LINE       5746
 EXPRESSION (aon_com_det_ctl_3_we & aon_com_det_ctl_3_regwen)
             ----------1---------   ------------2-----------
-1--2-StatusTests
01Not Covered
10CoveredT47,T48,T49
11CoveredT2,T3,T7

 LINE       5778
 EXPRESSION (aon_com_out_ctl_0_we & aon_com_out_ctl_0_regwen)
             ----------1---------   ------------2-----------
-1--2-StatusTests
01Not Covered
10CoveredT47,T48,T49
11CoveredT2,T3,T7

 LINE       5892
 EXPRESSION (aon_com_out_ctl_1_we & aon_com_out_ctl_1_regwen)
             ----------1---------   ------------2-----------
-1--2-StatusTests
01Not Covered
10CoveredT47,T48,T49
11CoveredT2,T3,T7

 LINE       6006
 EXPRESSION (aon_com_out_ctl_2_we & aon_com_out_ctl_2_regwen)
             ----------1---------   ------------2-----------
-1--2-StatusTests
01Not Covered
10CoveredT47,T48,T49
11CoveredT2,T3,T7

 LINE       6120
 EXPRESSION (aon_com_out_ctl_3_we & aon_com_out_ctl_3_regwen)
             ----------1---------   ------------2-----------
-1--2-StatusTests
01Not Covered
10CoveredT47,T48,T49
11CoveredT2,T3,T7

 LINE       6728
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_INTR_STATE_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       6729
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_INTR_ENABLE_OFFSET)
            --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       6730
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_INTR_TEST_OFFSET)
            -------------------------------1-------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T6,T3

 LINE       6731
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_ALERT_TEST_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT6,T3,T27

 LINE       6732
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_REGWEN_OFFSET)
            ------------------------------1-----------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT6,T3,T7

 LINE       6733
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_EC_RST_CTL_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT2,T3,T28

 LINE       6734
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_ULP_AC_DEBOUNCE_CTL_OFFSET)
            ------------------------------------1------------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT6,T3,T7

 LINE       6735
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_ULP_LID_DEBOUNCE_CTL_OFFSET)
            -------------------------------------1------------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT3,T28,T7

 LINE       6736
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_ULP_PWRB_DEBOUNCE_CTL_OFFSET)
            -------------------------------------1-------------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT6,T3,T7

 LINE       6737
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_ULP_CTL_OFFSET)
            ------------------------------1------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT3,T7,T30

 LINE       6738
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_ULP_STATUS_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T3,T7

 LINE       6739
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_WKUP_STATUS_OFFSET)
            --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T2,T3

 LINE       6740
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_KEY_INVERT_CTL_OFFSET)
            ----------------------------------1---------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT25,T3,T28

 LINE       6741
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_PIN_ALLOWED_CTL_OFFSET)
            ----------------------------------1----------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T6,T25

 LINE       6742
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_PIN_OUT_CTL_OFFSET)
            --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T6,T25

 LINE       6743
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_PIN_OUT_VALUE_OFFSET)
            ---------------------------------1---------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T6,T2

 LINE       6744
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_PIN_IN_VALUE_OFFSET)
            ---------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       6745
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_KEY_INTR_CTL_OFFSET)
            ---------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT6,T1,T3

 LINE       6746
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_KEY_INTR_DEBOUNCE_CTL_OFFSET)
            -------------------------------------1-------------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT6,T1,T2

 LINE       6747
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_AUTO_BLOCK_DEBOUNCE_CTL_OFFSET)
            --------------------------------------1--------------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT2,T3,T28

 LINE       6748
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_AUTO_BLOCK_OUT_CTL_OFFSET)
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT2,T3,T28

 LINE       6749
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_PRE_SEL_CTL_0_OFFSET)
            -----------------------------------1-----------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT2,T3,T7

 LINE       6750
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_PRE_SEL_CTL_1_OFFSET)
            -----------------------------------1-----------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT2,T3,T7

 LINE       6751
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_PRE_SEL_CTL_2_OFFSET)
            -----------------------------------1-----------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT6,T2,T3

 LINE       6752
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_PRE_SEL_CTL_3_OFFSET)
            -----------------------------------1-----------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT2,T3,T7

 LINE       6753
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_PRE_DET_CTL_0_OFFSET)
            -----------------------------------1-----------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT3,T7,T30

 LINE       6754
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_PRE_DET_CTL_1_OFFSET)
            -----------------------------------1-----------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT6,T3,T7

 LINE       6755
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_PRE_DET_CTL_2_OFFSET)
            -----------------------------------1-----------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT3,T7,T30

 LINE       6756
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_PRE_DET_CTL_3_OFFSET)
            -----------------------------------1-----------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT6,T3,T7

 LINE       6757
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_SEL_CTL_0_OFFSET)
            ---------------------------------1---------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT6,T2,T3

 LINE       6758
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_SEL_CTL_1_OFFSET)
            ---------------------------------1---------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT6,T2,T3

 LINE       6759
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_SEL_CTL_2_OFFSET)
            ---------------------------------1---------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT6,T2,T3

 LINE       6760
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_SEL_CTL_3_OFFSET)
            ---------------------------------1---------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT2,T3,T28

 LINE       6761
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_DET_CTL_0_OFFSET)
            ---------------------------------1---------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT6,T2,T3

 LINE       6762
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_DET_CTL_1_OFFSET)
            ---------------------------------1---------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT2,T3,T7

 LINE       6763
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_DET_CTL_2_OFFSET)
            ---------------------------------1---------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT2,T3,T7

 LINE       6764
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_DET_CTL_3_OFFSET)
            ---------------------------------1---------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT6,T2,T3

 LINE       6765
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_OUT_CTL_0_OFFSET)
            ---------------------------------1---------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT6,T2,T3

 LINE       6766
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_OUT_CTL_1_OFFSET)
            ---------------------------------1---------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT2,T3,T28

 LINE       6767
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_OUT_CTL_2_OFFSET)
            ---------------------------------1---------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT6,T2,T3

 LINE       6768
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_OUT_CTL_3_OFFSET)
            ---------------------------------1---------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT2,T3,T28

 LINE       6769
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COMBO_INTR_STATUS_OFFSET)
            -----------------------------------1-----------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T2,T3

 LINE       6770
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_KEY_INTR_STATUS_OFFSET)
            ----------------------------------1----------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T6,T1

 LINE       6773
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       6773
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT4,T5,T6
10CoveredT4,T5,T6

 LINE       6777
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[6] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[7] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[8] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1 & (~reg_be))))) | (addr_hit[12] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[13] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | (addr_hit[17] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[18] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[19] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1 & (~reg_be))))) | (addr_hit[22] & ((|(4'b1 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1 & (~reg_be))))) | (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[28] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[29] & ((|(4'b1 & (~reg_be))))) | (addr_hit[30] & ((|(4'b1 & (~reg_be))))) | (addr_hit[31] & ((|(4'b1 & (~reg_be))))) | (addr_hit[32] & ((|(4'b1 & (~reg_be))))) | (addr_hit[33] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[34] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[35] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[36] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[37] & ((|(4'b1 & (~reg_be))))) | (addr_hit[38] & ((|(4'b1 & (~reg_be))))) | (addr_hit[39] & ((|(4'b1 & (~reg_be))))) | (addr_hit[40] & ((|(4'b1 & (~reg_be))))) | (addr_hit[41] & ((|(4'b1 & (~reg_be))))) | (addr_hit[42] & ((|(4'b0011 & (~reg_be)))))))
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT10,T265,T46

 LINE       6777
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b0011 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b0011 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b0011 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b0011 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b0011 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b0011 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b0011 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b0111 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b1 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1 & (~reg_be))))) | 
     23  (addr_hit[22] & ((|(4'b1 & (~reg_be))))) | 
     24  (addr_hit[23] & ((|(4'b1 & (~reg_be))))) | 
     25  (addr_hit[24] & ((|(4'b1 & (~reg_be))))) | 
     26  (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | 
     27  (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) | 
     28  (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) | 
     29  (addr_hit[28] & ((|(4'b1111 & (~reg_be))))) | 
     30  (addr_hit[29] & ((|(4'b1 & (~reg_be))))) | 
     31  (addr_hit[30] & ((|(4'b1 & (~reg_be))))) | 
     32  (addr_hit[31] & ((|(4'b1 & (~reg_be))))) | 
     33  (addr_hit[32] & ((|(4'b1 & (~reg_be))))) | 
     34  (addr_hit[33] & ((|(4'b1111 & (~reg_be))))) | 
     35  (addr_hit[34] & ((|(4'b1111 & (~reg_be))))) | 
     36  (addr_hit[35] & ((|(4'b1111 & (~reg_be))))) | 
     37  (addr_hit[36] & ((|(4'b1111 & (~reg_be))))) | 
     38  (addr_hit[37] & ((|(4'b1 & (~reg_be))))) | 
     39  (addr_hit[38] & ((|(4'b1 & (~reg_be))))) | 
     40  (addr_hit[39] & ((|(4'b1 & (~reg_be))))) | 
     41  (addr_hit[40] & ((|(4'b1 & (~reg_be))))) | 
     42  (addr_hit[41] & ((|(4'b1 & (~reg_be))))) | 
     43  (addr_hit[42] & ((|(4'b0011 & (~reg_be))))))
Sensitive Expression == 1StatusTests
ALL ZEROSCoveredT4,T5,T6
43 (addr_hit[42] & ((|(4'...CoveredT4,T6,T1
42 (addr_hit[41] & ((|(4'...CoveredT2,T3,T7
41 (addr_hit[40] & ((|(4'...CoveredT2,T3,T7
40 (addr_hit[39] & ((|(4'...CoveredT2,T3,T7
39 (addr_hit[38] & ((|(4'...CoveredT2,T3,T7
38 (addr_hit[37] & ((|(4'...CoveredT6,T2,T3
37 (addr_hit[36] & ((|(4'...CoveredT6,T2,T3
36 (addr_hit[35] & ((|(4'...CoveredT2,T3,T7
35 (addr_hit[34] & ((|(4'...CoveredT2,T3,T7
34 (addr_hit[33] & ((|(4'...CoveredT6,T2,T3
33 (addr_hit[32] & ((|(4'...CoveredT2,T3,T7
32 (addr_hit[31] & ((|(4'...CoveredT6,T2,T3
31 (addr_hit[30] & ((|(4'...CoveredT2,T3,T7
30 (addr_hit[29] & ((|(4'...CoveredT2,T3,T7
29 (addr_hit[28] & ((|(4'...CoveredT6,T3,T7
28 (addr_hit[27] & ((|(4'...CoveredT3,T7,T30
27 (addr_hit[26] & ((|(4'...CoveredT6,T3,T7
26 (addr_hit[25] & ((|(4'...CoveredT3,T7,T30
25 (addr_hit[24] & ((|(4'...CoveredT2,T3,T7
24 (addr_hit[23] & ((|(4'...CoveredT2,T3,T7
23 (addr_hit[22] & ((|(4'...CoveredT2,T3,T7
22 (addr_hit[21] & ((|(4'...CoveredT2,T3,T7
21 (addr_hit[20] & ((|(4'...CoveredT2,T3,T7
20 (addr_hit[19] & ((|(4'...CoveredT2,T3,T28
19 (addr_hit[18] & ((|(4'...CoveredT6,T3,T7
18 (addr_hit[17] & ((|(4'...CoveredT3,T7,T30
17 (addr_hit[16] & ((|(4'...CoveredT4,T5,T6
16 (addr_hit[15] & ((|(4'...CoveredT6,T26,T3
15 (addr_hit[14] & ((|(4'...CoveredT6,T26,T3
14 (addr_hit[13] & ((|(4'...CoveredT6,T26,T3
13 (addr_hit[12] & ((|(4'...CoveredT25,T3,T28
12 (addr_hit[11] & ((|(4'...CoveredT2,T3,T7
11 (addr_hit[10] & ((|(4'...CoveredT3,T7,T30
10 (addr_hit[9] & ((|(4'b...CoveredT3,T7,T30
9 (addr_hit[8] & ((|(4'b...CoveredT3,T7,T30
8 (addr_hit[7] & ((|(4'b...CoveredT3,T7,T30
7 (addr_hit[6] & ((|(4'b...CoveredT6,T3,T7
6 (addr_hit[5] & ((|(4'b...CoveredT2,T3,T28
5 (addr_hit[4] & ((|(4'b...CoveredT3,T7,T10
4 (addr_hit[3] & ((|(4'b...CoveredT6,T3,T7
3 (addr_hit[2] & ((|(4'b...CoveredT4,T6,T3
2 (addr_hit[1] & ((|(4'b...CoveredT4,T3,T7
1 (addr_hit[0] & ((|(4'b...CoveredT4,T5,T1

 LINE       6777
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T6,T1
11CoveredT4,T5,T1

 LINE       6777
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT4,T3,T7

 LINE       6777
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T3,T7
11CoveredT4,T6,T3

 LINE       6777
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT6,T3,T27
11CoveredT6,T3,T7

 LINE       6777
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT6,T3,T7
11CoveredT3,T7,T10

 LINE       6777
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT2,T3,T7
11CoveredT2,T3,T28

 LINE       6777
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT3,T7,T30
11CoveredT6,T3,T7

 LINE       6777
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT3,T28,T7
11CoveredT3,T7,T30

 LINE       6777
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT6,T3,T7
11CoveredT3,T7,T30

 LINE       6777
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT3,T7,T30
11CoveredT3,T7,T30

 LINE       6777
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T3,T7
11CoveredT3,T7,T30

 LINE       6777
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T2,T3
11CoveredT2,T3,T7

 LINE       6777
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT25,T3,T7
11CoveredT25,T3,T28

 LINE       6777
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T25,T2
11CoveredT6,T26,T3

 LINE       6777
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T25,T2
11CoveredT6,T26,T3

 LINE       6777
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T2,T26
11CoveredT6,T26,T3

 LINE       6777
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT4,T5,T6

 LINE       6777
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT6,T1,T3
11CoveredT3,T7,T30

 LINE       6777
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT1,T2,T3
11CoveredT6,T3,T7

 LINE       6777
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT2,T3,T28
11CoveredT2,T3,T28

 LINE       6777
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT2,T3,T28
11CoveredT2,T3,T7

 LINE       6777
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT2,T3,T7
11CoveredT2,T3,T7

 LINE       6777
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT2,T3,T7
11CoveredT2,T3,T7

 LINE       6777
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT6,T2,T3
11CoveredT2,T3,T7

 LINE       6777
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT2,T3,T7
11CoveredT2,T3,T7

 LINE       6777
 SUB-EXPRESSION (addr_hit[25] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT3,T30,T9
11CoveredT3,T7,T30

 LINE       6777
 SUB-EXPRESSION (addr_hit[26] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT3,T7,T9
11CoveredT6,T3,T7

 LINE       6777
 SUB-EXPRESSION (addr_hit[27] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT3,T7,T9
11CoveredT3,T7,T30

 LINE       6777
 SUB-EXPRESSION (addr_hit[28] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT3,T9,T10
11CoveredT6,T3,T7

 LINE       6777
 SUB-EXPRESSION (addr_hit[29] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT6,T2,T3
11CoveredT2,T3,T7

 LINE       6777
 SUB-EXPRESSION (addr_hit[30] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT6,T2,T3
11CoveredT2,T3,T7

 LINE       6777
 SUB-EXPRESSION (addr_hit[31] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT2,T3,T7
11CoveredT6,T2,T3

 LINE       6777
 SUB-EXPRESSION (addr_hit[32] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT2,T3,T28
11CoveredT2,T3,T7

 LINE       6777
 SUB-EXPRESSION (addr_hit[33] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT2,T3,T7
11CoveredT6,T2,T3

 LINE       6777
 SUB-EXPRESSION (addr_hit[34] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT2,T3,T7
11CoveredT2,T3,T7

 LINE       6777
 SUB-EXPRESSION (addr_hit[35] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT2,T3,T7
11CoveredT2,T3,T7

 LINE       6777
 SUB-EXPRESSION (addr_hit[36] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT2,T3,T7
11CoveredT6,T2,T3

 LINE       6777
 SUB-EXPRESSION (addr_hit[37] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT6,T2,T3
11CoveredT6,T2,T3

 LINE       6777
 SUB-EXPRESSION (addr_hit[38] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT2,T3,T28
11CoveredT2,T3,T7

 LINE       6777
 SUB-EXPRESSION (addr_hit[39] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT6,T2,T3
11CoveredT2,T3,T7

 LINE       6777
 SUB-EXPRESSION (addr_hit[40] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT2,T3,T28
11CoveredT2,T3,T7

 LINE       6777
 SUB-EXPRESSION (addr_hit[41] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T2,T3
11CoveredT2,T3,T7

 LINE       6777
 SUB-EXPRESSION (addr_hit[42] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT1,T3,T7
11CoveredT4,T6,T1

 LINE       6824
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT4,T5,T6
110CoveredT266,T274,T275
111CoveredT4,T1,T2

 LINE       6827
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T1,T25
101CoveredT4,T5,T6
110CoveredT266,T276,T277
111CoveredT4,T5,T6

 LINE       6830
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT4,T6,T3
110CoveredT266,T276,T274
111CoveredT4,T10,T14

 LINE       6833
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT6,T3,T27
110CoveredT266,T274,T275
111CoveredT27,T138,T35

 LINE       6836
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT6,T3,T7
110CoveredT265,T266,T274
111CoveredT46,T47,T48

 LINE       6839
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT2,T3,T28
110CoveredT276,T274,T275
111CoveredT2,T3,T7

 LINE       6841
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT6,T3,T7
110CoveredT266,T274,T275
111CoveredT30,T10,T11

 LINE       6843
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT3,T28,T7
110CoveredT276,T274,T275
111CoveredT30,T10,T11

 LINE       6845
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT6,T3,T7
110CoveredT266,T274,T275
111CoveredT30,T10,T11

 LINE       6847
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT3,T7,T30
110CoveredT266,T274,T278
111CoveredT11,T14,T15
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%