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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.32 99.20 95.93 100.00 94.23 98.57 99.16 94.18


Total test records in report: 913
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T197 /workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.3451884249 Feb 29 01:44:31 PM PST 24 Feb 29 01:44:35 PM PST 24 2460375694 ps
T459 /workspace/coverage/default/22.sysrst_ctrl_alert_test.2032888426 Feb 29 01:43:32 PM PST 24 Feb 29 01:43:37 PM PST 24 2011768994 ps
T97 /workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.1794301458 Feb 29 01:44:47 PM PST 24 Feb 29 01:46:16 PM PST 24 46737479881 ps
T85 /workspace/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.3502874798 Feb 29 01:43:13 PM PST 24 Feb 29 01:43:50 PM PST 24 53121982446 ps
T460 /workspace/coverage/default/39.sysrst_ctrl_in_out_inverted.534825227 Feb 29 01:44:14 PM PST 24 Feb 29 01:44:15 PM PST 24 2562827040 ps
T98 /workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.1684271148 Feb 29 01:44:46 PM PST 24 Feb 29 01:46:10 PM PST 24 61441861650 ps
T292 /workspace/coverage/default/25.sysrst_ctrl_auto_blk_key_output.2387726253 Feb 29 01:43:38 PM PST 24 Feb 29 01:43:43 PM PST 24 3353499611 ps
T116 /workspace/coverage/default/49.sysrst_ctrl_combo_detect.1148445310 Feb 29 01:44:46 PM PST 24 Feb 29 01:46:03 PM PST 24 130039800266 ps
T461 /workspace/coverage/default/28.sysrst_ctrl_auto_blk_key_output.3187544272 Feb 29 01:43:41 PM PST 24 Feb 29 01:43:49 PM PST 24 3002303706 ps
T308 /workspace/coverage/default/38.sysrst_ctrl_pin_override_test.3882057314 Feb 29 01:44:07 PM PST 24 Feb 29 01:44:13 PM PST 24 2510255986 ps
T293 /workspace/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.1136204004 Feb 29 01:43:42 PM PST 24 Feb 29 01:45:56 PM PST 24 53918283269 ps
T462 /workspace/coverage/default/45.sysrst_ctrl_smoke.491083854 Feb 29 01:44:30 PM PST 24 Feb 29 01:44:32 PM PST 24 2135827783 ps
T463 /workspace/coverage/default/21.sysrst_ctrl_pin_override_test.855082762 Feb 29 01:43:20 PM PST 24 Feb 29 01:43:27 PM PST 24 2511693037 ps
T464 /workspace/coverage/default/9.sysrst_ctrl_stress_all.1895094592 Feb 29 01:42:49 PM PST 24 Feb 29 01:43:12 PM PST 24 10951822617 ps
T99 /workspace/coverage/default/39.sysrst_ctrl_ultra_low_pwr.856651113 Feb 29 01:44:08 PM PST 24 Feb 29 01:44:15 PM PST 24 2663587159 ps
T465 /workspace/coverage/default/22.sysrst_ctrl_in_out_inverted.2902658229 Feb 29 01:43:27 PM PST 24 Feb 29 01:43:34 PM PST 24 2450063128 ps
T117 /workspace/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.721169628 Feb 29 01:43:13 PM PST 24 Feb 29 01:43:45 PM PST 24 45945913668 ps
T466 /workspace/coverage/default/48.sysrst_ctrl_smoke.3294800189 Feb 29 01:44:31 PM PST 24 Feb 29 01:44:35 PM PST 24 2111074657 ps
T467 /workspace/coverage/default/43.sysrst_ctrl_smoke.177563639 Feb 29 01:44:23 PM PST 24 Feb 29 01:44:29 PM PST 24 2108619071 ps
T468 /workspace/coverage/default/43.sysrst_ctrl_pin_override_test.2543076549 Feb 29 01:44:23 PM PST 24 Feb 29 01:44:27 PM PST 24 2514911891 ps
T469 /workspace/coverage/default/18.sysrst_ctrl_smoke.3302965008 Feb 29 01:43:14 PM PST 24 Feb 29 01:43:17 PM PST 24 2127703452 ps
T239 /workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.2795710894 Feb 29 01:44:46 PM PST 24 Feb 29 01:45:02 PM PST 24 23106935126 ps
T470 /workspace/coverage/default/38.sysrst_ctrl_in_out_inverted.1633521579 Feb 29 01:44:09 PM PST 24 Feb 29 01:44:10 PM PST 24 2547512837 ps
T103 /workspace/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.99021373 Feb 29 01:43:07 PM PST 24 Feb 29 01:44:11 PM PST 24 1937288381215 ps
T471 /workspace/coverage/default/3.sysrst_ctrl_auto_blk_key_output.1187376237 Feb 29 01:42:48 PM PST 24 Feb 29 01:44:58 PM PST 24 51805179646 ps
T472 /workspace/coverage/default/32.sysrst_ctrl_combo_detect.1411988124 Feb 29 01:43:54 PM PST 24 Feb 29 01:44:47 PM PST 24 85124266970 ps
T473 /workspace/coverage/default/15.sysrst_ctrl_pin_override_test.1372407197 Feb 29 01:43:13 PM PST 24 Feb 29 01:43:17 PM PST 24 2514949867 ps
T214 /workspace/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.4176671514 Feb 29 01:44:07 PM PST 24 Feb 29 01:44:37 PM PST 24 30331496842 ps
T474 /workspace/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.3785010350 Feb 29 01:43:04 PM PST 24 Feb 29 01:43:08 PM PST 24 2614115275 ps
T475 /workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.4177921961 Feb 29 01:44:27 PM PST 24 Feb 29 01:44:34 PM PST 24 7035598515 ps
T476 /workspace/coverage/default/33.sysrst_ctrl_alert_test.1231867127 Feb 29 01:43:54 PM PST 24 Feb 29 01:43:56 PM PST 24 2052960688 ps
T477 /workspace/coverage/default/12.sysrst_ctrl_auto_blk_key_output.208722860 Feb 29 01:43:06 PM PST 24 Feb 29 01:43:09 PM PST 24 3165628199 ps
T478 /workspace/coverage/default/45.sysrst_ctrl_pin_access_test.2225419873 Feb 29 01:44:32 PM PST 24 Feb 29 01:44:35 PM PST 24 2163709327 ps
T184 /workspace/coverage/default/46.sysrst_ctrl_stress_all.4091545799 Feb 29 01:44:28 PM PST 24 Feb 29 01:44:54 PM PST 24 10859608597 ps
T479 /workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.3521799132 Feb 29 01:42:52 PM PST 24 Feb 29 01:42:56 PM PST 24 2475121687 ps
T347 /workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.3515827970 Feb 29 01:44:45 PM PST 24 Feb 29 01:45:35 PM PST 24 89794195498 ps
T480 /workspace/coverage/default/36.sysrst_ctrl_ultra_low_pwr.883669092 Feb 29 01:44:05 PM PST 24 Feb 29 01:44:14 PM PST 24 12961070077 ps
T481 /workspace/coverage/default/4.sysrst_ctrl_pin_access_test.2952884924 Feb 29 01:42:49 PM PST 24 Feb 29 01:42:51 PM PST 24 2098899512 ps
T482 /workspace/coverage/default/20.sysrst_ctrl_pin_access_test.3561178262 Feb 29 01:43:29 PM PST 24 Feb 29 01:43:31 PM PST 24 2208944257 ps
T483 /workspace/coverage/default/33.sysrst_ctrl_pin_access_test.3388370516 Feb 29 01:43:55 PM PST 24 Feb 29 01:44:02 PM PST 24 2079980051 ps
T484 /workspace/coverage/default/39.sysrst_ctrl_pin_access_test.2426418041 Feb 29 01:44:01 PM PST 24 Feb 29 01:44:08 PM PST 24 2027671766 ps
T384 /workspace/coverage/default/20.sysrst_ctrl_ultra_low_pwr.2410505818 Feb 29 01:43:18 PM PST 24 Feb 29 01:58:52 PM PST 24 4249457977685 ps
T313 /workspace/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.2650480251 Feb 29 01:43:18 PM PST 24 Feb 29 01:43:36 PM PST 24 27159013968 ps
T485 /workspace/coverage/default/33.sysrst_ctrl_pin_override_test.2830886938 Feb 29 01:43:53 PM PST 24 Feb 29 01:44:00 PM PST 24 2509958540 ps
T241 /workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.3575186085 Feb 29 01:44:46 PM PST 24 Feb 29 01:45:24 PM PST 24 26592632771 ps
T355 /workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.2191449508 Feb 29 01:44:43 PM PST 24 Feb 29 01:45:05 PM PST 24 91352153601 ps
T486 /workspace/coverage/default/17.sysrst_ctrl_stress_all.2107929095 Feb 29 01:43:13 PM PST 24 Feb 29 01:43:20 PM PST 24 9220560727 ps
T244 /workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.2811713149 Feb 29 01:44:46 PM PST 24 Feb 29 01:47:27 PM PST 24 62841384548 ps
T487 /workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.1108817211 Feb 29 01:44:21 PM PST 24 Feb 29 01:44:24 PM PST 24 2623752505 ps
T95 /workspace/coverage/default/5.sysrst_ctrl_stress_all.2384957355 Feb 29 01:42:51 PM PST 24 Feb 29 01:43:32 PM PST 24 17738127352 ps
T129 /workspace/coverage/default/33.sysrst_ctrl_auto_blk_key_output.588448060 Feb 29 01:43:54 PM PST 24 Feb 29 01:44:00 PM PST 24 3829611630 ps
T130 /workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.2189335536 Feb 29 01:44:27 PM PST 24 Feb 29 01:44:28 PM PST 24 2753958798 ps
T131 /workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.4079207487 Feb 29 01:44:47 PM PST 24 Feb 29 01:46:13 PM PST 24 67703933140 ps
T132 /workspace/coverage/default/37.sysrst_ctrl_ultra_low_pwr.1567635285 Feb 29 01:44:09 PM PST 24 Feb 29 01:44:11 PM PST 24 6400360925 ps
T133 /workspace/coverage/default/40.sysrst_ctrl_stress_all.3686712485 Feb 29 01:44:11 PM PST 24 Feb 29 01:45:49 PM PST 24 259628448969 ps
T134 /workspace/coverage/default/29.sysrst_ctrl_alert_test.2836959687 Feb 29 01:43:39 PM PST 24 Feb 29 01:43:41 PM PST 24 2031433165 ps
T135 /workspace/coverage/default/24.sysrst_ctrl_stress_all.3802147276 Feb 29 01:43:35 PM PST 24 Feb 29 01:43:42 PM PST 24 9686839432 ps
T136 /workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.1720619183 Feb 29 01:44:47 PM PST 24 Feb 29 01:48:17 PM PST 24 78755888426 ps
T137 /workspace/coverage/default/2.sysrst_ctrl_edge_detect.2221162372 Feb 29 01:42:45 PM PST 24 Feb 29 01:42:49 PM PST 24 2830273456 ps
T294 /workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.4181101526 Feb 29 01:42:53 PM PST 24 Feb 29 01:44:06 PM PST 24 113738846888 ps
T488 /workspace/coverage/default/23.sysrst_ctrl_pin_access_test.3276209624 Feb 29 01:43:26 PM PST 24 Feb 29 01:43:32 PM PST 24 2264439097 ps
T215 /workspace/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.1845292648 Feb 29 01:43:12 PM PST 24 Feb 29 01:43:44 PM PST 24 12280139615 ps
T489 /workspace/coverage/default/37.sysrst_ctrl_pin_override_test.2974006161 Feb 29 01:44:09 PM PST 24 Feb 29 01:44:12 PM PST 24 2518126358 ps
T91 /workspace/coverage/default/0.sysrst_ctrl_feature_disable.3639347276 Feb 29 01:42:27 PM PST 24 Feb 29 01:42:50 PM PST 24 33895187061 ps
T490 /workspace/coverage/default/1.sysrst_ctrl_alert_test.4208882234 Feb 29 01:42:32 PM PST 24 Feb 29 01:42:38 PM PST 24 2008926437 ps
T341 /workspace/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.1177772211 Feb 29 01:43:38 PM PST 24 Feb 29 01:44:26 PM PST 24 78199427800 ps
T102 /workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.4164194183 Feb 29 01:44:21 PM PST 24 Feb 29 01:44:24 PM PST 24 8024159535 ps
T491 /workspace/coverage/default/19.sysrst_ctrl_auto_blk_key_output.235884232 Feb 29 01:43:15 PM PST 24 Feb 29 01:43:20 PM PST 24 3000237101 ps
T492 /workspace/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.1520154843 Feb 29 01:43:56 PM PST 24 Feb 29 01:44:03 PM PST 24 2548076405 ps
T493 /workspace/coverage/default/1.sysrst_ctrl_in_out_inverted.3142439026 Feb 29 01:42:32 PM PST 24 Feb 29 01:42:35 PM PST 24 2490042060 ps
T494 /workspace/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.2207379412 Feb 29 01:43:56 PM PST 24 Feb 29 01:44:04 PM PST 24 2613839946 ps
T295 /workspace/coverage/default/30.sysrst_ctrl_auto_blk_key_output.1854413310 Feb 29 01:43:52 PM PST 24 Feb 29 01:43:55 PM PST 24 3129460355 ps
T495 /workspace/coverage/default/49.sysrst_ctrl_alert_test.749471151 Feb 29 01:44:44 PM PST 24 Feb 29 01:44:46 PM PST 24 2033926891 ps
T496 /workspace/coverage/default/13.sysrst_ctrl_in_out_inverted.17477211 Feb 29 01:43:10 PM PST 24 Feb 29 01:43:14 PM PST 24 2465803698 ps
T497 /workspace/coverage/default/26.sysrst_ctrl_in_out_inverted.367521244 Feb 29 01:43:38 PM PST 24 Feb 29 01:43:42 PM PST 24 2455244306 ps
T498 /workspace/coverage/default/42.sysrst_ctrl_edge_detect.27699096 Feb 29 01:44:30 PM PST 24 Feb 29 01:44:31 PM PST 24 3207803477 ps
T499 /workspace/coverage/default/3.sysrst_ctrl_in_out_inverted.711340493 Feb 29 01:42:48 PM PST 24 Feb 29 01:42:53 PM PST 24 2481823452 ps
T500 /workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.1443726942 Feb 29 01:42:55 PM PST 24 Feb 29 01:42:57 PM PST 24 3578575718 ps
T501 /workspace/coverage/default/34.sysrst_ctrl_in_out_inverted.3149187325 Feb 29 01:43:55 PM PST 24 Feb 29 01:43:58 PM PST 24 2489517529 ps
T250 /workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.3158507259 Feb 29 01:44:28 PM PST 24 Feb 29 01:48:48 PM PST 24 93678286858 ps
T502 /workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.525218931 Feb 29 01:44:15 PM PST 24 Feb 29 01:44:22 PM PST 24 5446708050 ps
T359 /workspace/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.1954461121 Feb 29 01:43:39 PM PST 24 Feb 29 01:46:10 PM PST 24 61903070244 ps
T245 /workspace/coverage/default/1.sysrst_ctrl_combo_detect.2642565721 Feb 29 01:42:27 PM PST 24 Feb 29 01:45:15 PM PST 24 64285562081 ps
T354 /workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.2967667059 Feb 29 01:44:45 PM PST 24 Feb 29 01:47:35 PM PST 24 61191086830 ps
T87 /workspace/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.366107389 Feb 29 01:43:37 PM PST 24 Feb 29 01:45:29 PM PST 24 53955907106 ps
T104 /workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.1803036106 Feb 29 01:42:51 PM PST 24 Feb 29 01:42:58 PM PST 24 4075146007 ps
T173 /workspace/coverage/default/28.sysrst_ctrl_pin_override_test.1265608752 Feb 29 01:43:39 PM PST 24 Feb 29 01:43:43 PM PST 24 2515397124 ps
T174 /workspace/coverage/default/24.sysrst_ctrl_alert_test.3781463726 Feb 29 01:43:33 PM PST 24 Feb 29 01:43:35 PM PST 24 2040296815 ps
T175 /workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.1245801565 Feb 29 01:44:22 PM PST 24 Feb 29 01:44:26 PM PST 24 3366302509 ps
T176 /workspace/coverage/default/42.sysrst_ctrl_smoke.2142779470 Feb 29 01:44:21 PM PST 24 Feb 29 01:44:28 PM PST 24 2111591393 ps
T177 /workspace/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.850902949 Feb 29 01:43:11 PM PST 24 Feb 29 01:43:22 PM PST 24 4293567450 ps
T178 /workspace/coverage/default/20.sysrst_ctrl_combo_detect.1500363265 Feb 29 01:43:16 PM PST 24 Feb 29 01:45:18 PM PST 24 180035558653 ps
T179 /workspace/coverage/default/17.sysrst_ctrl_edge_detect.3126109737 Feb 29 01:43:08 PM PST 24 Feb 29 01:53:56 PM PST 24 491624823987 ps
T180 /workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.957998537 Feb 29 01:44:47 PM PST 24 Feb 29 01:44:59 PM PST 24 67605855871 ps
T503 /workspace/coverage/default/30.sysrst_ctrl_smoke.2828211383 Feb 29 01:43:55 PM PST 24 Feb 29 01:43:57 PM PST 24 2135018679 ps
T334 /workspace/coverage/default/14.sysrst_ctrl_combo_detect.283207463 Feb 29 01:43:03 PM PST 24 Feb 29 01:44:33 PM PST 24 139407068307 ps
T185 /workspace/coverage/default/49.sysrst_ctrl_edge_detect.2022302702 Feb 29 01:44:45 PM PST 24 Feb 29 01:44:49 PM PST 24 5022939314 ps
T118 /workspace/coverage/default/2.sysrst_ctrl_combo_detect.2730649143 Feb 29 01:42:48 PM PST 24 Feb 29 01:43:03 PM PST 24 41841442922 ps
T360 /workspace/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.1657398653 Feb 29 01:42:48 PM PST 24 Feb 29 01:44:26 PM PST 24 71915391393 ps
T367 /workspace/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.3102613207 Feb 29 01:44:07 PM PST 24 Feb 29 01:47:12 PM PST 24 73320454386 ps
T504 /workspace/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.2642116513 Feb 29 01:42:48 PM PST 24 Feb 29 01:42:50 PM PST 24 2635142957 ps
T505 /workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.423783844 Feb 29 01:44:23 PM PST 24 Feb 29 01:44:27 PM PST 24 3881627180 ps
T506 /workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.1069765339 Feb 29 01:42:52 PM PST 24 Feb 29 01:43:00 PM PST 24 2461213852 ps
T507 /workspace/coverage/default/33.sysrst_ctrl_in_out_inverted.1236830386 Feb 29 01:43:53 PM PST 24 Feb 29 01:44:00 PM PST 24 2478734908 ps
T508 /workspace/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.4032467437 Feb 29 01:43:52 PM PST 24 Feb 29 01:43:55 PM PST 24 2623002358 ps
T509 /workspace/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.3397388564 Feb 29 01:43:15 PM PST 24 Feb 29 01:43:18 PM PST 24 2623718021 ps
T510 /workspace/coverage/default/22.sysrst_ctrl_auto_blk_key_output.1641586824 Feb 29 01:43:26 PM PST 24 Feb 29 01:43:36 PM PST 24 3726821841 ps
T511 /workspace/coverage/default/27.sysrst_ctrl_auto_blk_key_output.2724890947 Feb 29 01:43:39 PM PST 24 Feb 29 01:43:48 PM PST 24 3095665779 ps
T512 /workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.2501237103 Feb 29 01:42:49 PM PST 24 Feb 29 01:43:00 PM PST 24 21898005198 ps
T150 /workspace/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.1694732795 Feb 29 01:43:52 PM PST 24 Feb 29 01:46:50 PM PST 24 70487959590 ps
T513 /workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.2437101528 Feb 29 01:44:30 PM PST 24 Feb 29 01:45:59 PM PST 24 35725056793 ps
T514 /workspace/coverage/default/1.sysrst_ctrl_auto_blk_key_output.710298548 Feb 29 01:42:29 PM PST 24 Feb 29 01:42:32 PM PST 24 3842193368 ps
T515 /workspace/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.1387819851 Feb 29 01:43:07 PM PST 24 Feb 29 01:43:10 PM PST 24 4000152682 ps
T516 /workspace/coverage/default/17.sysrst_ctrl_pin_access_test.2468848863 Feb 29 01:43:07 PM PST 24 Feb 29 01:43:09 PM PST 24 2274266690 ps
T517 /workspace/coverage/default/2.sysrst_ctrl_auto_blk_key_output.4270853975 Feb 29 01:42:51 PM PST 24 Feb 29 01:42:53 PM PST 24 3174984974 ps
T186 /workspace/coverage/default/25.sysrst_ctrl_edge_detect.2123656453 Feb 29 01:43:37 PM PST 24 Feb 29 01:43:40 PM PST 24 5121809769 ps
T146 /workspace/coverage/default/16.sysrst_ctrl_ultra_low_pwr.2144841556 Feb 29 01:43:14 PM PST 24 Feb 29 01:43:18 PM PST 24 6062111765 ps
T518 /workspace/coverage/default/28.sysrst_ctrl_smoke.1790549183 Feb 29 01:43:40 PM PST 24 Feb 29 01:43:42 PM PST 24 2133468235 ps
T519 /workspace/coverage/default/8.sysrst_ctrl_pin_override_test.3891154438 Feb 29 01:42:51 PM PST 24 Feb 29 01:42:59 PM PST 24 2508671247 ps
T352 /workspace/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.199414976 Feb 29 01:43:22 PM PST 24 Feb 29 01:43:49 PM PST 24 36348795227 ps
T520 /workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.3594485637 Feb 29 01:44:13 PM PST 24 Feb 29 01:44:20 PM PST 24 2440150622 ps
T521 /workspace/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.3897924523 Feb 29 01:43:53 PM PST 24 Feb 29 01:43:58 PM PST 24 3086183975 ps
T522 /workspace/coverage/default/4.sysrst_ctrl_pin_override_test.1613883465 Feb 29 01:42:49 PM PST 24 Feb 29 01:42:52 PM PST 24 2524067429 ps
T523 /workspace/coverage/default/15.sysrst_ctrl_pin_access_test.1131579057 Feb 29 01:43:14 PM PST 24 Feb 29 01:43:20 PM PST 24 2061489227 ps
T86 /workspace/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.1949191811 Feb 29 01:44:08 PM PST 24 Feb 29 01:47:05 PM PST 24 127554946576 ps
T298 /workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.3449096472 Feb 29 01:44:26 PM PST 24 Feb 29 01:45:36 PM PST 24 27061770990 ps
T524 /workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.2119194214 Feb 29 01:44:30 PM PST 24 Feb 29 01:44:37 PM PST 24 2608263368 ps
T525 /workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.2681766221 Feb 29 01:44:47 PM PST 24 Feb 29 01:44:49 PM PST 24 3429327517 ps
T526 /workspace/coverage/default/34.sysrst_ctrl_edge_detect.1196502254 Feb 29 01:43:52 PM PST 24 Feb 29 01:43:54 PM PST 24 2537082187 ps
T527 /workspace/coverage/default/22.sysrst_ctrl_pin_access_test.2675101277 Feb 29 01:43:21 PM PST 24 Feb 29 01:43:23 PM PST 24 2158651055 ps
T157 /workspace/coverage/default/7.sysrst_ctrl_edge_detect.151385668 Feb 29 01:42:51 PM PST 24 Feb 29 01:42:58 PM PST 24 4635660863 ps
T528 /workspace/coverage/default/30.sysrst_ctrl_edge_detect.2207717645 Feb 29 01:43:54 PM PST 24 Feb 29 01:44:00 PM PST 24 325747660414 ps
T529 /workspace/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.1921256213 Feb 29 01:42:46 PM PST 24 Feb 29 01:42:54 PM PST 24 4836182561 ps
T530 /workspace/coverage/default/24.sysrst_ctrl_smoke.3901294928 Feb 29 01:43:31 PM PST 24 Feb 29 01:43:33 PM PST 24 2131329968 ps
T246 /workspace/coverage/default/5.sysrst_ctrl_combo_detect.658785155 Feb 29 01:42:45 PM PST 24 Feb 29 01:43:46 PM PST 24 65794595200 ps
T187 /workspace/coverage/default/26.sysrst_ctrl_edge_detect.2742904330 Feb 29 01:43:40 PM PST 24 Feb 29 01:43:43 PM PST 24 5228861623 ps
T531 /workspace/coverage/default/0.sysrst_ctrl_smoke.4268416038 Feb 29 01:42:27 PM PST 24 Feb 29 01:42:29 PM PST 24 2138424431 ps
T532 /workspace/coverage/default/26.sysrst_ctrl_stress_all.126802128 Feb 29 01:43:41 PM PST 24 Feb 29 01:44:00 PM PST 24 7020414397 ps
T381 /workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.143038946 Feb 29 01:44:45 PM PST 24 Feb 29 01:45:13 PM PST 24 108967764859 ps
T533 /workspace/coverage/default/32.sysrst_ctrl_pin_access_test.3849184746 Feb 29 01:43:52 PM PST 24 Feb 29 01:43:58 PM PST 24 2111189857 ps
T216 /workspace/coverage/default/44.sysrst_ctrl_edge_detect.290887276 Feb 29 01:44:25 PM PST 24 Feb 29 01:44:36 PM PST 24 5283508254 ps
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