Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
791 |
1 |
|
|
T48 |
9 |
|
T15 |
14 |
|
T49 |
8 |
| auto[1] |
709 |
1 |
|
|
T48 |
11 |
|
T15 |
6 |
|
T49 |
12 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
751 |
1 |
|
|
T48 |
8 |
|
T15 |
11 |
|
T49 |
9 |
| auto[1] |
749 |
1 |
|
|
T48 |
12 |
|
T15 |
9 |
|
T49 |
11 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
775 |
1 |
|
|
T48 |
10 |
|
T15 |
11 |
|
T49 |
11 |
| auto[1] |
725 |
1 |
|
|
T48 |
10 |
|
T15 |
9 |
|
T49 |
9 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
737 |
1 |
|
|
T48 |
11 |
|
T15 |
12 |
|
T49 |
13 |
| auto[1] |
763 |
1 |
|
|
T48 |
9 |
|
T15 |
8 |
|
T49 |
7 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
757 |
1 |
|
|
T48 |
12 |
|
T15 |
11 |
|
T49 |
11 |
| auto[1] |
743 |
1 |
|
|
T48 |
8 |
|
T15 |
9 |
|
T49 |
9 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
764 |
1 |
|
|
T48 |
9 |
|
T15 |
7 |
|
T49 |
11 |
| auto[1] |
736 |
1 |
|
|
T48 |
11 |
|
T15 |
13 |
|
T49 |
9 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
759 |
1 |
|
|
T48 |
12 |
|
T15 |
12 |
|
T49 |
12 |
| auto[1] |
741 |
1 |
|
|
T48 |
8 |
|
T15 |
8 |
|
T49 |
8 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
725 |
1 |
|
|
T48 |
7 |
|
T15 |
8 |
|
T49 |
10 |
| auto[1] |
775 |
1 |
|
|
T48 |
13 |
|
T15 |
12 |
|
T49 |
10 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
736 |
1 |
|
|
T48 |
8 |
|
T15 |
10 |
|
T49 |
7 |
| auto[1] |
764 |
1 |
|
|
T48 |
12 |
|
T15 |
10 |
|
T49 |
13 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
732 |
1 |
|
|
T48 |
8 |
|
T15 |
12 |
|
T49 |
8 |
| auto[1] |
768 |
1 |
|
|
T48 |
12 |
|
T15 |
8 |
|
T49 |
12 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
747 |
1 |
|
|
T48 |
10 |
|
T15 |
9 |
|
T49 |
9 |
| auto[1] |
753 |
1 |
|
|
T48 |
10 |
|
T15 |
11 |
|
T49 |
11 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
751 |
1 |
|
|
T48 |
14 |
|
T15 |
8 |
|
T49 |
11 |
| auto[1] |
749 |
1 |
|
|
T48 |
6 |
|
T15 |
12 |
|
T49 |
9 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
767 |
1 |
|
|
T48 |
8 |
|
T15 |
10 |
|
T49 |
11 |
| auto[1] |
733 |
1 |
|
|
T48 |
12 |
|
T15 |
10 |
|
T49 |
9 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
751 |
1 |
|
|
T48 |
8 |
|
T15 |
11 |
|
T49 |
9 |
| auto[1] |
749 |
1 |
|
|
T48 |
12 |
|
T15 |
9 |
|
T49 |
11 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
723 |
1 |
|
|
T48 |
13 |
|
T15 |
9 |
|
T49 |
9 |
| auto[1] |
777 |
1 |
|
|
T48 |
7 |
|
T15 |
11 |
|
T49 |
11 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
713 |
1 |
|
|
T48 |
14 |
|
T15 |
12 |
|
T49 |
7 |
| auto[1] |
787 |
1 |
|
|
T48 |
6 |
|
T15 |
8 |
|
T49 |
13 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
740 |
1 |
|
|
T48 |
7 |
|
T15 |
8 |
|
T49 |
5 |
| auto[1] |
760 |
1 |
|
|
T48 |
13 |
|
T15 |
12 |
|
T49 |
15 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
753 |
1 |
|
|
T48 |
10 |
|
T15 |
12 |
|
T49 |
9 |
| auto[1] |
747 |
1 |
|
|
T48 |
10 |
|
T15 |
8 |
|
T49 |
11 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
747 |
1 |
|
|
T48 |
10 |
|
T15 |
13 |
|
T49 |
10 |
| auto[1] |
753 |
1 |
|
|
T48 |
10 |
|
T15 |
7 |
|
T49 |
10 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
765 |
1 |
|
|
T48 |
11 |
|
T15 |
11 |
|
T49 |
12 |
| auto[1] |
735 |
1 |
|
|
T48 |
9 |
|
T15 |
9 |
|
T49 |
8 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
721 |
1 |
|
|
T48 |
11 |
|
T15 |
10 |
|
T49 |
11 |
| auto[1] |
779 |
1 |
|
|
T48 |
9 |
|
T15 |
10 |
|
T49 |
9 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
772 |
1 |
|
|
T48 |
10 |
|
T15 |
10 |
|
T49 |
10 |
| auto[1] |
728 |
1 |
|
|
T48 |
10 |
|
T15 |
10 |
|
T49 |
10 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
777 |
1 |
|
|
T48 |
8 |
|
T15 |
9 |
|
T49 |
11 |
| auto[1] |
723 |
1 |
|
|
T48 |
12 |
|
T15 |
11 |
|
T49 |
9 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
751 |
1 |
|
|
T48 |
14 |
|
T15 |
8 |
|
T49 |
11 |
| auto[1] |
749 |
1 |
|
|
T48 |
6 |
|
T15 |
12 |
|
T49 |
9 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
373 |
1 |
|
|
T48 |
5 |
|
T15 |
3 |
|
T49 |
3 |
| auto[0] |
auto[1] |
350 |
1 |
|
|
T48 |
8 |
|
T15 |
6 |
|
T49 |
6 |
| auto[1] |
auto[0] |
402 |
1 |
|
|
T48 |
5 |
|
T15 |
8 |
|
T49 |
8 |
| auto[1] |
auto[1] |
375 |
1 |
|
|
T48 |
2 |
|
T15 |
3 |
|
T49 |
3 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
349 |
1 |
|
|
T48 |
6 |
|
T15 |
5 |
|
T49 |
3 |
| auto[0] |
auto[1] |
364 |
1 |
|
|
T48 |
8 |
|
T15 |
7 |
|
T49 |
4 |
| auto[1] |
auto[0] |
388 |
1 |
|
|
T48 |
5 |
|
T15 |
7 |
|
T49 |
10 |
| auto[1] |
auto[1] |
399 |
1 |
|
|
T48 |
1 |
|
T15 |
1 |
|
T49 |
3 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
360 |
1 |
|
|
T48 |
5 |
|
T15 |
4 |
|
T49 |
2 |
| auto[0] |
auto[1] |
380 |
1 |
|
|
T48 |
2 |
|
T15 |
4 |
|
T49 |
3 |
| auto[1] |
auto[0] |
397 |
1 |
|
|
T48 |
7 |
|
T15 |
7 |
|
T49 |
9 |
| auto[1] |
auto[1] |
363 |
1 |
|
|
T48 |
6 |
|
T15 |
5 |
|
T49 |
6 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
370 |
1 |
|
|
T48 |
5 |
|
T15 |
4 |
|
T49 |
4 |
| auto[0] |
auto[1] |
383 |
1 |
|
|
T48 |
5 |
|
T15 |
8 |
|
T49 |
5 |
| auto[1] |
auto[0] |
394 |
1 |
|
|
T48 |
4 |
|
T15 |
3 |
|
T49 |
7 |
| auto[1] |
auto[1] |
353 |
1 |
|
|
T48 |
6 |
|
T15 |
5 |
|
T49 |
4 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
364 |
1 |
|
|
T48 |
6 |
|
T15 |
7 |
|
T49 |
7 |
| auto[0] |
auto[1] |
383 |
1 |
|
|
T48 |
4 |
|
T15 |
6 |
|
T49 |
3 |
| auto[1] |
auto[0] |
395 |
1 |
|
|
T48 |
6 |
|
T15 |
5 |
|
T49 |
5 |
| auto[1] |
auto[1] |
358 |
1 |
|
|
T48 |
4 |
|
T15 |
2 |
|
T49 |
5 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
356 |
1 |
|
|
T48 |
4 |
|
T15 |
4 |
|
T49 |
7 |
| auto[0] |
auto[1] |
409 |
1 |
|
|
T48 |
7 |
|
T15 |
7 |
|
T49 |
5 |
| auto[1] |
auto[0] |
369 |
1 |
|
|
T48 |
3 |
|
T15 |
4 |
|
T49 |
3 |
| auto[1] |
auto[1] |
366 |
1 |
|
|
T48 |
6 |
|
T15 |
5 |
|
T49 |
5 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
355 |
1 |
|
|
T48 |
3 |
|
T15 |
6 |
|
T49 |
3 |
| auto[0] |
auto[1] |
417 |
1 |
|
|
T48 |
7 |
|
T15 |
4 |
|
T49 |
7 |
| auto[1] |
auto[0] |
377 |
1 |
|
|
T48 |
5 |
|
T15 |
6 |
|
T49 |
5 |
| auto[1] |
auto[1] |
351 |
1 |
|
|
T48 |
5 |
|
T15 |
4 |
|
T49 |
5 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
365 |
1 |
|
|
T48 |
3 |
|
T15 |
4 |
|
T49 |
4 |
| auto[0] |
auto[1] |
412 |
1 |
|
|
T48 |
5 |
|
T15 |
5 |
|
T49 |
7 |
| auto[1] |
auto[0] |
382 |
1 |
|
|
T48 |
7 |
|
T15 |
5 |
|
T49 |
5 |
| auto[1] |
auto[1] |
341 |
1 |
|
|
T48 |
5 |
|
T15 |
6 |
|
T49 |
4 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
418 |
1 |
|
|
T48 |
4 |
|
T15 |
5 |
|
T49 |
6 |
| auto[0] |
auto[1] |
349 |
1 |
|
|
T48 |
4 |
|
T15 |
5 |
|
T49 |
5 |
| auto[1] |
auto[0] |
373 |
1 |
|
|
T48 |
5 |
|
T15 |
9 |
|
T49 |
2 |
| auto[1] |
auto[1] |
360 |
1 |
|
|
T48 |
7 |
|
T15 |
1 |
|
T49 |
7 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
751 |
1 |
|
|
T48 |
8 |
|
T15 |
11 |
|
T49 |
9 |
| auto[1] |
auto[1] |
749 |
1 |
|
|
T48 |
12 |
|
T15 |
9 |
|
T49 |
11 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
342 |
1 |
|
|
T48 |
5 |
|
T15 |
4 |
|
T49 |
4 |
| auto[0] |
auto[1] |
379 |
1 |
|
|
T48 |
6 |
|
T15 |
6 |
|
T49 |
7 |
| auto[1] |
auto[0] |
394 |
1 |
|
|
T48 |
3 |
|
T15 |
6 |
|
T49 |
3 |
| auto[1] |
auto[1] |
385 |
1 |
|
|
T48 |
6 |
|
T15 |
4 |
|
T49 |
6 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
751 |
1 |
|
|
T48 |
14 |
|
T15 |
8 |
|
T49 |
11 |
| auto[1] |
auto[1] |
749 |
1 |
|
|
T48 |
6 |
|
T15 |
12 |
|
T49 |
9 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
145 |
1 |
|
|
T15 |
12 |
|
T56 |
8 |
|
T95 |
10 |
| auto[1] |
115 |
1 |
|
|
T15 |
8 |
|
T56 |
12 |
|
T95 |
10 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
133 |
1 |
|
|
T15 |
11 |
|
T56 |
14 |
|
T95 |
7 |
| auto[1] |
127 |
1 |
|
|
T15 |
9 |
|
T56 |
6 |
|
T95 |
13 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
123 |
1 |
|
|
T15 |
10 |
|
T56 |
13 |
|
T95 |
6 |
| auto[1] |
137 |
1 |
|
|
T15 |
10 |
|
T56 |
7 |
|
T95 |
14 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
142 |
1 |
|
|
T15 |
11 |
|
T56 |
10 |
|
T95 |
6 |
| auto[1] |
118 |
1 |
|
|
T15 |
9 |
|
T56 |
10 |
|
T95 |
14 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
123 |
1 |
|
|
T15 |
9 |
|
T56 |
11 |
|
T95 |
10 |
| auto[1] |
137 |
1 |
|
|
T15 |
11 |
|
T56 |
9 |
|
T95 |
10 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
126 |
1 |
|
|
T15 |
9 |
|
T56 |
10 |
|
T95 |
12 |
| auto[1] |
134 |
1 |
|
|
T15 |
11 |
|
T56 |
10 |
|
T95 |
8 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
131 |
1 |
|
|
T15 |
12 |
|
T56 |
10 |
|
T95 |
10 |
| auto[1] |
129 |
1 |
|
|
T15 |
8 |
|
T56 |
10 |
|
T95 |
10 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
139 |
1 |
|
|
T15 |
9 |
|
T56 |
12 |
|
T95 |
13 |
| auto[1] |
121 |
1 |
|
|
T15 |
11 |
|
T56 |
8 |
|
T95 |
7 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
127 |
1 |
|
|
T15 |
10 |
|
T56 |
7 |
|
T95 |
7 |
| auto[1] |
133 |
1 |
|
|
T15 |
10 |
|
T56 |
13 |
|
T95 |
13 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
129 |
1 |
|
|
T15 |
13 |
|
T56 |
7 |
|
T95 |
11 |
| auto[1] |
131 |
1 |
|
|
T15 |
7 |
|
T56 |
13 |
|
T95 |
9 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
129 |
1 |
|
|
T15 |
6 |
|
T56 |
12 |
|
T95 |
11 |
| auto[1] |
131 |
1 |
|
|
T15 |
14 |
|
T56 |
8 |
|
T95 |
9 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
143 |
1 |
|
|
T15 |
8 |
|
T56 |
13 |
|
T95 |
11 |
| auto[1] |
117 |
1 |
|
|
T15 |
12 |
|
T56 |
7 |
|
T95 |
9 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
123 |
1 |
|
|
T15 |
9 |
|
T56 |
9 |
|
T95 |
8 |
| auto[1] |
137 |
1 |
|
|
T15 |
11 |
|
T56 |
11 |
|
T95 |
12 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
133 |
1 |
|
|
T15 |
11 |
|
T56 |
14 |
|
T95 |
7 |
| auto[1] |
127 |
1 |
|
|
T15 |
9 |
|
T56 |
6 |
|
T95 |
13 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
119 |
1 |
|
|
T15 |
8 |
|
T56 |
16 |
|
T95 |
7 |
| auto[1] |
141 |
1 |
|
|
T15 |
12 |
|
T56 |
4 |
|
T95 |
13 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
132 |
1 |
|
|
T15 |
9 |
|
T56 |
11 |
|
T95 |
9 |
| auto[1] |
128 |
1 |
|
|
T15 |
11 |
|
T56 |
9 |
|
T95 |
11 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
126 |
1 |
|
|
T15 |
10 |
|
T56 |
9 |
|
T95 |
9 |
| auto[1] |
134 |
1 |
|
|
T15 |
10 |
|
T56 |
11 |
|
T95 |
11 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
145 |
1 |
|
|
T15 |
10 |
|
T56 |
6 |
|
T95 |
15 |
| auto[1] |
115 |
1 |
|
|
T15 |
10 |
|
T56 |
14 |
|
T95 |
5 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
136 |
1 |
|
|
T15 |
10 |
|
T56 |
9 |
|
T95 |
9 |
| auto[1] |
124 |
1 |
|
|
T15 |
10 |
|
T56 |
11 |
|
T95 |
11 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
136 |
1 |
|
|
T15 |
9 |
|
T56 |
9 |
|
T95 |
12 |
| auto[1] |
124 |
1 |
|
|
T15 |
11 |
|
T56 |
11 |
|
T95 |
8 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
122 |
1 |
|
|
T15 |
10 |
|
T56 |
9 |
|
T95 |
10 |
| auto[1] |
138 |
1 |
|
|
T15 |
10 |
|
T56 |
11 |
|
T95 |
10 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
119 |
1 |
|
|
T15 |
10 |
|
T56 |
9 |
|
T95 |
8 |
| auto[1] |
141 |
1 |
|
|
T15 |
10 |
|
T56 |
11 |
|
T95 |
12 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
141 |
1 |
|
|
T15 |
7 |
|
T56 |
14 |
|
T95 |
14 |
| auto[1] |
119 |
1 |
|
|
T15 |
13 |
|
T56 |
6 |
|
T95 |
6 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
143 |
1 |
|
|
T15 |
8 |
|
T56 |
13 |
|
T95 |
11 |
| auto[1] |
117 |
1 |
|
|
T15 |
12 |
|
T56 |
7 |
|
T95 |
9 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
57 |
1 |
|
|
T15 |
4 |
|
T56 |
11 |
|
T95 |
2 |
| auto[0] |
auto[1] |
62 |
1 |
|
|
T15 |
4 |
|
T56 |
5 |
|
T95 |
5 |
| auto[1] |
auto[0] |
66 |
1 |
|
|
T15 |
6 |
|
T56 |
2 |
|
T95 |
4 |
| auto[1] |
auto[1] |
75 |
1 |
|
|
T15 |
6 |
|
T56 |
2 |
|
T95 |
9 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
73 |
1 |
|
|
T15 |
5 |
|
T56 |
7 |
|
T95 |
3 |
| auto[0] |
auto[1] |
59 |
1 |
|
|
T15 |
4 |
|
T56 |
4 |
|
T95 |
6 |
| auto[1] |
auto[0] |
69 |
1 |
|
|
T15 |
6 |
|
T56 |
3 |
|
T95 |
3 |
| auto[1] |
auto[1] |
59 |
1 |
|
|
T15 |
5 |
|
T56 |
6 |
|
T95 |
8 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
55 |
1 |
|
|
T15 |
3 |
|
T56 |
5 |
|
T95 |
4 |
| auto[0] |
auto[1] |
71 |
1 |
|
|
T15 |
7 |
|
T56 |
4 |
|
T95 |
5 |
| auto[1] |
auto[0] |
68 |
1 |
|
|
T15 |
6 |
|
T56 |
6 |
|
T95 |
6 |
| auto[1] |
auto[1] |
66 |
1 |
|
|
T15 |
4 |
|
T56 |
5 |
|
T95 |
5 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
66 |
1 |
|
|
T15 |
3 |
|
T56 |
3 |
|
T95 |
8 |
| auto[0] |
auto[1] |
79 |
1 |
|
|
T15 |
7 |
|
T56 |
3 |
|
T95 |
7 |
| auto[1] |
auto[0] |
60 |
1 |
|
|
T15 |
6 |
|
T56 |
7 |
|
T95 |
4 |
| auto[1] |
auto[1] |
55 |
1 |
|
|
T15 |
4 |
|
T56 |
7 |
|
T95 |
1 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
76 |
1 |
|
|
T15 |
6 |
|
T56 |
7 |
|
T95 |
6 |
| auto[0] |
auto[1] |
60 |
1 |
|
|
T15 |
4 |
|
T56 |
2 |
|
T95 |
3 |
| auto[1] |
auto[0] |
55 |
1 |
|
|
T15 |
6 |
|
T56 |
3 |
|
T95 |
4 |
| auto[1] |
auto[1] |
69 |
1 |
|
|
T15 |
4 |
|
T56 |
8 |
|
T95 |
7 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
80 |
1 |
|
|
T15 |
4 |
|
T56 |
8 |
|
T95 |
9 |
| auto[0] |
auto[1] |
56 |
1 |
|
|
T15 |
5 |
|
T56 |
1 |
|
T95 |
3 |
| auto[1] |
auto[0] |
59 |
1 |
|
|
T15 |
5 |
|
T56 |
4 |
|
T95 |
4 |
| auto[1] |
auto[1] |
65 |
1 |
|
|
T15 |
6 |
|
T56 |
7 |
|
T95 |
4 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
70 |
1 |
|
|
T15 |
10 |
|
T56 |
4 |
|
T95 |
6 |
| auto[0] |
auto[1] |
49 |
1 |
|
|
T56 |
5 |
|
T95 |
2 |
|
T393 |
4 |
| auto[1] |
auto[0] |
59 |
1 |
|
|
T15 |
3 |
|
T56 |
3 |
|
T95 |
5 |
| auto[1] |
auto[1] |
82 |
1 |
|
|
T15 |
7 |
|
T56 |
8 |
|
T95 |
7 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
81 |
1 |
|
|
T15 |
5 |
|
T56 |
9 |
|
T95 |
9 |
| auto[0] |
auto[1] |
60 |
1 |
|
|
T15 |
2 |
|
T56 |
5 |
|
T95 |
5 |
| auto[1] |
auto[0] |
48 |
1 |
|
|
T15 |
1 |
|
T56 |
3 |
|
T95 |
2 |
| auto[1] |
auto[1] |
71 |
1 |
|
|
T15 |
12 |
|
T56 |
3 |
|
T95 |
4 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
65 |
1 |
|
|
T15 |
6 |
|
T56 |
2 |
|
T95 |
2 |
| auto[0] |
auto[1] |
58 |
1 |
|
|
T15 |
3 |
|
T56 |
7 |
|
T95 |
6 |
| auto[1] |
auto[0] |
80 |
1 |
|
|
T15 |
6 |
|
T56 |
6 |
|
T95 |
8 |
| auto[1] |
auto[1] |
57 |
1 |
|
|
T15 |
5 |
|
T56 |
5 |
|
T95 |
4 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
133 |
1 |
|
|
T15 |
11 |
|
T56 |
14 |
|
T95 |
7 |
| auto[1] |
auto[1] |
127 |
1 |
|
|
T15 |
9 |
|
T56 |
6 |
|
T95 |
13 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
58 |
1 |
|
|
T15 |
4 |
|
T56 |
5 |
|
T95 |
5 |
| auto[0] |
auto[1] |
64 |
1 |
|
|
T15 |
6 |
|
T56 |
4 |
|
T95 |
5 |
| auto[1] |
auto[0] |
69 |
1 |
|
|
T15 |
6 |
|
T56 |
2 |
|
T95 |
2 |
| auto[1] |
auto[1] |
69 |
1 |
|
|
T15 |
4 |
|
T56 |
9 |
|
T95 |
8 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
143 |
1 |
|
|
T15 |
8 |
|
T56 |
13 |
|
T95 |
11 |
| auto[1] |
auto[1] |
117 |
1 |
|
|
T15 |
12 |
|
T56 |
7 |
|
T95 |
9 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
31 |
1 |
|
|
T391 |
8 |
|
T320 |
13 |
|
T287 |
10 |
| auto[1] |
29 |
1 |
|
|
T391 |
12 |
|
T320 |
7 |
|
T287 |
10 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
30 |
1 |
|
|
T391 |
12 |
|
T320 |
7 |
|
T287 |
11 |
| auto[1] |
30 |
1 |
|
|
T391 |
8 |
|
T320 |
13 |
|
T287 |
9 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19 |
1 |
|
|
T391 |
7 |
|
T320 |
6 |
|
T287 |
6 |
| auto[1] |
41 |
1 |
|
|
T391 |
13 |
|
T320 |
14 |
|
T287 |
14 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
28 |
1 |
|
|
T391 |
11 |
|
T320 |
9 |
|
T287 |
8 |
| auto[1] |
32 |
1 |
|
|
T391 |
9 |
|
T320 |
11 |
|
T287 |
12 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
30 |
1 |
|
|
T391 |
10 |
|
T320 |
10 |
|
T287 |
10 |
| auto[1] |
30 |
1 |
|
|
T391 |
10 |
|
T320 |
10 |
|
T287 |
10 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
29 |
1 |
|
|
T391 |
14 |
|
T320 |
8 |
|
T287 |
7 |
| auto[1] |
31 |
1 |
|
|
T391 |
6 |
|
T320 |
12 |
|
T287 |
13 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
32 |
1 |
|
|
T391 |
10 |
|
T320 |
11 |
|
T287 |
11 |
| auto[1] |
28 |
1 |
|
|
T391 |
10 |
|
T320 |
9 |
|
T287 |
9 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
33 |
1 |
|
|
T391 |
9 |
|
T320 |
12 |
|
T287 |
12 |
| auto[1] |
27 |
1 |
|
|
T391 |
11 |
|
T320 |
8 |
|
T287 |
8 |