Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.57	99.31	96.07	100.00	96.15	98.68	99.16	93.64

Total tests in report: 907

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
57.37	57.37	73.52	73.52	63.42	63.42	91.00	91.00	18.59	18.59	76.54	76.54	65.92	65.92	12.61	12.61	/workspace/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.2344233919
74.30	16.93	88.80	15.28	81.45	18.03	94.08	3.08	44.87	26.28	90.01	13.47	79.78	13.86	41.14	28.53	/workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.4142300186
81.06	6.76	93.92	5.12	87.19	5.75	95.67	1.59	60.90	16.03	93.87	3.86	88.11	8.33	47.75	6.61	/workspace/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.4158202744
85.96	4.90	95.16	1.23	88.27	1.07	96.13	0.46	75.64	14.74	95.02	1.15	94.57	6.46	56.96	9.21	/workspace/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.473386060
87.96	2.00	96.09	0.94	90.01	1.74	96.13	0.00	85.90	10.26	96.07	1.04	94.57	0.00	56.96	0.00	/workspace/coverage/default/0.sysrst_ctrl_feature_disable.152061030
89.28	1.32	96.09	0.00	90.01	0.00	96.13	0.00	85.90	0.00	96.07	0.00	94.57	0.00	66.22	9.26	/workspace/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.562156915
90.54	1.26	97.52	1.42	91.25	1.24	96.47	0.34	87.18	1.28	96.94	0.87	95.41	0.84	69.02	2.80	/workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.835191193
91.78	1.24	97.59	0.07	92.49	1.24	97.15	0.68	87.18	0.00	97.04	0.10	95.69	0.28	75.33	6.31	/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.2826727734
92.52	0.74	97.85	0.26	92.80	0.31	97.15	0.00	89.74	2.56	97.35	0.31	96.44	0.75	76.33	1.00	/workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.2082299948
93.19	0.66	97.85	0.00	92.80	0.00	97.15	0.00	89.74	0.00	97.35	0.00	96.44	0.00	80.98	4.65	/workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.2832653406
93.76	0.57	98.16	0.31	92.85	0.05	97.15	0.00	92.95	3.21	97.67	0.31	96.54	0.09	80.98	0.00	/workspace/coverage/default/1.sysrst_ctrl_feature_disable.2240736272
94.17	0.42	98.56	0.40	93.13	0.29	97.84	0.68	93.59	0.64	97.91	0.24	97.19	0.66	80.98	0.00	/workspace/coverage/default/9.sysrst_ctrl_edge_detect.943475189
94.56	0.39	98.63	0.07	93.32	0.19	97.84	0.00	94.23	0.64	97.95	0.03	97.28	0.09	82.68	1.70	/workspace/coverage/default/39.sysrst_ctrl_stress_all.3067500448
94.90	0.34	98.77	0.14	93.37	0.05	97.95	0.11	95.51	1.28	98.02	0.07	97.38	0.09	83.28	0.60	/workspace/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.2559989250
95.18	0.28	98.77	0.00	93.39	0.02	99.54	1.59	95.51	0.00	98.02	0.00	97.47	0.09	83.53	0.25	/workspace/coverage/default/1.sysrst_ctrl_sec_cm.4050396523
95.43	0.25	98.91	0.14	93.87	0.48	99.54	0.00	95.51	0.00	98.29	0.28	98.13	0.66	83.73	0.20	/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.2106291858
95.67	0.24	98.94	0.03	94.01	0.14	99.54	0.00	95.51	0.00	98.29	0.00	98.13	0.00	85.24	1.50	/workspace/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.3399477888
95.84	0.17	98.94	0.00	94.01	0.00	99.54	0.00	95.51	0.00	98.29	0.00	98.13	0.00	86.44	1.20	/workspace/coverage/default/22.sysrst_ctrl_combo_detect.650472965
96.01	0.17	98.94	0.00	94.59	0.57	99.54	0.00	95.51	0.00	98.29	0.00	98.13	0.00	87.04	0.60	/workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.116779837
96.16	0.15	98.99	0.05	94.68	0.10	99.54	0.00	95.51	0.00	98.29	0.00	98.13	0.00	87.94	0.90	/workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.1662007599
96.29	0.14	99.03	0.03	94.75	0.07	99.54	0.00	96.15	0.64	98.33	0.03	98.31	0.19	87.94	0.00	/workspace/coverage/default/30.sysrst_ctrl_edge_detect.2636213814
96.42	0.13	99.04	0.02	94.75	0.00	99.77	0.23	96.15	0.00	98.33	0.00	98.41	0.09	88.49	0.55	/workspace/coverage/default/3.sysrst_ctrl_pin_override_test.250565823
96.51	0.09	99.04	0.00	94.75	0.00	99.77	0.00	96.15	0.00	98.33	0.00	98.41	0.00	89.09	0.60	/workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.256284075
96.59	0.08	99.04	0.00	94.75	0.00	99.77	0.00	96.15	0.00	98.33	0.00	98.41	0.00	89.64	0.55	/workspace/coverage/default/3.sysrst_ctrl_stress_all.95271886
96.66	0.07	99.04	0.00	94.78	0.02	99.77	0.00	96.15	0.00	98.33	0.00	98.41	0.00	90.14	0.50	/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.186858283
96.73	0.07	99.06	0.02	94.87	0.10	99.77	0.00	96.15	0.00	98.36	0.03	98.60	0.19	90.29	0.15	/workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.100966214
96.79	0.06	99.11	0.05	94.87	0.00	99.77	0.00	96.15	0.00	98.50	0.14	98.69	0.09	90.44	0.15	/workspace/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.1671625952
96.85	0.06	99.13	0.02	94.87	0.00	99.77	0.00	96.15	0.00	98.50	0.00	98.69	0.00	90.84	0.40	/workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.307320069
96.91	0.05	99.13	0.00	95.25	0.38	99.77	0.00	96.15	0.00	98.50	0.00	98.69	0.00	90.84	0.00	/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.3457459303
96.96	0.05	99.18	0.05	95.33	0.07	100.00	0.23	96.15	0.00	98.50	0.00	98.69	0.00	90.84	0.00	/workspace/coverage/default/0.sysrst_ctrl_alert_test.57151811
97.01	0.05	99.18	0.00	95.33	0.00	100.00	0.00	96.15	0.00	98.50	0.00	98.69	0.00	91.19	0.35	/workspace/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.1907174180
97.05	0.05	99.18	0.00	95.61	0.29	100.00	0.00	96.15	0.00	98.50	0.00	98.69	0.00	91.24	0.05	/workspace/coverage/default/21.sysrst_ctrl_ultra_low_pwr.3577205066
97.10	0.04	99.18	0.00	95.61	0.00	100.00	0.00	96.15	0.00	98.50	0.00	98.69	0.00	91.54	0.30	/workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.3288383828
97.14	0.04	99.18	0.00	95.64	0.02	100.00	0.00	96.15	0.00	98.50	0.00	98.78	0.09	91.69	0.15	/workspace/coverage/default/46.sysrst_ctrl_combo_detect.1435219930
97.17	0.04	99.18	0.00	95.64	0.00	100.00	0.00	96.15	0.00	98.50	0.00	98.78	0.00	91.94	0.25	/workspace/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.135146104
97.21	0.03	99.18	0.00	95.68	0.05	100.00	0.00	96.15	0.00	98.50	0.00	98.88	0.09	92.04	0.10	/workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.543906864
97.24	0.03	99.18	0.00	95.92	0.24	100.00	0.00	96.15	0.00	98.50	0.00	98.88	0.00	92.04	0.00	/workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.2930346104
97.27	0.03	99.20	0.02	95.99	0.07	100.00	0.00	96.15	0.00	98.54	0.03	98.97	0.09	92.04	0.00	/workspace/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.2284358978
97.30	0.03	99.20	0.00	95.99	0.00	100.00	0.00	96.15	0.00	98.54	0.00	98.97	0.00	92.24	0.20	/workspace/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.242374910
97.33	0.03	99.20	0.00	95.99	0.00	100.00	0.00	96.15	0.00	98.54	0.00	98.97	0.00	92.44	0.20	/workspace/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.4074733503
97.35	0.02	99.25	0.05	95.99	0.00	100.00	0.00	96.15	0.00	98.64	0.10	98.97	0.00	92.44	0.00	/workspace/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.2065947973
97.37	0.02	99.25	0.00	95.99	0.00	100.00	0.00	96.15	0.00	98.64	0.00	98.97	0.00	92.59	0.15	/workspace/coverage/default/12.sysrst_ctrl_auto_blk_key_output.3369436376
97.39	0.02	99.25	0.00	95.99	0.00	100.00	0.00	96.15	0.00	98.64	0.00	98.97	0.00	92.74	0.15	/workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.2440076305
97.41	0.02	99.25	0.00	96.02	0.02	100.00	0.00	96.15	0.00	98.64	0.00	99.06	0.09	92.74	0.00	/workspace/coverage/default/17.sysrst_ctrl_edge_detect.1162176675
97.42	0.01	99.25	0.00	96.02	0.00	100.00	0.00	96.15	0.00	98.64	0.00	99.06	0.00	92.84	0.10	/workspace/coverage/default/21.sysrst_ctrl_stress_all.2741277234
97.44	0.01	99.25	0.00	96.02	0.00	100.00	0.00	96.15	0.00	98.64	0.00	99.06	0.00	92.94	0.10	/workspace/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.3626761266
97.45	0.01	99.25	0.00	96.02	0.00	100.00	0.00	96.15	0.00	98.64	0.00	99.06	0.00	93.04	0.10	/workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.2609480783
97.47	0.01	99.25	0.00	96.02	0.00	100.00	0.00	96.15	0.00	98.64	0.00	99.16	0.09	93.04	0.00	/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.1346070925
97.48	0.01	99.27	0.02	96.02	0.00	100.00	0.00	96.15	0.00	98.64	0.00	99.16	0.00	93.09	0.05	/workspace/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.3754242426
97.48	0.01	99.29	0.02	96.02	0.00	100.00	0.00	96.15	0.00	98.68	0.03	99.16	0.00	93.09	0.00	/workspace/coverage/default/42.sysrst_ctrl_edge_detect.2329394670
97.49	0.01	99.29	0.00	96.02	0.00	100.00	0.00	96.15	0.00	98.68	0.00	99.16	0.00	93.14	0.05	/workspace/coverage/default/0.sysrst_ctrl_combo_detect.461220544
97.50	0.01	99.29	0.00	96.02	0.00	100.00	0.00	96.15	0.00	98.68	0.00	99.16	0.00	93.19	0.05	/workspace/coverage/default/10.sysrst_ctrl_ultra_low_pwr.3078516318
97.51	0.01	99.29	0.00	96.02	0.00	100.00	0.00	96.15	0.00	98.68	0.00	99.16	0.00	93.24	0.05	/workspace/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.468733328
97.51	0.01	99.29	0.00	96.02	0.00	100.00	0.00	96.15	0.00	98.68	0.00	99.16	0.00	93.29	0.05	/workspace/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.694952554
97.52	0.01	99.29	0.00	96.02	0.00	100.00	0.00	96.15	0.00	98.68	0.00	99.16	0.00	93.34	0.05	/workspace/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.3909322196
97.53	0.01	99.29	0.00	96.02	0.00	100.00	0.00	96.15	0.00	98.68	0.00	99.16	0.00	93.39	0.05	/workspace/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.3652678803
97.53	0.01	99.29	0.00	96.02	0.00	100.00	0.00	96.15	0.00	98.68	0.00	99.16	0.00	93.44	0.05	/workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.1796551120
97.54	0.01	99.29	0.00	96.02	0.00	100.00	0.00	96.15	0.00	98.68	0.00	99.16	0.00	93.49	0.05	/workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.1004663007
97.55	0.01	99.29	0.00	96.02	0.00	100.00	0.00	96.15	0.00	98.68	0.00	99.16	0.00	93.54	0.05	/workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.880243657
97.56	0.01	99.29	0.00	96.02	0.00	100.00	0.00	96.15	0.00	98.68	0.00	99.16	0.00	93.59	0.05	/workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.2040073220
97.56	0.01	99.29	0.00	96.02	0.00	100.00	0.00	96.15	0.00	98.68	0.00	99.16	0.00	93.64	0.05	/workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.1945859217
97.57	0.01	99.29	0.00	96.04	0.02	100.00	0.00	96.15	0.00	98.68	0.00	99.16	0.00	93.64	0.00	/workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.1502283311
97.57	0.01	99.31	0.02	96.04	0.00	100.00	0.00	96.15	0.00	98.68	0.00	99.16	0.00	93.64	0.00	/workspace/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.2592590554

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.3810409968
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.2083105622
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.2025732317
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.1111025174
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.1716500297
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.857220539
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.2833577012
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.1802230635
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.4192248849
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.1044312855
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.992436994
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.925728037
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.2185183979
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.3029617235
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.3102960014
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.388375837
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.1756390559
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.1074106210
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.3858745245
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.249399263
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.3568231644
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.2033088504
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.4294875519
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.2654855080
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.2331254467
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.985627342
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.1538352862
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.2048200014
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.3111408747
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.2101514846
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.1915737057
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.2131365160
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.2349355312
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.3025947282
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.1943478148
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.4241202085
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.3414639583
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.4138603457
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.775365650
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.295387570
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.488379319
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.2647895146
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.1279655942
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.609245934
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.2532291125
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.3120602732
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.2356123087
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.3883168377
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.4256331514
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.3952950218
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.3321787960
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.2296631661
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.1132969734
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.1511920753
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.3670862531
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.3464476454
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.1783576853
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.578748307
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.2925038345
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.3386968250
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/workspace/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.3812013952
/workspace/coverage/default/40.sysrst_ctrl_edge_detect.152435665
/workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.1692325188
/workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.2429983606
/workspace/coverage/default/40.sysrst_ctrl_pin_access_test.4147910485
/workspace/coverage/default/40.sysrst_ctrl_pin_override_test.3568932029
/workspace/coverage/default/40.sysrst_ctrl_smoke.1677384319
/workspace/coverage/default/40.sysrst_ctrl_stress_all.431561175
/workspace/coverage/default/41.sysrst_ctrl_alert_test.1333551763
/workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.486171085
/workspace/coverage/default/41.sysrst_ctrl_combo_detect.667995962
/workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.4117550094
/workspace/coverage/default/41.sysrst_ctrl_edge_detect.2837955689
/workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.2609954732
/workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.3241733498
/workspace/coverage/default/41.sysrst_ctrl_pin_access_test.3402944166
/workspace/coverage/default/41.sysrst_ctrl_pin_override_test.2661833621
/workspace/coverage/default/41.sysrst_ctrl_smoke.168472269
/workspace/coverage/default/41.sysrst_ctrl_stress_all.2474041626
/workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.2785770073
/workspace/coverage/default/42.sysrst_ctrl_alert_test.3053848874
/workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.339091992
/workspace/coverage/default/42.sysrst_ctrl_combo_detect.864316692
/workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.686289342
/workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.4009597047
/workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.1841089885
/workspace/coverage/default/42.sysrst_ctrl_pin_access_test.3825484385
/workspace/coverage/default/42.sysrst_ctrl_pin_override_test.1783907625
/workspace/coverage/default/42.sysrst_ctrl_smoke.1080344379
/workspace/coverage/default/42.sysrst_ctrl_stress_all.1242000474
/workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.1422822537
/workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.1428175261
/workspace/coverage/default/43.sysrst_ctrl_alert_test.166794523
/workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.3620009435
/workspace/coverage/default/43.sysrst_ctrl_combo_detect.946067899
/workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.1766824701
/workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.67096376
/workspace/coverage/default/43.sysrst_ctrl_edge_detect.4069637651
/workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.3535104824
/workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.3262177408
/workspace/coverage/default/43.sysrst_ctrl_pin_access_test.874610487
/workspace/coverage/default/43.sysrst_ctrl_pin_override_test.3861854391
/workspace/coverage/default/43.sysrst_ctrl_smoke.2102426543
/workspace/coverage/default/43.sysrst_ctrl_stress_all.2003164663
/workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.2348275249
/workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.1211029234
/workspace/coverage/default/44.sysrst_ctrl_alert_test.384013027
/workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.1269634131
/workspace/coverage/default/44.sysrst_ctrl_combo_detect.3944930152
/workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.1921933317
/workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.3224567541
/workspace/coverage/default/44.sysrst_ctrl_edge_detect.3383493290
/workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.2600672458
/workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.2314170552
/workspace/coverage/default/44.sysrst_ctrl_pin_access_test.2841599107
/workspace/coverage/default/44.sysrst_ctrl_pin_override_test.1416685616
/workspace/coverage/default/44.sysrst_ctrl_smoke.2958597055
/workspace/coverage/default/44.sysrst_ctrl_stress_all.3963435085
/workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.739982968
/workspace/coverage/default/45.sysrst_ctrl_alert_test.2419695137
/workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.1865233386
/workspace/coverage/default/45.sysrst_ctrl_combo_detect.1115307214
/workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.345037920
/workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.2338540476
/workspace/coverage/default/45.sysrst_ctrl_edge_detect.3213037985
/workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.3896790246
/workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.394414717
/workspace/coverage/default/45.sysrst_ctrl_pin_access_test.1719633271
/workspace/coverage/default/45.sysrst_ctrl_pin_override_test.572738827
/workspace/coverage/default/45.sysrst_ctrl_smoke.530435531
/workspace/coverage/default/45.sysrst_ctrl_stress_all.2231273591
/workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.3201883672
/workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.4280110158
/workspace/coverage/default/46.sysrst_ctrl_alert_test.1259366594
/workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.506923586
/workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.2239754426
/workspace/coverage/default/46.sysrst_ctrl_edge_detect.803826606
/workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.2927134827
/workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.3968405136
/workspace/coverage/default/46.sysrst_ctrl_pin_access_test.1801894544
/workspace/coverage/default/46.sysrst_ctrl_pin_override_test.1067193650
/workspace/coverage/default/46.sysrst_ctrl_smoke.1192627035
/workspace/coverage/default/46.sysrst_ctrl_stress_all.3219548616
/workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.3831867452
/workspace/coverage/default/47.sysrst_ctrl_alert_test.252901772
/workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.897579258
/workspace/coverage/default/47.sysrst_ctrl_combo_detect.3732367338
/workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.2546180504
/workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.3227939609
/workspace/coverage/default/47.sysrst_ctrl_edge_detect.1929286062
/workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.3013470851
/workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.3849661575
/workspace/coverage/default/47.sysrst_ctrl_pin_access_test.657682515
/workspace/coverage/default/47.sysrst_ctrl_pin_override_test.4179679930
/workspace/coverage/default/47.sysrst_ctrl_smoke.3513239311
/workspace/coverage/default/47.sysrst_ctrl_stress_all.1864916225
/workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.4104484081
/workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.1000033697
/workspace/coverage/default/48.sysrst_ctrl_alert_test.2416066782
/workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.481742463
/workspace/coverage/default/48.sysrst_ctrl_combo_detect.380188489
/workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.2193402510
/workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.4059822162
/workspace/coverage/default/48.sysrst_ctrl_edge_detect.994927836
/workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.2357887110
/workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.455134219
/workspace/coverage/default/48.sysrst_ctrl_pin_access_test.3890930083
/workspace/coverage/default/48.sysrst_ctrl_pin_override_test.1427536092
/workspace/coverage/default/48.sysrst_ctrl_smoke.487654969
/workspace/coverage/default/48.sysrst_ctrl_stress_all.1901952056
/workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.95600380
/workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.2320825934
/workspace/coverage/default/49.sysrst_ctrl_alert_test.3979579753
/workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.1697743427
/workspace/coverage/default/49.sysrst_ctrl_combo_detect.1267003803
/workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.3990673561
/workspace/coverage/default/49.sysrst_ctrl_edge_detect.743758339
/workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.2688515177
/workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.1963380786
/workspace/coverage/default/49.sysrst_ctrl_pin_access_test.3435682112
/workspace/coverage/default/49.sysrst_ctrl_pin_override_test.2583564445
/workspace/coverage/default/49.sysrst_ctrl_smoke.2013940666
/workspace/coverage/default/49.sysrst_ctrl_stress_all.706405472
/workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.1569947319
/workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.3925865572
/workspace/coverage/default/5.sysrst_ctrl_alert_test.2896750876
/workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.558450173
/workspace/coverage/default/5.sysrst_ctrl_combo_detect.2845999518
/workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.2103381476
/workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.1420225344
/workspace/coverage/default/5.sysrst_ctrl_edge_detect.1635362038
/workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.3769419178
/workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.3225138770
/workspace/coverage/default/5.sysrst_ctrl_pin_access_test.196649608
/workspace/coverage/default/5.sysrst_ctrl_pin_override_test.1285433756
/workspace/coverage/default/5.sysrst_ctrl_smoke.1687055393
/workspace/coverage/default/5.sysrst_ctrl_stress_all.2170936159
/workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.1259327977
/workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.326725568
/workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.3004236559
/workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.1414293269
/workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.1592410542
/workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.992279456
/workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.177612273
/workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.3818150259
/workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.250955437
/workspace/coverage/default/6.sysrst_ctrl_alert_test.2255949949
/workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.3482597312
/workspace/coverage/default/6.sysrst_ctrl_combo_detect.4153621096
/workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.3183866033
/workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.3710150173
/workspace/coverage/default/6.sysrst_ctrl_edge_detect.2834082992
/workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.2759238224
/workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.3956897322
/workspace/coverage/default/6.sysrst_ctrl_pin_access_test.24023170
/workspace/coverage/default/6.sysrst_ctrl_pin_override_test.3715177957
/workspace/coverage/default/6.sysrst_ctrl_smoke.1122474810
/workspace/coverage/default/6.sysrst_ctrl_stress_all.3251248668
/workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.708312849
/workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.1466881197
/workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.98709530
/workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.1484588331
/workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.643761259
/workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.3774187411
/workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.2102581445
/workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.2862534780
/workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.1120284952
/workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.272114241
/workspace/coverage/default/7.sysrst_ctrl_alert_test.2065363745
/workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.3608594780
/workspace/coverage/default/7.sysrst_ctrl_combo_detect.3388745742
/workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.3163677221
/workspace/coverage/default/7.sysrst_ctrl_edge_detect.1790597174
/workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.1646094918
/workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.2970944309
/workspace/coverage/default/7.sysrst_ctrl_pin_access_test.2988022734
/workspace/coverage/default/7.sysrst_ctrl_pin_override_test.3716030115
/workspace/coverage/default/7.sysrst_ctrl_smoke.731891742
/workspace/coverage/default/7.sysrst_ctrl_stress_all.1718293294
/workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.3709196721
/workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.3905077976
/workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.533788058
/workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.1624667861
/workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.1766680536
/workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.3998350491
/workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.835385636
/workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.615476438
/workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.478249609
/workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.914379057
/workspace/coverage/default/8.sysrst_ctrl_alert_test.1689683189
/workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.3264901063
/workspace/coverage/default/8.sysrst_ctrl_combo_detect.4001826829
/workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.2723143122
/workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.3719505844
/workspace/coverage/default/8.sysrst_ctrl_edge_detect.1063262460
/workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.2554956817
/workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.2814689506
/workspace/coverage/default/8.sysrst_ctrl_pin_access_test.2200410384
/workspace/coverage/default/8.sysrst_ctrl_pin_override_test.2584332630
/workspace/coverage/default/8.sysrst_ctrl_smoke.3550042055
/workspace/coverage/default/8.sysrst_ctrl_stress_all.1423482388
/workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.472913724
/workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.1770532443
/workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.2857983942
/workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.1805034884
/workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.2506914233
/workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.2581335277
/workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.1734006263
/workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.3138503369
/workspace/coverage/default/9.sysrst_ctrl_alert_test.3677853927
/workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.2612387804
/workspace/coverage/default/9.sysrst_ctrl_combo_detect.2388222778
/workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.335550795
/workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.3808473488
/workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.4154390223
/workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.3051239563
/workspace/coverage/default/9.sysrst_ctrl_pin_access_test.3946525832
/workspace/coverage/default/9.sysrst_ctrl_pin_override_test.714909786
/workspace/coverage/default/9.sysrst_ctrl_smoke.17431479
/workspace/coverage/default/9.sysrst_ctrl_stress_all.3915424102
/workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.3813582624
/workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.2915819384
/workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.3266014737
/workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.2894024647
/workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.4041142220
/workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.3423758906
/workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.1601352508
/workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.4178749060
/workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.1311365822

Total test records in report: 907

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T4	/workspace/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.2559989250	Mar 03 02:26:02 PM PST 24	Mar 03 02:26:36 PM PST 24	29594717450 ps
T5	/workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3828422961	Mar 03 02:25:13 PM PST 24	Mar 03 02:25:17 PM PST 24	2304752738 ps
T6	/workspace/coverage/default/35.sysrst_ctrl_stress_all.1908694382	Mar 03 02:26:09 PM PST 24	Mar 03 02:26:34 PM PST 24	9884152105 ps
T39	/workspace/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.161629476	Mar 03 02:26:02 PM PST 24	Mar 03 02:26:05 PM PST 24	2621826196 ps
T40	/workspace/coverage/default/14.sysrst_ctrl_stress_all.3618209759	Mar 03 02:25:44 PM PST 24	Mar 03 02:26:19 PM PST 24	12027825322 ps
T41	/workspace/coverage/default/3.sysrst_ctrl_pin_override_test.250565823	Mar 03 02:25:12 PM PST 24	Mar 03 02:25:17 PM PST 24	2515368386 ps
T42	/workspace/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.2344233919	Mar 03 02:25:37 PM PST 24	Mar 03 02:26:18 PM PST 24	59574902362 ps
T43	/workspace/coverage/default/6.sysrst_ctrl_alert_test.2255949949	Mar 03 02:25:16 PM PST 24	Mar 03 02:25:23 PM PST 24	2012967159 ps
T1	/workspace/coverage/default/20.sysrst_ctrl_combo_detect.3006023201	Mar 03 02:25:48 PM PST 24	Mar 03 02:27:50 PM PST 24	88828911872 ps
T25	/workspace/coverage/default/14.sysrst_ctrl_combo_detect.3163458791	Mar 03 02:25:22 PM PST 24	Mar 03 02:26:11 PM PST 24	124337993822 ps
T26	/workspace/coverage/default/14.sysrst_ctrl_pin_access_test.2964636830	Mar 03 02:25:18 PM PST 24	Mar 03 02:25:22 PM PST 24	2203449167 ps
T27	/workspace/coverage/default/17.sysrst_ctrl_alert_test.4101722142	Mar 03 02:25:46 PM PST 24	Mar 03 02:25:47 PM PST 24	2059402461 ps
T2	/workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.177612273	Mar 03 02:26:58 PM PST 24	Mar 03 02:28:48 PM PST 24	38346630657 ps
T3	/workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.2320825934	Mar 03 02:26:49 PM PST 24	Mar 03 02:26:57 PM PST 24	5762870187 ps
T7	/workspace/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.979071835	Mar 03 02:25:48 PM PST 24	Mar 03 02:27:43 PM PST 24	162085023789 ps
T8	/workspace/coverage/default/49.sysrst_ctrl_edge_detect.743758339	Mar 03 02:27:01 PM PST 24	Mar 03 02:27:06 PM PST 24	2902944481 ps
T28	/workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.1484588331	Mar 03 02:26:58 PM PST 24	Mar 03 02:29:47 PM PST 24	59375342454 ps
T9	/workspace/coverage/default/12.sysrst_ctrl_ultra_low_pwr.3117226051	Mar 03 02:25:21 PM PST 24	Mar 03 02:25:29 PM PST 24	3428546645 ps
T10	/workspace/coverage/default/9.sysrst_ctrl_edge_detect.943475189	Mar 03 02:25:16 PM PST 24	Mar 03 02:25:19 PM PST 24	3192375915 ps
T29	/workspace/coverage/default/33.sysrst_ctrl_pin_override_test.2581210514	Mar 03 02:26:12 PM PST 24	Mar 03 02:26:14 PM PST 24	2538633385 ps
T11	/workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.835191193	Mar 03 02:26:50 PM PST 24	Mar 03 02:28:10 PM PST 24	233086486260 ps
T30	/workspace/coverage/default/19.sysrst_ctrl_pin_override_test.985395896	Mar 03 02:25:48 PM PST 24	Mar 03 02:25:51 PM PST 24	2534029079 ps
T31	/workspace/coverage/default/0.sysrst_ctrl_alert_test.57151811	Mar 03 02:25:14 PM PST 24	Mar 03 02:25:22 PM PST 24	2036710162 ps
T32	/workspace/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.2908726362	Mar 03 02:25:52 PM PST 24	Mar 03 02:26:09 PM PST 24	25613909082 ps
T33	/workspace/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.2300292088	Mar 03 02:25:07 PM PST 24	Mar 03 02:25:10 PM PST 24	4388859825 ps
T75	/workspace/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.3909322196	Mar 03 02:26:08 PM PST 24	Mar 03 02:27:31 PM PST 24	31083750637 ps
T12	/workspace/coverage/default/25.sysrst_ctrl_edge_detect.61666484	Mar 03 02:26:09 PM PST 24	Mar 03 02:26:13 PM PST 24	3255149281 ps
T13	/workspace/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.135146104	Mar 03 02:25:49 PM PST 24	Mar 03 02:28:19 PM PST 24	117696477059 ps
T50	/workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.897579258	Mar 03 02:26:54 PM PST 24	Mar 03 02:30:07 PM PST 24	295978424343 ps
T14	/workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.1259327977	Mar 03 02:25:16 PM PST 24	Mar 03 02:26:04 PM PST 24	17728954361 ps
T51	/workspace/coverage/default/3.sysrst_ctrl_auto_blk_key_output.2629975135	Mar 03 02:25:15 PM PST 24	Mar 03 02:27:37 PM PST 24	248682570575 ps
T48	/workspace/coverage/default/2.sysrst_ctrl_in_out_inverted.3069619454	Mar 03 02:25:08 PM PST 24	Mar 03 02:25:16 PM PST 24	2448111753 ps
T15	/workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.4142300186	Mar 03 02:25:19 PM PST 24	Mar 03 02:26:10 PM PST 24	73395363630 ps
T16	/workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.3925865572	Mar 03 02:27:00 PM PST 24	Mar 03 02:27:16 PM PST 24	336416263253 ps
T62	/workspace/coverage/default/22.sysrst_ctrl_alert_test.3614362482	Mar 03 02:25:53 PM PST 24	Mar 03 02:25:58 PM PST 24	2010622805 ps
T17	/workspace/coverage/default/0.sysrst_ctrl_edge_detect.755358438	Mar 03 02:25:11 PM PST 24	Mar 03 02:25:17 PM PST 24	4205637684 ps
T63	/workspace/coverage/default/39.sysrst_ctrl_alert_test.3967351732	Mar 03 02:26:13 PM PST 24	Mar 03 02:26:15 PM PST 24	2040986489 ps
T64	/workspace/coverage/default/46.sysrst_ctrl_pin_override_test.1067193650	Mar 03 02:26:44 PM PST 24	Mar 03 02:26:48 PM PST 24	2514871935 ps
T18	/workspace/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.3399477888	Mar 03 02:25:20 PM PST 24	Mar 03 02:25:50 PM PST 24	56477187008 ps
T73	/workspace/coverage/default/21.sysrst_ctrl_smoke.3902361817	Mar 03 02:25:49 PM PST 24	Mar 03 02:25:51 PM PST 24	2126666676 ps
T74	/workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.2609954732	Mar 03 02:26:36 PM PST 24	Mar 03 02:26:40 PM PST 24	2617361153 ps
T49	/workspace/coverage/default/38.sysrst_ctrl_in_out_inverted.3322902918	Mar 03 02:26:04 PM PST 24	Mar 03 02:26:11 PM PST 24	2472262723 ps
T93	/workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.3423758906	Mar 03 02:26:57 PM PST 24	Mar 03 02:27:17 PM PST 24	30349331779 ps
T82	/workspace/coverage/default/46.sysrst_ctrl_combo_detect.1435219930	Mar 03 02:26:49 PM PST 24	Mar 03 02:27:15 PM PST 24	69700925349 ps
T105	/workspace/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.927499262	Mar 03 02:26:04 PM PST 24	Mar 03 02:26:13 PM PST 24	3118694753 ps
T106	/workspace/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.3960224943	Mar 03 02:26:06 PM PST 24	Mar 03 02:26:10 PM PST 24	4330065852 ps
T66	/workspace/coverage/default/29.sysrst_ctrl_in_out_inverted.1815855923	Mar 03 02:26:06 PM PST 24	Mar 03 02:26:10 PM PST 24	2474873287 ps
T19	/workspace/coverage/default/39.sysrst_ctrl_stress_all.3067500448	Mar 03 02:26:14 PM PST 24	Mar 03 02:27:11 PM PST 24	83802676734 ps
T107	/workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.3163677221	Mar 03 02:25:13 PM PST 24	Mar 03 02:25:18 PM PST 24	3471660475 ps
T108	/workspace/coverage/default/36.sysrst_ctrl_pin_override_test.4174520666	Mar 03 02:26:12 PM PST 24	Mar 03 02:26:15 PM PST 24	2520716373 ps
T109	/workspace/coverage/default/26.sysrst_ctrl_smoke.397196291	Mar 03 02:26:02 PM PST 24	Mar 03 02:26:05 PM PST 24	2116138038 ps
T67	/workspace/coverage/default/23.sysrst_ctrl_in_out_inverted.1997490224	Mar 03 02:26:05 PM PST 24	Mar 03 02:26:07 PM PST 24	2482120487 ps
T68	/workspace/coverage/default/28.sysrst_ctrl_in_out_inverted.278485113	Mar 03 02:26:08 PM PST 24	Mar 03 02:26:10 PM PST 24	2495105045 ps
T131	/workspace/coverage/default/10.sysrst_ctrl_alert_test.525988746	Mar 03 02:25:13 PM PST 24	Mar 03 02:25:17 PM PST 24	2021752452 ps
T110	/workspace/coverage/default/45.sysrst_ctrl_combo_detect.1115307214	Mar 03 02:26:47 PM PST 24	Mar 03 02:28:50 PM PST 24	88586247297 ps
T69	/workspace/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.3755169830	Mar 03 02:25:22 PM PST 24	Mar 03 02:25:56 PM PST 24	12079629689 ps
T20	/workspace/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.4158202744	Mar 03 02:26:05 PM PST 24	Mar 03 02:27:14 PM PST 24	106495887287 ps
T149	/workspace/coverage/default/11.sysrst_ctrl_combo_detect.263270879	Mar 03 02:25:17 PM PST 24	Mar 03 02:29:26 PM PST 24	180678287931 ps
T52	/workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.1662007599	Mar 03 02:26:49 PM PST 24	Mar 03 02:27:37 PM PST 24	144870395843 ps
T150	/workspace/coverage/default/5.sysrst_ctrl_pin_override_test.1285433756	Mar 03 02:25:18 PM PST 24	Mar 03 02:25:26 PM PST 24	2513017858 ps
T21	/workspace/coverage/default/11.sysrst_ctrl_edge_detect.3902078871	Mar 03 02:25:19 PM PST 24	Mar 03 02:25:26 PM PST 24	3258577632 ps
T83	/workspace/coverage/default/31.sysrst_ctrl_combo_detect.492293540	Mar 03 02:26:07 PM PST 24	Mar 03 02:27:19 PM PST 24	135195497227 ps
T34	/workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.2082299948	Mar 03 02:26:20 PM PST 24	Mar 03 02:28:24 PM PST 24	48099984494 ps
T70	/workspace/coverage/default/31.sysrst_ctrl_in_out_inverted.3810430158	Mar 03 02:26:02 PM PST 24	Mar 03 02:26:04 PM PST 24	2462135185 ps
T35	/workspace/coverage/default/1.sysrst_ctrl_ultra_low_pwr.2957492186	Mar 03 02:25:17 PM PST 24	Mar 03 02:25:20 PM PST 24	7308041025 ps
T120	/workspace/coverage/default/20.sysrst_ctrl_pin_access_test.3284136144	Mar 03 02:25:41 PM PST 24	Mar 03 02:25:43 PM PST 24	2217458782 ps
T121	/workspace/coverage/default/7.sysrst_ctrl_pin_override_test.3716030115	Mar 03 02:25:15 PM PST 24	Mar 03 02:25:18 PM PST 24	2522538293 ps
T122	/workspace/coverage/default/8.sysrst_ctrl_smoke.3550042055	Mar 03 02:25:15 PM PST 24	Mar 03 02:25:21 PM PST 24	2108608244 ps
T123	/workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.2357887110	Mar 03 02:26:51 PM PST 24	Mar 03 02:26:54 PM PST 24	2626296622 ps
T124	/workspace/coverage/default/30.sysrst_ctrl_pin_access_test.197064066	Mar 03 02:26:13 PM PST 24	Mar 03 02:26:14 PM PST 24	2320204352 ps
T125	/workspace/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.4075470847	Mar 03 02:26:02 PM PST 24	Mar 03 02:28:38 PM PST 24	62469197131 ps
T126	/workspace/coverage/default/24.sysrst_ctrl_smoke.2059479038	Mar 03 02:25:55 PM PST 24	Mar 03 02:26:01 PM PST 24	2112950163 ps
T305	/workspace/coverage/default/0.sysrst_ctrl_stress_all.1852615979	Mar 03 02:25:14 PM PST 24	Mar 03 02:25:19 PM PST 24	6690753844 ps
T71	/workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.3849661575	Mar 03 02:26:41 PM PST 24	Mar 03 02:26:48 PM PST 24	2475945961 ps
T72	/workspace/coverage/default/19.sysrst_ctrl_stress_all.730349831	Mar 03 02:25:49 PM PST 24	Mar 03 02:25:55 PM PST 24	8685695109 ps
T58	/workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.3482597312	Mar 03 02:25:14 PM PST 24	Mar 03 02:25:33 PM PST 24	26293290440 ps
T256	/workspace/coverage/default/3.sysrst_ctrl_combo_detect.1747573923	Mar 03 02:25:12 PM PST 24	Mar 03 02:31:37 PM PST 24	137814165816 ps
T282	/workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.2759238224	Mar 03 02:25:18 PM PST 24	Mar 03 02:25:26 PM PST 24	2611935578 ps
T283	/workspace/coverage/default/1.sysrst_ctrl_stress_all.3732401876	Mar 03 02:25:13 PM PST 24	Mar 03 02:25:32 PM PST 24	7123904563 ps
T22	/workspace/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.3581207089	Mar 03 02:25:47 PM PST 24	Mar 03 02:27:26 PM PST 24	44543746888 ps
T212	/workspace/coverage/default/3.sysrst_ctrl_pin_access_test.4160174413	Mar 03 02:25:13 PM PST 24	Mar 03 02:25:14 PM PST 24	2146548777 ps
T65	/workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.4280110158	Mar 03 02:26:43 PM PST 24	Mar 03 02:26:45 PM PST 24	6950730012 ps
T213	/workspace/coverage/default/1.sysrst_ctrl_sec_cm.4050396523	Mar 03 02:25:14 PM PST 24	Mar 03 02:25:33 PM PST 24	42173094769 ps
T214	/workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.3183866033	Mar 03 02:25:20 PM PST 24	Mar 03 02:26:34 PM PST 24	71056751094 ps
T215	/workspace/coverage/default/27.sysrst_ctrl_pin_override_test.568908897	Mar 03 02:26:04 PM PST 24	Mar 03 02:26:09 PM PST 24	2513409009 ps
T216	/workspace/coverage/default/44.sysrst_ctrl_pin_access_test.2841599107	Mar 03 02:26:48 PM PST 24	Mar 03 02:26:50 PM PST 24	2119975461 ps
T217	/workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.2894024647	Mar 03 02:26:57 PM PST 24	Mar 03 02:27:35 PM PST 24	55368942315 ps
T218	/workspace/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.1926787389	Mar 03 02:25:58 PM PST 24	Mar 03 02:26:22 PM PST 24	38056337289 ps
T36	/workspace/coverage/default/14.sysrst_ctrl_ultra_low_pwr.1961308305	Mar 03 02:25:39 PM PST 24	Mar 03 02:25:43 PM PST 24	3160807707 ps
T238	/workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3891213104	Mar 03 02:25:18 PM PST 24	Mar 03 02:25:27 PM PST 24	2527907907 ps
T275	/workspace/coverage/default/14.sysrst_ctrl_pin_override_test.437225311	Mar 03 02:25:20 PM PST 24	Mar 03 02:25:23 PM PST 24	2536499581 ps
T276	/workspace/coverage/default/17.sysrst_ctrl_pin_access_test.3473236182	Mar 03 02:25:51 PM PST 24	Mar 03 02:25:57 PM PST 24	2131716454 ps
T37	/workspace/coverage/default/23.sysrst_ctrl_ultra_low_pwr.2421749852	Mar 03 02:26:10 PM PST 24	Mar 03 02:26:17 PM PST 24	4296341776 ps
T395	/workspace/coverage/default/41.sysrst_ctrl_pin_access_test.3402944166	Mar 03 02:26:25 PM PST 24	Mar 03 02:26:27 PM PST 24	2189163887 ps
T396	/workspace/coverage/default/0.sysrst_ctrl_in_out_inverted.1358608997	Mar 03 02:25:09 PM PST 24	Mar 03 02:25:17 PM PST 24	2462894956 ps
T397	/workspace/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.3021088005	Mar 03 02:25:50 PM PST 24	Mar 03 02:25:54 PM PST 24	2612226750 ps
T398	/workspace/coverage/default/25.sysrst_ctrl_pin_access_test.2076972598	Mar 03 02:26:06 PM PST 24	Mar 03 02:26:11 PM PST 24	2023558798 ps
T86	/workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.543906864	Mar 03 02:26:56 PM PST 24	Mar 03 02:30:14 PM PST 24	144223639235 ps
T306	/workspace/coverage/default/10.sysrst_ctrl_ultra_low_pwr.3078516318	Mar 03 02:25:14 PM PST 24	Mar 03 02:26:42 PM PST 24	898553507070 ps
T399	/workspace/coverage/default/25.sysrst_ctrl_smoke.2331229378	Mar 03 02:26:11 PM PST 24	Mar 03 02:26:12 PM PST 24	2152433211 ps
T400	/workspace/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.2971169314	Mar 03 02:25:16 PM PST 24	Mar 03 02:25:20 PM PST 24	3425920493 ps
T59	/workspace/coverage/default/25.sysrst_ctrl_auto_blk_key_output.1348039198	Mar 03 02:26:04 PM PST 24	Mar 03 02:26:06 PM PST 24	3434157266 ps
T60	/workspace/coverage/default/20.sysrst_ctrl_auto_blk_key_output.3497013152	Mar 03 02:25:48 PM PST 24	Mar 03 02:25:58 PM PST 24	3680419834 ps
T236	/workspace/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.1213869400	Mar 03 02:25:16 PM PST 24	Mar 03 02:26:33 PM PST 24	27580912565 ps
T300	/workspace/coverage/default/6.sysrst_ctrl_pin_override_test.3715177957	Mar 03 02:25:13 PM PST 24	Mar 03 02:25:15 PM PST 24	2604793163 ps
T401	/workspace/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.3456424788	Mar 03 02:26:06 PM PST 24	Mar 03 02:26:11 PM PST 24	2612775382 ps
T294	/workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.3241733498	Mar 03 02:26:29 PM PST 24	Mar 03 02:26:38 PM PST 24	2455165733 ps
T301	/workspace/coverage/default/31.sysrst_ctrl_pin_override_test.3655067928	Mar 03 02:26:03 PM PST 24	Mar 03 02:26:11 PM PST 24	2511590445 ps
T250	/workspace/coverage/default/32.sysrst_ctrl_combo_detect.160293137	Mar 03 02:26:08 PM PST 24	Mar 03 02:26:29 PM PST 24	40982988316 ps
T295	/workspace/coverage/default/25.sysrst_ctrl_in_out_inverted.2831337971	Mar 03 02:26:08 PM PST 24	Mar 03 02:26:16 PM PST 24	2445813922 ps
T296	/workspace/coverage/default/20.sysrst_ctrl_in_out_inverted.894707619	Mar 03 02:25:38 PM PST 24	Mar 03 02:25:40 PM PST 24	2483007968 ps
T61	/workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.1865233386	Mar 03 02:26:48 PM PST 24	Mar 03 02:26:53 PM PST 24	3189371812 ps
T92	/workspace/coverage/default/14.sysrst_ctrl_auto_blk_key_output.3157452364	Mar 03 02:25:20 PM PST 24	Mar 03 02:25:26 PM PST 24	3056254058 ps
T402	/workspace/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.742509027	Mar 03 02:25:09 PM PST 24	Mar 03 02:25:11 PM PST 24	2908578231 ps
T403	/workspace/coverage/default/36.sysrst_ctrl_smoke.1062282438	Mar 03 02:26:05 PM PST 24	Mar 03 02:26:11 PM PST 24	2114519642 ps
T382	/workspace/coverage/default/18.sysrst_ctrl_stress_all.3589675458	Mar 03 02:25:31 PM PST 24	Mar 03 02:25:45 PM PST 24	9146998695 ps
T404	/workspace/coverage/default/21.sysrst_ctrl_pin_override_test.3145737911	Mar 03 02:25:53 PM PST 24	Mar 03 02:26:00 PM PST 24	2510893228 ps
T405	/workspace/coverage/default/12.sysrst_ctrl_pin_override_test.83603734	Mar 03 02:25:21 PM PST 24	Mar 03 02:25:29 PM PST 24	2511490662 ps
T406	/workspace/coverage/default/27.sysrst_ctrl_in_out_inverted.4198083008	Mar 03 02:26:09 PM PST 24	Mar 03 02:26:11 PM PST 24	2488826663 ps
T407	/workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.2927134827	Mar 03 02:26:58 PM PST 24	Mar 03 02:27:03 PM PST 24	2646540596 ps
T239	/workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.1004663007	Mar 03 02:26:24 PM PST 24	Mar 03 02:32:04 PM PST 24	127812465899 ps
T297	/workspace/coverage/default/26.sysrst_ctrl_in_out_inverted.1982248221	Mar 03 02:26:08 PM PST 24	Mar 03 02:26:11 PM PST 24	2463493132 ps
T408	/workspace/coverage/default/24.sysrst_ctrl_auto_blk_key_output.4276472833	Mar 03 02:25:49 PM PST 24	Mar 03 02:25:52 PM PST 24	3654421861 ps
T237	/workspace/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.3754242426	Mar 03 02:26:00 PM PST 24	Mar 03 02:26:36 PM PST 24	26587880945 ps
T409	/workspace/coverage/default/10.sysrst_ctrl_pin_override_test.3654762821	Mar 03 02:25:18 PM PST 24	Mar 03 02:25:21 PM PST 24	2534737421 ps
T307	/workspace/coverage/default/34.sysrst_ctrl_ultra_low_pwr.388808126	Mar 03 02:26:05 PM PST 24	Mar 03 02:26:11 PM PST 24	7618474519 ps
T23	/workspace/coverage/default/20.sysrst_ctrl_stress_all.840163906	Mar 03 02:25:49 PM PST 24	Mar 03 02:28:32 PM PST 24	88604545110 ps
T24	/workspace/coverage/default/7.sysrst_ctrl_edge_detect.1790597174	Mar 03 02:25:13 PM PST 24	Mar 03 02:25:21 PM PST 24	2731525782 ps
T410	/workspace/coverage/default/36.sysrst_ctrl_pin_access_test.3568341497	Mar 03 02:26:09 PM PST 24	Mar 03 02:26:14 PM PST 24	2071824871 ps
T411	/workspace/coverage/default/39.sysrst_ctrl_smoke.1812230786	Mar 03 02:26:03 PM PST 24	Mar 03 02:26:06 PM PST 24	2116875354 ps
T111	/workspace/coverage/default/44.sysrst_ctrl_stress_all.3963435085	Mar 03 02:26:37 PM PST 24	Mar 03 02:26:47 PM PST 24	13283207955 ps
T412	/workspace/coverage/default/16.sysrst_ctrl_pin_access_test.19130491	Mar 03 02:25:37 PM PST 24	Mar 03 02:25:44 PM PST 24	2209781390 ps
T413	/workspace/coverage/default/29.sysrst_ctrl_smoke.3670921397	Mar 03 02:26:07 PM PST 24	Mar 03 02:26:09 PM PST 24	2144584494 ps
T240	/workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.2862534780	Mar 03 02:27:03 PM PST 24	Mar 03 02:31:20 PM PST 24	89366897165 ps
T414	/workspace/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.2785516382	Mar 03 02:26:07 PM PST 24	Mar 03 02:26:11 PM PST 24	2621768998 ps
T38	/workspace/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.4170580247	Mar 03 02:25:14 PM PST 24	Mar 03 02:25:53 PM PST 24	32321874270 ps
T53	/workspace/coverage/default/19.sysrst_ctrl_edge_detect.527084784	Mar 03 02:25:52 PM PST 24	Mar 03 02:25:59 PM PST 24	5653652725 ps
T224	/workspace/coverage/default/14.sysrst_ctrl_alert_test.659046706	Mar 03 02:25:47 PM PST 24	Mar 03 02:25:51 PM PST 24	2022876098 ps
T225	/workspace/coverage/default/9.sysrst_ctrl_combo_detect.2388222778	Mar 03 02:25:17 PM PST 24	Mar 03 02:25:41 PM PST 24	45963500902 ps
T226	/workspace/coverage/default/16.sysrst_ctrl_alert_test.3124640274	Mar 03 02:25:43 PM PST 24	Mar 03 02:25:47 PM PST 24	2015937234 ps
T227	/workspace/coverage/default/37.sysrst_ctrl_pin_override_test.571745917	Mar 03 02:26:39 PM PST 24	Mar 03 02:26:42 PM PST 24	2523985140 ps
T228	/workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.2609480783	Mar 03 02:27:02 PM PST 24	Mar 03 02:27:58 PM PST 24	77032074420 ps
T78	/workspace/coverage/default/23.sysrst_ctrl_combo_detect.2396330652	Mar 03 02:26:06 PM PST 24	Mar 03 02:30:25 PM PST 24	99631024944 ps
T229	/workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.307320069	Mar 03 02:25:20 PM PST 24	Mar 03 02:31:46 PM PST 24	160799357266 ps
T230	/workspace/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.3640987220	Mar 03 02:25:55 PM PST 24	Mar 03 02:25:58 PM PST 24	2626874122 ps
T231	/workspace/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.1824128904	Mar 03 02:26:07 PM PST 24	Mar 03 02:26:11 PM PST 24	4478887673 ps
T415	/workspace/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.3661023617	Mar 03 02:26:05 PM PST 24	Mar 03 02:26:07 PM PST 24	2629556761 ps
T416	/workspace/coverage/default/13.sysrst_ctrl_pin_access_test.3359256605	Mar 03 02:25:51 PM PST 24	Mar 03 02:25:52 PM PST 24	2315072776 ps
T417	/workspace/coverage/default/23.sysrst_ctrl_auto_blk_key_output.920577	Mar 03 02:26:01 PM PST 24	Mar 03 02:26:04 PM PST 24	3057207976 ps
T418	/workspace/coverage/default/4.sysrst_ctrl_pin_access_test.981188313	Mar 03 02:25:10 PM PST 24	Mar 03 02:25:16 PM PST 24	2135058736 ps
T243	/workspace/coverage/default/21.sysrst_ctrl_combo_detect.2865358624	Mar 03 02:26:09 PM PST 24	Mar 03 02:27:38 PM PST 24	159425754685 ps
T419	/workspace/coverage/default/41.sysrst_ctrl_alert_test.1333551763	Mar 03 02:26:21 PM PST 24	Mar 03 02:26:23 PM PST 24	2031780682 ps
T79	/workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.3266014737	Mar 03 02:27:01 PM PST 24	Mar 03 02:27:25 PM PST 24	109459219204 ps
T420	/workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.3808473488	Mar 03 02:25:15 PM PST 24	Mar 03 02:25:25 PM PST 24	3601068274 ps
T368	/workspace/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.31767534	Mar 03 02:25:12 PM PST 24	Mar 03 02:25:55 PM PST 24	59181485600 ps
T372	/workspace/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.2592590554	Mar 03 02:25:47 PM PST 24	Mar 03 02:26:10 PM PST 24	117338687015 ps
T421	/workspace/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.1912451557	Mar 03 02:26:12 PM PST 24	Mar 03 02:26:16 PM PST 24	2622479459 ps
T249	/workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.1734006263	Mar 03 02:26:51 PM PST 24	Mar 03 02:27:11 PM PST 24	36051736111 ps
T422	/workspace/coverage/default/45.sysrst_ctrl_smoke.530435531	Mar 03 02:26:35 PM PST 24	Mar 03 02:26:38 PM PST 24	2115251168 ps
T423	/workspace/coverage/default/27.sysrst_ctrl_pin_access_test.3763281841	Mar 03 02:26:06 PM PST 24	Mar 03 02:26:07 PM PST 24	2112839962 ps
T277	/workspace/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.4074733503	Mar 03 02:26:18 PM PST 24	Mar 03 02:27:00 PM PST 24	15918389275 ps
T424	/workspace/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.3984781869	Mar 03 02:26:01 PM PST 24	Mar 03 02:26:05 PM PST 24	3816862186 ps
T425	/workspace/coverage/default/13.sysrst_ctrl_pin_override_test.294291347	Mar 03 02:25:25 PM PST 24	Mar 03 02:25:33 PM PST 24	2511601248 ps
T389	/workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.2193402510	Mar 03 02:26:44 PM PST 24	Mar 03 02:27:47 PM PST 24	90623563371 ps
T426	/workspace/coverage/default/20.sysrst_ctrl_pin_override_test.552684657	Mar 03 02:25:50 PM PST 24	Mar 03 02:25:53 PM PST 24	2533546572 ps
T427	/workspace/coverage/default/15.sysrst_ctrl_pin_access_test.4142857832	Mar 03 02:25:50 PM PST 24	Mar 03 02:25:56 PM PST 24	2170573858 ps
T428	/workspace/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.1949650173	Mar 03 02:25:45 PM PST 24	Mar 03 02:25:59 PM PST 24	4983495562 ps
T429	/workspace/coverage/default/22.sysrst_ctrl_in_out_inverted.1141655973	Mar 03 02:25:50 PM PST 24	Mar 03 02:25:57 PM PST 24	2448408924 ps
T430	/workspace/coverage/default/38.sysrst_ctrl_stress_all.3531683066	Mar 03 02:26:10 PM PST 24	Mar 03 02:26:15 PM PST 24	6778102955 ps
T56	/workspace/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.1986417678	Mar 03 02:26:06 PM PST 24	Mar 03 02:26:38 PM PST 24	108845706340 ps
T290	/workspace/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.1968758	Mar 03 02:25:15 PM PST 24	Mar 03 02:25:23 PM PST 24	3428641300 ps
T431	/workspace/coverage/default/43.sysrst_ctrl_pin_override_test.3861854391	Mar 03 02:26:22 PM PST 24	Mar 03 02:26:29 PM PST 24	2511743050 ps
T432	/workspace/coverage/default/10.sysrst_ctrl_smoke.354759855	Mar 03 02:25:15 PM PST 24	Mar 03 02:25:22 PM PST 24	2111974986 ps
T433	/workspace/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.118783531	Mar 03 02:26:10 PM PST 24	Mar 03 02:26:12 PM PST 24	3859317846 ps
T380	/workspace/coverage/default/7.sysrst_ctrl_combo_detect.3388745742	Mar 03 02:25:15 PM PST 24	Mar 03 02:26:18 PM PST 24	87769975911 ps
T434	/workspace/coverage/default/12.sysrst_ctrl_auto_blk_key_output.3369436376	Mar 03 02:25:30 PM PST 24	Mar 03 02:25:36 PM PST 24	4006142077 ps
T354	/workspace/coverage/default/22.sysrst_ctrl_combo_detect.650472965	Mar 03 02:25:50 PM PST 24	Mar 03 02:31:30 PM PST 24	124148062543 ps
T351	/workspace/coverage/default/44.sysrst_ctrl_combo_detect.3944930152	Mar 03 02:26:45 PM PST 24	Mar 03 02:29:57 PM PST 24	146371427349 ps
T435	/workspace/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.3361009933	Mar 03 02:25:15 PM PST 24	Mar 03 02:25:26 PM PST 24	4319147023 ps
T54	/workspace/coverage/default/29.sysrst_ctrl_edge_detect.4179911198	Mar 03 02:26:03 PM PST 24	Mar 03 02:26:10 PM PST 24	2836062215 ps
T436	/workspace/coverage/default/39.sysrst_ctrl_auto_blk_key_output.748223004	Mar 03 02:26:06 PM PST 24	Mar 03 02:26:09 PM PST 24	3656967324 ps
T437	/workspace/coverage/default/36.sysrst_ctrl_alert_test.2802320318	Mar 03 02:26:14 PM PST 24	Mar 03 02:26:16 PM PST 24	2027082336 ps
T438	/workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.2688515177	Mar 03 02:26:59 PM PST 24	Mar 03 02:27:04 PM PST 24	2629352271 ps
T439	/workspace/coverage/default/39.sysrst_ctrl_pin_access_test.4151164215	Mar 03 02:26:35 PM PST 24	Mar 03 02:26:37 PM PST 24	2042519936 ps
T440	/workspace/coverage/default/38.sysrst_ctrl_alert_test.1424004525	Mar 03 02:26:35 PM PST 24	Mar 03 02:26:42 PM PST 24	2010677808 ps
T441	/workspace/coverage/default/1.sysrst_ctrl_smoke.1835119830	Mar 03 02:25:12 PM PST 24	Mar 03 02:25:15 PM PST 24	2115031451 ps
T442	/workspace/coverage/default/49.sysrst_ctrl_smoke.2013940666	Mar 03 02:27:01 PM PST 24	Mar 03 02:27:05 PM PST 24	2132364853 ps
T298	/workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.2814689506	Mar 03 02:25:19 PM PST 24	Mar 03 02:25:27 PM PST 24	2472067966 ps
T352	/workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.880243657	Mar 03 02:26:49 PM PST 24	Mar 03 02:28:13 PM PST 24	133764822356 ps
T241	/workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.2506914233	Mar 03 02:26:54 PM PST 24	Mar 03 02:27:57 PM PST 24	26080832997 ps
T253	/workspace/coverage/default/42.sysrst_ctrl_combo_detect.864316692	Mar 03 02:26:23 PM PST 24	Mar 03 02:29:22 PM PST 24	68057528998 ps
T360	/workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.3138503369	Mar 03 02:26:56 PM PST 24	Mar 03 02:27:56 PM PST 24	186577682497 ps
T369	/workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.1770532443	Mar 03 02:26:48 PM PST 24	Mar 03 02:29:19 PM PST 24	121294908755 ps
T284	/workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.3905077976	Mar 03 02:26:58 PM PST 24	Mar 03 02:31:44 PM PST 24	110320207340 ps
T242	/workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.3818150259	Mar 03 02:26:57 PM PST 24	Mar 03 02:28:11 PM PST 24	25581330255 ps
T443	/workspace/coverage/default/39.sysrst_ctrl_pin_override_test.3860776135	Mar 03 02:26:08 PM PST 24	Mar 03 02:26:11 PM PST 24	2535944368 ps
T444	/workspace/coverage/default/21.sysrst_ctrl_auto_blk_key_output.2081307337	Mar 03 02:25:58 PM PST 24	Mar 03 02:26:07 PM PST 24	3167122623 ps
T445	/workspace/coverage/default/33.sysrst_ctrl_auto_blk_key_output.2191038280	Mar 03 02:26:12 PM PST 24	Mar 03 02:26:14 PM PST 24	3091330700 ps
T446	/workspace/coverage/default/48.sysrst_ctrl_smoke.487654969	Mar 03 02:26:58 PM PST 24	Mar 03 02:27:03 PM PST 24	2116620185 ps
T447	/workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.2915819384	Mar 03 02:26:58 PM PST 24	Mar 03 02:27:20 PM PST 24	26103953618 ps
T448	/workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.3990673561	Mar 03 02:26:51 PM PST 24	Mar 03 02:27:00 PM PST 24	3477683391 ps
T359	/workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.256284075	Mar 03 02:26:57 PM PST 24	Mar 03 02:27:34 PM PST 24	52625604989 ps
T285	/workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.1921933317	Mar 03 02:26:45 PM PST 24	Mar 03 02:29:06 PM PST 24	108883995659 ps
T449	/workspace/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.3155834539	Mar 03 02:26:04 PM PST 24	Mar 03 02:26:06 PM PST 24	2688651722 ps
T450	/workspace/coverage/default/15.sysrst_ctrl_smoke.3218228666	Mar 03 02:25:25 PM PST 24	Mar 03 02:25:33 PM PST 24	2112094800 ps
T94	/workspace/coverage/default/37.sysrst_ctrl_combo_detect.2272392318	Mar 03 02:26:05 PM PST 24	Mar 03 02:33:32 PM PST 24	170551871798 ps
T451	/workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.3807414212	Mar 03 02:26:10 PM PST 24	Mar 03 02:26:21 PM PST 24	3499917884 ps
T452	/workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.2554956817	Mar 03 02:25:16 PM PST 24	Mar 03 02:25:19 PM PST 24	2643378150 ps
T453	/workspace/coverage/default/47.sysrst_ctrl_smoke.3513239311	Mar 03 02:26:47 PM PST 24	Mar 03 02:26:49 PM PST 24	2128998963 ps
T454	/workspace/coverage/default/34.sysrst_ctrl_in_out_inverted.3593463120	Mar 03 02:26:12 PM PST 24	Mar 03 02:26:19 PM PST 24	2461914264 ps
T455	/workspace/coverage/default/18.sysrst_ctrl_pin_access_test.2229564631	Mar 03 02:25:40 PM PST 24	Mar 03 02:25:47 PM PST 24	2208021266 ps
T112	/workspace/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.419764920	Mar 03 02:26:07 PM PST 24	Mar 03 02:27:19 PM PST 24	51969935787 ps
T315	/workspace/coverage/default/2.sysrst_ctrl_pin_access_test.360278946	Mar 03 02:25:14 PM PST 24	Mar 03 02:25:21 PM PST 24	2103035516 ps
T57	/workspace/coverage/default/15.sysrst_ctrl_edge_detect.2202761835	Mar 03 02:25:30 PM PST 24	Mar 03 02:25:40 PM PST 24	3485299291 ps
T316	/workspace/coverage/default/14.sysrst_ctrl_smoke.484834729	Mar 03 02:25:17 PM PST 24	Mar 03 02:25:24 PM PST 24	2112601697 ps
T299	/workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.3956897322	Mar 03 02:25:18 PM PST 24	Mar 03 02:25:23 PM PST 24	2475832574 ps
T91	/workspace/coverage/default/21.sysrst_ctrl_ultra_low_pwr.3577205066	Mar 03 02:25:49 PM PST 24	Mar 03 02:26:09 PM PST 24	339946697708 ps
T317	/workspace/coverage/default/49.sysrst_ctrl_pin_access_test.3435682112	Mar 03 02:26:54 PM PST 24	Mar 03 02:26:58 PM PST 24	2178505260 ps
T318	/workspace/coverage/default/25.sysrst_ctrl_ultra_low_pwr.3281028788	Mar 03 02:26:01 PM PST 24	Mar 03 02:26:08 PM PST 24	5094336772 ps
T286	/workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.2857983942	Mar 03 02:27:01 PM PST 24	Mar 03 02:32:37 PM PST 24	137441267853 ps
T319	/workspace/coverage/default/43.sysrst_ctrl_pin_access_test.874610487	Mar 03 02:26:22 PM PST 24	Mar 03 02:26:29 PM PST 24	2162890611 ps
T55	/workspace/coverage/default/28.sysrst_ctrl_edge_detect.1783414774	Mar 03 02:26:03 PM PST 24	Mar 03 02:26:06 PM PST 24	3532628722 ps
T163	/workspace/coverage/default/21.sysrst_ctrl_in_out_inverted.2409077290	Mar 03 02:25:52 PM PST 24	Mar 03 02:25:59 PM PST 24	2447837150 ps
T151	/workspace/coverage/default/26.sysrst_ctrl_edge_detect.2184992336	Mar 03 02:26:04 PM PST 24	Mar 03 02:26:06 PM PST 24	3036370227 ps
T164	/workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.506923586	Mar 03 02:26:46 PM PST 24	Mar 03 02:26:49 PM PST 24	3736169871 ps
T165	/workspace/coverage/default/5.sysrst_ctrl_pin_access_test.196649608	Mar 03 02:25:17 PM PST 24	Mar 03 02:25:24 PM PST 24	2089975147 ps
T113	/workspace/coverage/default/0.sysrst_ctrl_ultra_low_pwr.1257720065	Mar 03 02:25:08 PM PST 24	Mar 03 02:25:15 PM PST 24	3469050359 ps
T166	/workspace/coverage/default/30.sysrst_ctrl_in_out_inverted.1331056668	Mar 03 02:26:06 PM PST 24	Mar 03 02:26:10 PM PST 24	2478357177 ps
T167	/workspace/coverage/default/19.sysrst_ctrl_ultra_low_pwr.45712236	Mar 03 02:25:51 PM PST 24	Mar 03 02:25:57 PM PST 24	5852592762 ps
T168	/workspace/coverage/default/48.sysrst_ctrl_pin_access_test.3890930083	Mar 03 02:26:50 PM PST 24	Mar 03 02:26:54 PM PST 24	2051189797 ps
T114	/workspace/coverage/default/28.sysrst_ctrl_stress_all.2628232878	Mar 03 02:26:07 PM PST 24	Mar 03 02:26:32 PM PST 24	12681394294 ps
T456	/workspace/coverage/default/43.sysrst_ctrl_alert_test.166794523	Mar 03 02:26:29 PM PST 24	Mar 03 02:26:33 PM PST 24	2028430036 ps
T353	/workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.1805034884	Mar 03 02:27:01 PM PST 24	Mar 03 02:29:01 PM PST 24	85883223670 ps
T457	/workspace/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.2042146457	Mar 03 02:25:14 PM PST 24	Mar 03 02:25:23 PM PST 24	2548048893 ps
T458	/workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.4009597047	Mar 03 02:26:15 PM PST 24	Mar 03 02:26:18 PM PST 24	2626006902 ps
T459	/workspace/coverage/default/2.sysrst_ctrl_alert_test.2993568649	Mar 03 02:25:15 PM PST 24	Mar 03 02:25:21 PM PST 24	2009659171 ps
T460	/workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.2429983606	Mar 03 02:26:12 PM PST 24	Mar 03 02:26:17 PM PST 24	2488905198 ps
T88	/workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.100966214	Mar 03 02:25:19 PM PST 24	Mar 03 02:27:27 PM PST 24	273678463248 ps
T196	/workspace/coverage/default/38.sysrst_ctrl_pin_override_test.3384640456	Mar 03 02:26:06 PM PST 24	Mar 03 02:26:13 PM PST 24	2513625266 ps
T95	/workspace/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.2766744102	Mar 03 02:26:06 PM PST 24	Mar 03 02:27:33 PM PST 24	69309150249 ps
T80	/workspace/coverage/default/34.sysrst_ctrl_edge_detect.1360522249	Mar 03 02:26:12 PM PST 24	Mar 03 02:26:22 PM PST 24	5842789601 ps
T115	/workspace/coverage/default/13.sysrst_ctrl_ultra_low_pwr.924582558	Mar 03 02:25:31 PM PST 24	Mar 03 02:25:37 PM PST 24	14377002337 ps
T197	/workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.1269634131	Mar 03 02:26:38 PM PST 24	Mar 03 02:26:42 PM PST 24	3989278781 ps
T198	/workspace/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.468733328	Mar 03 02:26:00 PM PST 24	Mar 03 02:26:29 PM PST 24	39383784999 ps
T199	/workspace/coverage/default/11.sysrst_ctrl_pin_override_test.32727877	Mar 03 02:25:21 PM PST 24	Mar 03 02:25:22 PM PST 24	2701366811 ps
T200	/workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2700046045	Mar 03 02:25:16 PM PST 24	Mar 03 02:25:21 PM PST 24	2499290101 ps
T201	/workspace/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.3626761266	Mar 03 02:26:09 PM PST 24	Mar 03 02:28:41 PM PST 24	61088467074 ps
T461	/workspace/coverage/default/38.sysrst_ctrl_pin_access_test.1587271047	Mar 03 02:26:06 PM PST 24	Mar 03 02:26:13 PM PST 24	2085222731 ps
T152	/workspace/coverage/default/15.sysrst_ctrl_stress_all.3683821885	Mar 03 02:25:37 PM PST 24	Mar 03 02:31:40 PM PST 24	144108079385 ps
T462	/workspace/coverage/default/24.sysrst_ctrl_pin_access_test.3340726962	Mar 03 02:25:52 PM PST 24	Mar 03 02:25:58 PM PST 24	2222239209 ps