Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
7 |
1 |
|
|
T121 |
7 |
| auto[1] |
13 |
1 |
|
|
T121 |
13 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
11 |
1 |
|
|
T121 |
11 |
| auto[1] |
9 |
1 |
|
|
T121 |
9 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
8 |
1 |
|
|
T121 |
8 |
| auto[1] |
12 |
1 |
|
|
T121 |
12 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
13 |
1 |
|
|
T121 |
13 |
| auto[1] |
7 |
1 |
|
|
T121 |
7 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
12 |
1 |
|
|
T121 |
12 |
| auto[1] |
8 |
1 |
|
|
T121 |
8 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
7 |
1 |
|
|
T121 |
7 |
| auto[1] |
13 |
1 |
|
|
T121 |
13 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
9 |
1 |
|
|
T121 |
9 |
| auto[1] |
11 |
1 |
|
|
T121 |
11 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
8 |
1 |
|
|
T121 |
8 |
| auto[1] |
12 |
1 |
|
|
T121 |
12 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
10 |
1 |
|
|
T121 |
10 |
| auto[1] |
10 |
1 |
|
|
T121 |
10 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
12 |
1 |
|
|
T121 |
12 |
| auto[1] |
8 |
1 |
|
|
T121 |
8 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
10 |
1 |
|
|
T121 |
10 |
| auto[1] |
10 |
1 |
|
|
T121 |
10 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
8 |
1 |
|
|
T121 |
8 |
| auto[1] |
12 |
1 |
|
|
T121 |
12 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
6 |
1 |
|
|
T121 |
6 |
| auto[1] |
14 |
1 |
|
|
T121 |
14 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
11 |
1 |
|
|
T121 |
11 |
| auto[1] |
9 |
1 |
|
|
T121 |
9 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
10 |
1 |
|
|
T121 |
10 |
| auto[1] |
10 |
1 |
|
|
T121 |
10 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
11 |
1 |
|
|
T121 |
11 |
| auto[1] |
9 |
1 |
|
|
T121 |
9 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
13 |
1 |
|
|
T121 |
13 |
| auto[1] |
7 |
1 |
|
|
T121 |
7 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
8 |
1 |
|
|
T121 |
8 |
| auto[1] |
12 |
1 |
|
|
T121 |
12 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
7 |
1 |
|
|
T121 |
7 |
| auto[1] |
13 |
1 |
|
|
T121 |
13 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
8 |
1 |
|
|
T121 |
8 |
| auto[1] |
12 |
1 |
|
|
T121 |
12 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
8 |
1 |
|
|
T121 |
8 |
| auto[1] |
12 |
1 |
|
|
T121 |
12 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
13 |
1 |
|
|
T121 |
13 |
| auto[1] |
7 |
1 |
|
|
T121 |
7 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
9 |
1 |
|
|
T121 |
9 |
| auto[1] |
11 |
1 |
|
|
T121 |
11 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
8 |
1 |
|
|
T121 |
8 |
| auto[1] |
12 |
1 |
|
|
T121 |
12 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
auto[0] |
5 |
1 |
|
|
T121 |
5 |
| auto[0] |
auto[1] |
5 |
1 |
|
|
T121 |
5 |
| auto[1] |
auto[0] |
3 |
1 |
|
|
T121 |
3 |
| auto[1] |
auto[1] |
7 |
1 |
|
|
T121 |
7 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
auto[0] |
8 |
1 |
|
|
T121 |
8 |
| auto[0] |
auto[1] |
3 |
1 |
|
|
T121 |
3 |
| auto[1] |
auto[0] |
5 |
1 |
|
|
T121 |
5 |
| auto[1] |
auto[1] |
4 |
1 |
|
|
T121 |
4 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
auto[0] |
8 |
1 |
|
|
T121 |
8 |
| auto[0] |
auto[1] |
5 |
1 |
|
|
T121 |
5 |
| auto[1] |
auto[0] |
4 |
1 |
|
|
T121 |
4 |
| auto[1] |
auto[1] |
3 |
1 |
|
|
T121 |
3 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
auto[0] |
3 |
1 |
|
|
T121 |
3 |
| auto[0] |
auto[1] |
5 |
1 |
|
|
T121 |
5 |
| auto[1] |
auto[0] |
4 |
1 |
|
|
T121 |
4 |
| auto[1] |
auto[1] |
8 |
1 |
|
|
T121 |
8 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
auto[0] |
4 |
1 |
|
|
T121 |
4 |
| auto[0] |
auto[1] |
3 |
1 |
|
|
T121 |
3 |
| auto[1] |
auto[0] |
5 |
1 |
|
|
T121 |
5 |
| auto[1] |
auto[1] |
8 |
1 |
|
|
T121 |
8 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
auto[0] |
4 |
1 |
|
|
T121 |
4 |
| auto[0] |
auto[1] |
4 |
1 |
|
|
T121 |
4 |
| auto[1] |
auto[0] |
4 |
1 |
|
|
T121 |
4 |
| auto[1] |
auto[1] |
8 |
1 |
|
|
T121 |
8 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
auto[0] |
10 |
1 |
|
|
T121 |
10 |
| auto[0] |
auto[1] |
3 |
1 |
|
|
T121 |
3 |
| auto[1] |
auto[0] |
2 |
1 |
|
|
T121 |
2 |
| auto[1] |
auto[1] |
5 |
1 |
|
|
T121 |
5 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
auto[0] |
7 |
1 |
|
|
T121 |
7 |
| auto[0] |
auto[1] |
2 |
1 |
|
|
T121 |
2 |
| auto[1] |
auto[0] |
3 |
1 |
|
|
T121 |
3 |
| auto[1] |
auto[1] |
8 |
1 |
|
|
T121 |
8 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
1 |
3 |
75.00 |
1 |
Automatically Generated Cross Bins for ac_presentXval
Uncovered bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0]] |
[auto[0]] |
0 |
1 |
1 |
|
Covered bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
auto[1] |
6 |
1 |
|
|
T121 |
6 |
| auto[1] |
auto[0] |
7 |
1 |
|
|
T121 |
7 |
| auto[1] |
auto[1] |
7 |
1 |
|
|
T121 |
7 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
auto[0] |
11 |
1 |
|
|
T121 |
11 |
| auto[1] |
auto[1] |
9 |
1 |
|
|
T121 |
9 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
auto[0] |
5 |
1 |
|
|
T121 |
5 |
| auto[0] |
auto[1] |
3 |
1 |
|
|
T121 |
3 |
| auto[1] |
auto[0] |
5 |
1 |
|
|
T121 |
5 |
| auto[1] |
auto[1] |
7 |
1 |
|
|
T121 |
7 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
auto[0] |
8 |
1 |
|
|
T121 |
8 |
| auto[1] |
auto[1] |
12 |
1 |
|
|
T121 |
12 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
872 |
1 |
|
|
T4 |
10 |
|
T35 |
11 |
|
T39 |
12 |
| auto[1] |
828 |
1 |
|
|
T4 |
10 |
|
T35 |
9 |
|
T39 |
8 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
853 |
1 |
|
|
T4 |
14 |
|
T35 |
10 |
|
T39 |
9 |
| auto[1] |
847 |
1 |
|
|
T4 |
6 |
|
T35 |
10 |
|
T39 |
11 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
862 |
1 |
|
|
T4 |
11 |
|
T35 |
6 |
|
T39 |
9 |
| auto[1] |
838 |
1 |
|
|
T4 |
9 |
|
T35 |
14 |
|
T39 |
11 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
853 |
1 |
|
|
T4 |
5 |
|
T35 |
10 |
|
T39 |
11 |
| auto[1] |
847 |
1 |
|
|
T4 |
15 |
|
T35 |
10 |
|
T39 |
9 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
867 |
1 |
|
|
T4 |
14 |
|
T35 |
8 |
|
T39 |
8 |
| auto[1] |
833 |
1 |
|
|
T4 |
6 |
|
T35 |
12 |
|
T39 |
12 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
826 |
1 |
|
|
T4 |
12 |
|
T35 |
12 |
|
T39 |
13 |
| auto[1] |
874 |
1 |
|
|
T4 |
8 |
|
T35 |
8 |
|
T39 |
7 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
818 |
1 |
|
|
T4 |
10 |
|
T35 |
8 |
|
T39 |
11 |
| auto[1] |
882 |
1 |
|
|
T4 |
10 |
|
T35 |
12 |
|
T39 |
9 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
874 |
1 |
|
|
T4 |
11 |
|
T35 |
15 |
|
T39 |
7 |
| auto[1] |
826 |
1 |
|
|
T4 |
9 |
|
T35 |
5 |
|
T39 |
13 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
848 |
1 |
|
|
T4 |
10 |
|
T35 |
9 |
|
T39 |
9 |
| auto[1] |
852 |
1 |
|
|
T4 |
10 |
|
T35 |
11 |
|
T39 |
11 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
874 |
1 |
|
|
T4 |
11 |
|
T35 |
14 |
|
T39 |
10 |
| auto[1] |
826 |
1 |
|
|
T4 |
9 |
|
T35 |
6 |
|
T39 |
10 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
854 |
1 |
|
|
T4 |
10 |
|
T35 |
8 |
|
T39 |
11 |
| auto[1] |
846 |
1 |
|
|
T4 |
10 |
|
T35 |
12 |
|
T39 |
9 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
834 |
1 |
|
|
T4 |
11 |
|
T35 |
14 |
|
T39 |
10 |
| auto[1] |
866 |
1 |
|
|
T4 |
9 |
|
T35 |
6 |
|
T39 |
10 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
839 |
1 |
|
|
T4 |
11 |
|
T35 |
12 |
|
T39 |
10 |
| auto[1] |
861 |
1 |
|
|
T4 |
9 |
|
T35 |
8 |
|
T39 |
10 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
853 |
1 |
|
|
T4 |
14 |
|
T35 |
10 |
|
T39 |
9 |
| auto[1] |
847 |
1 |
|
|
T4 |
6 |
|
T35 |
10 |
|
T39 |
11 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
841 |
1 |
|
|
T4 |
7 |
|
T35 |
11 |
|
T39 |
10 |
| auto[1] |
859 |
1 |
|
|
T4 |
13 |
|
T35 |
9 |
|
T39 |
10 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
862 |
1 |
|
|
T4 |
13 |
|
T35 |
9 |
|
T39 |
10 |
| auto[1] |
838 |
1 |
|
|
T4 |
7 |
|
T35 |
11 |
|
T39 |
10 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
867 |
1 |
|
|
T4 |
10 |
|
T35 |
12 |
|
T39 |
11 |
| auto[1] |
833 |
1 |
|
|
T4 |
10 |
|
T35 |
8 |
|
T39 |
9 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
842 |
1 |
|
|
T4 |
8 |
|
T35 |
10 |
|
T39 |
10 |
| auto[1] |
858 |
1 |
|
|
T4 |
12 |
|
T35 |
10 |
|
T39 |
10 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
845 |
1 |
|
|
T4 |
9 |
|
T35 |
11 |
|
T39 |
10 |
| auto[1] |
855 |
1 |
|
|
T4 |
11 |
|
T35 |
9 |
|
T39 |
10 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
843 |
1 |
|
|
T4 |
10 |
|
T35 |
12 |
|
T39 |
14 |
| auto[1] |
857 |
1 |
|
|
T4 |
10 |
|
T35 |
8 |
|
T39 |
6 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
849 |
1 |
|
|
T4 |
12 |
|
T35 |
7 |
|
T39 |
10 |
| auto[1] |
851 |
1 |
|
|
T4 |
8 |
|
T35 |
13 |
|
T39 |
10 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
838 |
1 |
|
|
T4 |
9 |
|
T35 |
14 |
|
T39 |
10 |
| auto[1] |
862 |
1 |
|
|
T4 |
11 |
|
T35 |
6 |
|
T39 |
10 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
830 |
1 |
|
|
T4 |
8 |
|
T35 |
10 |
|
T39 |
13 |
| auto[1] |
870 |
1 |
|
|
T4 |
12 |
|
T35 |
10 |
|
T39 |
7 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
834 |
1 |
|
|
T4 |
11 |
|
T35 |
14 |
|
T39 |
10 |
| auto[1] |
866 |
1 |
|
|
T4 |
9 |
|
T35 |
6 |
|
T39 |
10 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
430 |
1 |
|
|
T4 |
3 |
|
T35 |
6 |
|
T39 |
3 |
| auto[0] |
auto[1] |
411 |
1 |
|
|
T4 |
4 |
|
T35 |
5 |
|
T39 |
7 |
| auto[1] |
auto[0] |
432 |
1 |
|
|
T4 |
8 |
|
T39 |
6 |
|
T10 |
7 |
| auto[1] |
auto[1] |
427 |
1 |
|
|
T4 |
5 |
|
T35 |
9 |
|
T39 |
4 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
436 |
1 |
|
|
T4 |
3 |
|
T35 |
7 |
|
T39 |
4 |
| auto[0] |
auto[1] |
426 |
1 |
|
|
T4 |
10 |
|
T35 |
2 |
|
T39 |
6 |
| auto[1] |
auto[0] |
417 |
1 |
|
|
T4 |
2 |
|
T35 |
3 |
|
T39 |
7 |
| auto[1] |
auto[1] |
421 |
1 |
|
|
T4 |
5 |
|
T35 |
8 |
|
T39 |
3 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
444 |
1 |
|
|
T4 |
6 |
|
T35 |
5 |
|
T39 |
6 |
| auto[0] |
auto[1] |
423 |
1 |
|
|
T4 |
4 |
|
T35 |
7 |
|
T39 |
5 |
| auto[1] |
auto[0] |
423 |
1 |
|
|
T4 |
8 |
|
T35 |
3 |
|
T39 |
2 |
| auto[1] |
auto[1] |
410 |
1 |
|
|
T4 |
2 |
|
T35 |
5 |
|
T39 |
7 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
411 |
1 |
|
|
T4 |
4 |
|
T35 |
6 |
|
T39 |
8 |
| auto[0] |
auto[1] |
431 |
1 |
|
|
T4 |
4 |
|
T35 |
4 |
|
T39 |
2 |
| auto[1] |
auto[0] |
415 |
1 |
|
|
T4 |
8 |
|
T35 |
6 |
|
T39 |
5 |
| auto[1] |
auto[1] |
443 |
1 |
|
|
T4 |
4 |
|
T35 |
4 |
|
T39 |
5 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
403 |
1 |
|
|
T4 |
5 |
|
T35 |
4 |
|
T39 |
5 |
| auto[0] |
auto[1] |
442 |
1 |
|
|
T4 |
4 |
|
T35 |
7 |
|
T39 |
5 |
| auto[1] |
auto[0] |
415 |
1 |
|
|
T4 |
5 |
|
T35 |
4 |
|
T39 |
6 |
| auto[1] |
auto[1] |
440 |
1 |
|
|
T4 |
6 |
|
T35 |
5 |
|
T39 |
4 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
430 |
1 |
|
|
T4 |
6 |
|
T35 |
8 |
|
T39 |
5 |
| auto[0] |
auto[1] |
413 |
1 |
|
|
T4 |
4 |
|
T35 |
4 |
|
T39 |
9 |
| auto[1] |
auto[0] |
444 |
1 |
|
|
T4 |
5 |
|
T35 |
7 |
|
T39 |
2 |
| auto[1] |
auto[1] |
413 |
1 |
|
|
T4 |
5 |
|
T35 |
1 |
|
T39 |
4 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
425 |
1 |
|
|
T4 |
7 |
|
T35 |
9 |
|
T39 |
5 |
| auto[0] |
auto[1] |
413 |
1 |
|
|
T4 |
2 |
|
T35 |
5 |
|
T39 |
5 |
| auto[1] |
auto[0] |
449 |
1 |
|
|
T4 |
4 |
|
T35 |
5 |
|
T39 |
5 |
| auto[1] |
auto[1] |
413 |
1 |
|
|
T4 |
7 |
|
T35 |
1 |
|
T39 |
5 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
411 |
1 |
|
|
T4 |
6 |
|
T35 |
4 |
|
T39 |
7 |
| auto[0] |
auto[1] |
419 |
1 |
|
|
T4 |
2 |
|
T35 |
6 |
|
T39 |
6 |
| auto[1] |
auto[0] |
443 |
1 |
|
|
T4 |
4 |
|
T35 |
4 |
|
T39 |
4 |
| auto[1] |
auto[1] |
427 |
1 |
|
|
T4 |
8 |
|
T35 |
6 |
|
T39 |
3 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
424 |
1 |
|
|
T4 |
6 |
|
T35 |
8 |
|
T39 |
6 |
| auto[0] |
auto[1] |
415 |
1 |
|
|
T4 |
5 |
|
T35 |
4 |
|
T39 |
4 |
| auto[1] |
auto[0] |
448 |
1 |
|
|
T4 |
4 |
|
T35 |
3 |
|
T39 |
6 |
| auto[1] |
auto[1] |
413 |
1 |
|
|
T4 |
5 |
|
T35 |
5 |
|
T39 |
4 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
853 |
1 |
|
|
T4 |
14 |
|
T35 |
10 |
|
T39 |
9 |
| auto[1] |
auto[1] |
847 |
1 |
|
|
T4 |
6 |
|
T35 |
10 |
|
T39 |
11 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
436 |
1 |
|
|
T4 |
7 |
|
T35 |
4 |
|
T39 |
5 |
| auto[0] |
auto[1] |
413 |
1 |
|
|
T4 |
5 |
|
T35 |
3 |
|
T39 |
5 |
| auto[1] |
auto[0] |
412 |
1 |
|
|
T4 |
3 |
|
T35 |
5 |
|
T39 |
4 |
| auto[1] |
auto[1] |
439 |
1 |
|
|
T4 |
5 |
|
T35 |
8 |
|
T39 |
6 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
834 |
1 |
|
|
T4 |
11 |
|
T35 |
14 |
|
T39 |
10 |
| auto[1] |
auto[1] |
866 |
1 |
|
|
T4 |
9 |
|
T35 |
6 |
|
T39 |
10 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
119 |
1 |
|
|
T4 |
9 |
|
T29 |
6 |
|
T43 |
13 |
| auto[1] |
141 |
1 |
|
|
T4 |
11 |
|
T29 |
14 |
|
T43 |
7 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
133 |
1 |
|
|
T4 |
13 |
|
T29 |
8 |
|
T43 |
9 |
| auto[1] |
127 |
1 |
|
|
T4 |
7 |
|
T29 |
12 |
|
T43 |
11 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
115 |
1 |
|
|
T4 |
8 |
|
T29 |
9 |
|
T43 |
7 |
| auto[1] |
145 |
1 |
|
|
T4 |
12 |
|
T29 |
11 |
|
T43 |
13 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
123 |
1 |
|
|
T4 |
7 |
|
T29 |
9 |
|
T43 |
7 |
| auto[1] |
137 |
1 |
|
|
T4 |
13 |
|
T29 |
11 |
|
T43 |
13 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
117 |
1 |
|
|
T4 |
7 |
|
T29 |
9 |
|
T43 |
10 |
| auto[1] |
143 |
1 |
|
|
T4 |
13 |
|
T29 |
11 |
|
T43 |
10 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
135 |
1 |
|
|
T4 |
10 |
|
T29 |
10 |
|
T43 |
15 |
| auto[1] |
125 |
1 |
|
|
T4 |
10 |
|
T29 |
10 |
|
T43 |
5 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
129 |
1 |
|
|
T4 |
9 |
|
T29 |
11 |
|
T43 |
11 |
| auto[1] |
131 |
1 |
|
|
T4 |
11 |
|
T29 |
9 |
|
T43 |
9 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
125 |
1 |
|
|
T4 |
6 |
|
T29 |
11 |
|
T43 |
12 |
| auto[1] |
135 |
1 |
|
|
T4 |
14 |
|
T29 |
9 |
|
T43 |
8 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
130 |
1 |
|
|
T4 |
11 |
|
T29 |
11 |
|
T43 |
12 |
| auto[1] |
130 |
1 |
|
|
T4 |
9 |
|
T29 |
9 |
|
T43 |
8 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
137 |
1 |
|
|
T4 |
11 |
|
T29 |
12 |
|
T43 |
9 |
| auto[1] |
123 |
1 |
|
|
T4 |
9 |
|
T29 |
8 |
|
T43 |
11 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
126 |
1 |
|
|
T4 |
11 |
|
T29 |
14 |
|
T43 |
7 |
| auto[1] |
134 |
1 |
|
|
T4 |
9 |
|
T29 |
6 |
|
T43 |
13 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
134 |
1 |
|
|
T4 |
11 |
|
T29 |
13 |
|
T43 |
9 |
| auto[1] |
126 |
1 |
|
|
T4 |
9 |
|
T29 |
7 |
|
T43 |
11 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
142 |
1 |
|
|
T4 |
9 |
|
T29 |
9 |
|
T43 |
9 |
| auto[1] |
118 |
1 |
|
|
T4 |
11 |
|
T29 |
11 |
|
T43 |
11 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
133 |
1 |
|
|
T4 |
13 |
|
T29 |
8 |
|
T43 |
9 |
| auto[1] |
127 |
1 |
|
|
T4 |
7 |
|
T29 |
12 |
|
T43 |
11 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
127 |
1 |
|
|
T4 |
9 |
|
T29 |
11 |
|
T43 |
6 |
| auto[1] |
133 |
1 |
|
|
T4 |
11 |
|
T29 |
9 |
|
T43 |
14 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
139 |
1 |
|
|
T4 |
10 |
|
T29 |
11 |
|
T43 |
6 |
| auto[1] |
121 |
1 |
|
|
T4 |
10 |
|
T29 |
9 |
|
T43 |
14 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
149 |
1 |
|
|
T4 |
11 |
|
T29 |
10 |
|
T43 |
10 |
| auto[1] |
111 |
1 |
|
|
T4 |
9 |
|
T29 |
10 |
|
T43 |
10 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
141 |
1 |
|
|
T4 |
10 |
|
T29 |
13 |
|
T43 |
11 |
| auto[1] |
119 |
1 |
|
|
T4 |
10 |
|
T29 |
7 |
|
T43 |
9 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
146 |
1 |
|
|
T4 |
14 |
|
T29 |
14 |
|
T43 |
6 |
| auto[1] |
114 |
1 |
|
|
T4 |
6 |
|
T29 |
6 |
|
T43 |
14 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
154 |
1 |
|
|
T4 |
13 |
|
T29 |
10 |
|
T43 |
11 |
| auto[1] |
106 |
1 |
|
|
T4 |
7 |
|
T29 |
10 |
|
T43 |
9 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
116 |
1 |
|
|
T4 |
7 |
|
T29 |
8 |
|
T43 |
8 |
| auto[1] |
144 |
1 |
|
|
T4 |
13 |
|
T29 |
12 |
|
T43 |
12 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
126 |
1 |
|
|
T4 |
12 |
|
T29 |
7 |
|
T43 |
6 |
| auto[1] |
134 |
1 |
|
|
T4 |
8 |
|
T29 |
13 |
|
T43 |
14 |