Unified Coverage Report :: Group Instance : sysrst_ctrl_key_invert_ctl_cg_(3)

Summary for Variable cfg.vif.ac_present

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.ac_present

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

43

1

T4

11

T43

11

T121

11

auto[1]

37

1

T4

9

T43

9

T121

9

---

Summary for Variable cfg.vif.bat_disable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.bat_disable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

43

1

T4

12

T43

9

T121

14

auto[1]

37

1

T4

8

T43

11

T121

6

---

Summary for Variable cfg.vif.key0_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key0_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

37

1

T4

12

T43

10

T121

6

auto[1]

43

1

T4

8

T43

10

T121

14

---

Summary for Variable cfg.vif.key0_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key0_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

41

1

T4

10

T43

11

T121

8

auto[1]

39

1

T4

10

T43

9

T121

12

---

Summary for Variable cfg.vif.key1_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key1_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

36

1

T4

10

T43

10

T121

6

auto[1]

44

1

T4

10

T43

10

T121

14

---

Summary for Variable cfg.vif.key1_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key1_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47

1

T4

12

T43

11

T121

12

auto[1]

33

1

T4

8

T43

9

T121

8

---

Summary for Variable cfg.vif.key2_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key2_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

36

1

T4

7

T43

11

T121

8

auto[1]

44

1

T4

13

T43

9

T121

12

---

Summary for Variable cfg.vif.key2_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key2_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

36

1

T4

11

T43

9

T121

9

auto[1]

44

1

T4

9

T43

11

T121

11

---

Summary for Variable cfg.vif.lid_open

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.lid_open

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

42

1

T4

9

T43

11

T121

9

auto[1]

38

1

T4

11

T43

9

T121

11

---

Summary for Variable cfg.vif.pwrb_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.pwrb_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

36

1

T4

10

T43

11

T121

8

auto[1]

44

1

T4

10

T43

9

T121

12

---

Summary for Variable cfg.vif.pwrb_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.pwrb_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35

1

T4

12

T43

8

T121

4

auto[1]

45

1

T4

8

T43

12

T121

16

---

Summary for Variable cfg.vif.z3_wakeup

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.z3_wakeup

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

42

1

T4

12

T43

13

T121

7

auto[1]

38

1

T4

8

T43

7

T121

13

---

Summary for Variable cp_ac_present

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

37

1

T4

11

T43

8

T121

10

auto[1]

43

1

T4

9

T43

12

T121

10

---

Summary for Variable cp_bat_disable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_bat_disable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

43

1

T4

12

T43

9

T121

14

auto[1]

37

1

T4

8

T43

11

T121

6

---

Summary for Variable cp_key0_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

40

1

T4

13

T43

8

T121

9

auto[1]

40

1

T4

7

T43

12

T121

11

---

Summary for Variable cp_key0_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

38

1

T4

7

T43

11

T121

9

auto[1]

42

1

T4

13

T43

9

T121

11

---

Summary for Variable cp_key1_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31

1

T4

8

T43

6

T121

8

auto[1]

49

1

T4

12

T43

14

T121

12

---

Summary for Variable cp_key1_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

40

1

T4

12

T43

9

T121

10

auto[1]

40

1

T4

8

T43

11

T121

10

---

Summary for Variable cp_key2_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

37

1

T4

8

T43

8

T121

13

auto[1]

43

1

T4

12

T43

12

T121

7

---

Summary for Variable cp_key2_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45

1

T4

12

T43

12

T121

10

auto[1]

35

1

T4

8

T43

8

T121

10

---

Summary for Variable cp_lid_open

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_lid_open

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

36

1

T4

11

T43

9

T121

8

auto[1]

44

1

T4

9

T43

11

T121

12

---

Summary for Variable cp_pwrb_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28

1

T4

7

T43

7

T121

7

auto[1]

52

1

T4

13

T43

13

T121

13

---

Summary for Variable cp_pwrb_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

39

1

T4

9

T43

12

T121

7

auto[1]

41

1

T4

11

T43

8

T121

13

---

Summary for Variable cp_z3_wakeup

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_z3_wakeup

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

42

1

T4

12

T43

13

T121

7

auto[1]

38

1

T4

8

T43

7

T121

13

---

Summary for Cross key0_inXval

Samples crossed: cp_key0_in cfg.vif.key0_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key0_inXval

Bins

cp_key0_in

cfg.vif.key0_in

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18

1

T4

8

T43

5

T121

1

auto[0]

auto[1]

22

1

T4

5

T43

3

T121

8

auto[1]

auto[0]

19

1

T4

4

T43

5

T121

5

auto[1]

auto[1]

21

1

T4

3

T43

7

T121

6

---

Summary for Cross key0_outXval

Samples crossed: cp_key0_out cfg.vif.key0_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key0_outXval

Bins

cp_key0_out

cfg.vif.key0_out

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19

1

T4

4

T43

7

T121

2

auto[0]

auto[1]

19

1

T4

3

T43

4

T121

7

auto[1]

auto[0]

22

1

T4

6

T43

4

T121

6

auto[1]

auto[1]

20

1

T4

7

T43

5

T121

5

---

Summary for Cross key1_inXval

Samples crossed: cp_key1_in cfg.vif.key1_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key1_inXval

Bins

cp_key1_in

cfg.vif.key1_in

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

14

1

T4

6

T43

2

T121

3

auto[0]

auto[1]

17

1

T4

2

T43

4

T121

5

auto[1]

auto[0]

22

1

T4

4

T43

8

T121

3

auto[1]

auto[1]

27

1

T4

8

T43

6

T121

9

---

Summary for Cross key1_outXval

Samples crossed: cp_key1_out cfg.vif.key1_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key1_outXval

Bins

cp_key1_out

cfg.vif.key1_out

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

24

1

T4

9

T43

4

T121

7

auto[0]

auto[1]

16

1

T4

3

T43

5

T121

3

auto[1]

auto[0]

23

1

T4

3

T43

7

T121

5

auto[1]

auto[1]

17

1

T4

5

T43

4

T121

5

---

Summary for Cross key2_inXval

Samples crossed: cp_key2_in cfg.vif.key2_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key2_inXval

Bins

cp_key2_in

cfg.vif.key2_in

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20

1

T4

3

T43

7

T121

5

auto[0]

auto[1]

17

1

T4

5

T43

1

T121

8

auto[1]

auto[0]

16

1

T4

4

T43

4

T121

3

auto[1]

auto[1]

27

1

T4

8

T43

8

T121

4

---

Summary for Cross key2_outXval

Samples crossed: cp_key2_out cfg.vif.key2_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key2_outXval

Bins

cp_key2_out

cfg.vif.key2_out

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

24

1

T4

7

T43

8

T121

4

auto[0]

auto[1]

21

1

T4

5

T43

4

T121

6

auto[1]

auto[0]

12

1

T4

4

T43

1

T121

5

auto[1]

auto[1]

23

1

T4

4

T43

7

T121

5

---

Summary for Cross pwrb_inXval

Samples crossed: cp_pwrb_in cfg.vif.pwrb_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for pwrb_inXval

Bins

cp_pwrb_in

cfg.vif.pwrb_in

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

10

1

T4

2

T43

3

T121

2

auto[0]

auto[1]

18

1

T4

5

T43

4

T121

5

auto[1]

auto[0]

26

1

T4

8

T43

8

T121

6

auto[1]

auto[1]

26

1

T4

5

T43

5

T121

7

---

Summary for Cross pwrb_outXval

Samples crossed: cp_pwrb_out cfg.vif.pwrb_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for pwrb_outXval

Bins

cp_pwrb_out

cfg.vif.pwrb_out

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

15

1

T4

4

T43

4

T138

7

auto[0]

auto[1]

24

1

T4

5

T43

8

T121

7

auto[1]

auto[0]

20

1

T4

8

T43

4

T121

4

auto[1]

auto[1]

21

1

T4

3

T43

4

T121

9

---

Summary for Cross ac_presentXval

Samples crossed: cp_ac_present cfg.vif.ac_present

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for ac_presentXval

Bins

cp_ac_present

cfg.vif.ac_present

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

24

1

T4

8

T43

6

T121

5

auto[0]

auto[1]

13

1

T4

3

T43

2

T121

5

auto[1]

auto[0]

19

1

T4

3

T43

5

T121

6

auto[1]

auto[1]

24

1

T4

6

T43

7

T121

4

---

Summary for Cross bat_disableXval

Samples crossed: cp_bat_disable cfg.vif.bat_disable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	2	0	2	100.00
Automatically Generated Cross Bins	2	0	2	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for bat_disableXval

Bins

cp_bat_disable

cfg.vif.bat_disable

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

43

1

T4

12

T43

9

T121

14

auto[1]

auto[1]

37

1

T4

8

T43

11

T121

6

User Defined Cross Bins for bat_disableXval

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded
invalid1	0	Excluded

---

Summary for Cross lid_openXval

Samples crossed: cp_lid_open cfg.vif.lid_open

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for lid_openXval

Bins

cp_lid_open

cfg.vif.lid_open

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

16

1

T4

5

T43

4

T121

4

auto[0]

auto[1]

20

1

T4

6

T43

5

T121

4

auto[1]

auto[0]

26

1

T4

4

T43

7

T121

5

auto[1]

auto[1]

18

1

T4

5

T43

4

T121

7

---

Summary for Cross z3_wakeupXval

Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	2	0	2	100.00
Automatically Generated Cross Bins	2	0	2	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for z3_wakeupXval

Bins

cp_z3_wakeup

cfg.vif.z3_wakeup

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

42

1

T4

12

T43

13

T121

7

auto[1]

auto[1]

38

1

T4

8

T43

7

T121

13

User Defined Cross Bins for z3_wakeupXval

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded
invalid1	0	Excluded