Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
879 |
1 |
|
|
T46 |
8 |
|
T55 |
10 |
|
T27 |
7 |
| auto[1] |
941 |
1 |
|
|
T46 |
12 |
|
T55 |
10 |
|
T27 |
13 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
887 |
1 |
|
|
T46 |
11 |
|
T55 |
12 |
|
T27 |
10 |
| auto[1] |
933 |
1 |
|
|
T46 |
9 |
|
T55 |
8 |
|
T27 |
10 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
904 |
1 |
|
|
T46 |
6 |
|
T55 |
9 |
|
T27 |
7 |
| auto[1] |
916 |
1 |
|
|
T46 |
14 |
|
T55 |
11 |
|
T27 |
13 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
904 |
1 |
|
|
T46 |
7 |
|
T55 |
12 |
|
T27 |
11 |
| auto[1] |
916 |
1 |
|
|
T46 |
13 |
|
T55 |
8 |
|
T27 |
9 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
914 |
1 |
|
|
T46 |
11 |
|
T55 |
10 |
|
T27 |
8 |
| auto[1] |
906 |
1 |
|
|
T46 |
9 |
|
T55 |
10 |
|
T27 |
12 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
917 |
1 |
|
|
T46 |
10 |
|
T55 |
6 |
|
T27 |
10 |
| auto[1] |
903 |
1 |
|
|
T46 |
10 |
|
T55 |
14 |
|
T27 |
10 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
902 |
1 |
|
|
T46 |
5 |
|
T55 |
11 |
|
T27 |
11 |
| auto[1] |
918 |
1 |
|
|
T46 |
15 |
|
T55 |
9 |
|
T27 |
9 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
891 |
1 |
|
|
T46 |
6 |
|
T55 |
9 |
|
T27 |
11 |
| auto[1] |
929 |
1 |
|
|
T46 |
14 |
|
T55 |
11 |
|
T27 |
9 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
942 |
1 |
|
|
T46 |
9 |
|
T55 |
10 |
|
T27 |
12 |
| auto[1] |
878 |
1 |
|
|
T46 |
11 |
|
T55 |
10 |
|
T27 |
8 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
912 |
1 |
|
|
T46 |
10 |
|
T55 |
10 |
|
T27 |
10 |
| auto[1] |
908 |
1 |
|
|
T46 |
10 |
|
T55 |
10 |
|
T27 |
10 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
923 |
1 |
|
|
T46 |
12 |
|
T55 |
12 |
|
T27 |
10 |
| auto[1] |
897 |
1 |
|
|
T46 |
8 |
|
T55 |
8 |
|
T27 |
10 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
902 |
1 |
|
|
T46 |
7 |
|
T55 |
15 |
|
T27 |
11 |
| auto[1] |
918 |
1 |
|
|
T46 |
13 |
|
T55 |
5 |
|
T27 |
9 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
921 |
1 |
|
|
T46 |
5 |
|
T55 |
9 |
|
T27 |
10 |
| auto[1] |
899 |
1 |
|
|
T46 |
15 |
|
T55 |
11 |
|
T27 |
10 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
887 |
1 |
|
|
T46 |
11 |
|
T55 |
12 |
|
T27 |
10 |
| auto[1] |
933 |
1 |
|
|
T46 |
9 |
|
T55 |
8 |
|
T27 |
10 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
919 |
1 |
|
|
T46 |
9 |
|
T55 |
6 |
|
T27 |
5 |
| auto[1] |
901 |
1 |
|
|
T46 |
11 |
|
T55 |
14 |
|
T27 |
15 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
895 |
1 |
|
|
T46 |
8 |
|
T55 |
13 |
|
T27 |
9 |
| auto[1] |
925 |
1 |
|
|
T46 |
12 |
|
T55 |
7 |
|
T27 |
11 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
922 |
1 |
|
|
T46 |
8 |
|
T55 |
6 |
|
T27 |
13 |
| auto[1] |
898 |
1 |
|
|
T46 |
12 |
|
T55 |
14 |
|
T27 |
7 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
923 |
1 |
|
|
T46 |
11 |
|
T55 |
10 |
|
T27 |
11 |
| auto[1] |
897 |
1 |
|
|
T46 |
9 |
|
T55 |
10 |
|
T27 |
9 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
934 |
1 |
|
|
T46 |
11 |
|
T55 |
14 |
|
T27 |
14 |
| auto[1] |
886 |
1 |
|
|
T46 |
9 |
|
T55 |
6 |
|
T27 |
6 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
877 |
1 |
|
|
T46 |
12 |
|
T55 |
12 |
|
T27 |
10 |
| auto[1] |
943 |
1 |
|
|
T46 |
8 |
|
T55 |
8 |
|
T27 |
10 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
894 |
1 |
|
|
T46 |
14 |
|
T55 |
8 |
|
T27 |
14 |
| auto[1] |
926 |
1 |
|
|
T46 |
6 |
|
T55 |
12 |
|
T27 |
6 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
907 |
1 |
|
|
T46 |
7 |
|
T55 |
11 |
|
T27 |
12 |
| auto[1] |
913 |
1 |
|
|
T46 |
13 |
|
T55 |
9 |
|
T27 |
8 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
906 |
1 |
|
|
T46 |
11 |
|
T55 |
9 |
|
T27 |
12 |
| auto[1] |
914 |
1 |
|
|
T46 |
9 |
|
T55 |
11 |
|
T27 |
8 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
902 |
1 |
|
|
T46 |
7 |
|
T55 |
15 |
|
T27 |
11 |
| auto[1] |
918 |
1 |
|
|
T46 |
13 |
|
T55 |
5 |
|
T27 |
9 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
449 |
1 |
|
|
T46 |
3 |
|
T55 |
2 |
|
T27 |
1 |
| auto[0] |
auto[1] |
470 |
1 |
|
|
T46 |
6 |
|
T55 |
4 |
|
T27 |
4 |
| auto[1] |
auto[0] |
455 |
1 |
|
|
T46 |
3 |
|
T55 |
7 |
|
T27 |
6 |
| auto[1] |
auto[1] |
446 |
1 |
|
|
T46 |
8 |
|
T55 |
7 |
|
T27 |
9 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
437 |
1 |
|
|
T46 |
3 |
|
T55 |
7 |
|
T27 |
5 |
| auto[0] |
auto[1] |
458 |
1 |
|
|
T46 |
5 |
|
T55 |
6 |
|
T27 |
4 |
| auto[1] |
auto[0] |
467 |
1 |
|
|
T46 |
4 |
|
T55 |
5 |
|
T27 |
6 |
| auto[1] |
auto[1] |
458 |
1 |
|
|
T46 |
8 |
|
T55 |
2 |
|
T27 |
5 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
450 |
1 |
|
|
T46 |
4 |
|
T55 |
3 |
|
T27 |
5 |
| auto[0] |
auto[1] |
472 |
1 |
|
|
T46 |
4 |
|
T55 |
3 |
|
T27 |
8 |
| auto[1] |
auto[0] |
464 |
1 |
|
|
T46 |
7 |
|
T55 |
7 |
|
T27 |
3 |
| auto[1] |
auto[1] |
434 |
1 |
|
|
T46 |
5 |
|
T55 |
7 |
|
T27 |
4 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
452 |
1 |
|
|
T46 |
5 |
|
T55 |
3 |
|
T27 |
5 |
| auto[0] |
auto[1] |
471 |
1 |
|
|
T46 |
6 |
|
T55 |
7 |
|
T27 |
6 |
| auto[1] |
auto[0] |
465 |
1 |
|
|
T46 |
5 |
|
T55 |
3 |
|
T27 |
5 |
| auto[1] |
auto[1] |
432 |
1 |
|
|
T46 |
4 |
|
T55 |
7 |
|
T27 |
4 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
468 |
1 |
|
|
T46 |
3 |
|
T55 |
8 |
|
T27 |
8 |
| auto[0] |
auto[1] |
466 |
1 |
|
|
T46 |
8 |
|
T55 |
6 |
|
T27 |
6 |
| auto[1] |
auto[0] |
434 |
1 |
|
|
T46 |
2 |
|
T55 |
3 |
|
T27 |
3 |
| auto[1] |
auto[1] |
452 |
1 |
|
|
T46 |
7 |
|
T55 |
3 |
|
T27 |
3 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
434 |
1 |
|
|
T46 |
4 |
|
T55 |
6 |
|
T27 |
6 |
| auto[0] |
auto[1] |
443 |
1 |
|
|
T46 |
8 |
|
T55 |
6 |
|
T27 |
4 |
| auto[1] |
auto[0] |
457 |
1 |
|
|
T46 |
2 |
|
T55 |
3 |
|
T27 |
5 |
| auto[1] |
auto[1] |
486 |
1 |
|
|
T46 |
6 |
|
T55 |
5 |
|
T27 |
5 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
450 |
1 |
|
|
T46 |
3 |
|
T55 |
6 |
|
T27 |
4 |
| auto[0] |
auto[1] |
457 |
1 |
|
|
T46 |
4 |
|
T55 |
5 |
|
T27 |
8 |
| auto[1] |
auto[0] |
462 |
1 |
|
|
T46 |
7 |
|
T55 |
4 |
|
T27 |
6 |
| auto[1] |
auto[1] |
451 |
1 |
|
|
T46 |
6 |
|
T55 |
5 |
|
T27 |
2 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
455 |
1 |
|
|
T46 |
6 |
|
T55 |
6 |
|
T27 |
4 |
| auto[0] |
auto[1] |
451 |
1 |
|
|
T46 |
5 |
|
T55 |
3 |
|
T27 |
8 |
| auto[1] |
auto[0] |
468 |
1 |
|
|
T46 |
6 |
|
T55 |
6 |
|
T27 |
6 |
| auto[1] |
auto[1] |
446 |
1 |
|
|
T46 |
3 |
|
T55 |
5 |
|
T27 |
2 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
433 |
1 |
|
|
T55 |
4 |
|
T27 |
3 |
|
T28 |
4 |
| auto[0] |
auto[1] |
488 |
1 |
|
|
T46 |
5 |
|
T55 |
5 |
|
T27 |
7 |
| auto[1] |
auto[0] |
446 |
1 |
|
|
T46 |
8 |
|
T55 |
6 |
|
T27 |
4 |
| auto[1] |
auto[1] |
453 |
1 |
|
|
T46 |
7 |
|
T55 |
5 |
|
T27 |
6 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
887 |
1 |
|
|
T46 |
11 |
|
T55 |
12 |
|
T27 |
10 |
| auto[1] |
auto[1] |
933 |
1 |
|
|
T46 |
9 |
|
T55 |
8 |
|
T27 |
10 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
456 |
1 |
|
|
T46 |
7 |
|
T55 |
2 |
|
T27 |
7 |
| auto[0] |
auto[1] |
438 |
1 |
|
|
T46 |
7 |
|
T55 |
6 |
|
T27 |
7 |
| auto[1] |
auto[0] |
486 |
1 |
|
|
T46 |
2 |
|
T55 |
8 |
|
T27 |
5 |
| auto[1] |
auto[1] |
440 |
1 |
|
|
T46 |
4 |
|
T55 |
4 |
|
T27 |
1 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
902 |
1 |
|
|
T46 |
7 |
|
T55 |
15 |
|
T27 |
11 |
| auto[1] |
auto[1] |
918 |
1 |
|
|
T46 |
13 |
|
T55 |
5 |
|
T27 |
9 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
144 |
1 |
|
|
T9 |
11 |
|
T10 |
8 |
|
T11 |
10 |
| auto[1] |
156 |
1 |
|
|
T9 |
9 |
|
T10 |
12 |
|
T11 |
10 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
142 |
1 |
|
|
T9 |
12 |
|
T10 |
9 |
|
T11 |
10 |
| auto[1] |
158 |
1 |
|
|
T9 |
8 |
|
T10 |
11 |
|
T11 |
10 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
162 |
1 |
|
|
T9 |
8 |
|
T10 |
10 |
|
T11 |
11 |
| auto[1] |
138 |
1 |
|
|
T9 |
12 |
|
T10 |
10 |
|
T11 |
9 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
155 |
1 |
|
|
T9 |
10 |
|
T10 |
10 |
|
T11 |
14 |
| auto[1] |
145 |
1 |
|
|
T9 |
10 |
|
T10 |
10 |
|
T11 |
6 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
151 |
1 |
|
|
T9 |
10 |
|
T10 |
10 |
|
T11 |
13 |
| auto[1] |
149 |
1 |
|
|
T9 |
10 |
|
T10 |
10 |
|
T11 |
7 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
150 |
1 |
|
|
T9 |
8 |
|
T10 |
12 |
|
T11 |
10 |
| auto[1] |
150 |
1 |
|
|
T9 |
12 |
|
T10 |
8 |
|
T11 |
10 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
161 |
1 |
|
|
T9 |
14 |
|
T10 |
6 |
|
T11 |
10 |
| auto[1] |
139 |
1 |
|
|
T9 |
6 |
|
T10 |
14 |
|
T11 |
10 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
161 |
1 |
|
|
T9 |
9 |
|
T10 |
11 |
|
T11 |
11 |
| auto[1] |
139 |
1 |
|
|
T9 |
11 |
|
T10 |
9 |
|
T11 |
9 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
144 |
1 |
|
|
T9 |
11 |
|
T10 |
8 |
|
T11 |
9 |
| auto[1] |
156 |
1 |
|
|
T9 |
9 |
|
T10 |
12 |
|
T11 |
11 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
144 |
1 |
|
|
T9 |
13 |
|
T10 |
8 |
|
T11 |
10 |
| auto[1] |
156 |
1 |
|
|
T9 |
7 |
|
T10 |
12 |
|
T11 |
10 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
142 |
1 |
|
|
T9 |
9 |
|
T10 |
10 |
|
T11 |
11 |
| auto[1] |
158 |
1 |
|
|
T9 |
11 |
|
T10 |
10 |
|
T11 |
9 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
136 |
1 |
|
|
T9 |
5 |
|
T10 |
9 |
|
T11 |
10 |
| auto[1] |
164 |
1 |
|
|
T9 |
15 |
|
T10 |
11 |
|
T11 |
10 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
153 |
1 |
|
|
T9 |
13 |
|
T10 |
6 |
|
T11 |
10 |
| auto[1] |
147 |
1 |
|
|
T9 |
7 |
|
T10 |
14 |
|
T11 |
10 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
142 |
1 |
|
|
T9 |
12 |
|
T10 |
9 |
|
T11 |
10 |
| auto[1] |
158 |
1 |
|
|
T9 |
8 |
|
T10 |
11 |
|
T11 |
10 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
148 |
1 |
|
|
T9 |
8 |
|
T10 |
12 |
|
T11 |
13 |
| auto[1] |
152 |
1 |
|
|
T9 |
12 |
|
T10 |
8 |
|
T11 |
7 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
165 |
1 |
|
|
T9 |
12 |
|
T10 |
6 |
|
T11 |
12 |
| auto[1] |
135 |
1 |
|
|
T9 |
8 |
|
T10 |
14 |
|
T11 |
8 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
152 |
1 |
|
|
T9 |
8 |
|
T10 |
8 |
|
T11 |
7 |
| auto[1] |
148 |
1 |
|
|
T9 |
12 |
|
T10 |
12 |
|
T11 |
13 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
163 |
1 |
|
|
T9 |
10 |
|
T10 |
10 |
|
T11 |
10 |
| auto[1] |
137 |
1 |
|
|
T9 |
10 |
|
T10 |
10 |
|
T11 |
10 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
137 |
1 |
|
|
T9 |
9 |
|
T10 |
8 |
|
T11 |
8 |
| auto[1] |
163 |
1 |
|
|
T9 |
11 |
|
T10 |
12 |
|
T11 |
12 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
159 |
1 |
|
|
T9 |
14 |
|
T10 |
11 |
|
T11 |
9 |
| auto[1] |
141 |
1 |
|
|
T9 |
6 |
|
T10 |
9 |
|
T11 |
11 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
155 |
1 |
|
|
T9 |
12 |
|
T10 |
15 |
|
T11 |
6 |
| auto[1] |
145 |
1 |
|
|
T9 |
8 |
|
T10 |
5 |
|
T11 |
14 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
164 |
1 |
|
|
T9 |
11 |
|
T10 |
15 |
|
T11 |
12 |
| auto[1] |
136 |
1 |
|
|
T9 |
9 |
|
T10 |
5 |
|
T11 |
8 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
148 |
1 |
|
|
T9 |
9 |
|
T10 |
11 |
|
T11 |
17 |
| auto[1] |
152 |
1 |
|
|
T9 |
11 |
|
T10 |
9 |
|
T11 |
3 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
136 |
1 |
|
|
T9 |
5 |
|
T10 |
9 |
|
T11 |
10 |
| auto[1] |
164 |
1 |
|
|
T9 |
15 |
|
T10 |
11 |
|
T11 |
10 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
79 |
1 |
|
|
T9 |
2 |
|
T10 |
6 |
|
T11 |
8 |
| auto[0] |
auto[1] |
69 |
1 |
|
|
T9 |
6 |
|
T10 |
6 |
|
T11 |
5 |
| auto[1] |
auto[0] |
83 |
1 |
|
|
T9 |
6 |
|
T10 |
4 |
|
T11 |
3 |
| auto[1] |
auto[1] |
69 |
1 |
|
|
T9 |
6 |
|
T10 |
4 |
|
T11 |
4 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
84 |
1 |
|
|
T9 |
5 |
|
T10 |
3 |
|
T11 |
9 |
| auto[0] |
auto[1] |
81 |
1 |
|
|
T9 |
7 |
|
T10 |
3 |
|
T11 |
3 |
| auto[1] |
auto[0] |
71 |
1 |
|
|
T9 |
5 |
|
T10 |
7 |
|
T11 |
5 |
| auto[1] |
auto[1] |
64 |
1 |
|
|
T9 |
3 |
|
T10 |
7 |
|
T11 |
3 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
81 |
1 |
|
|
T9 |
3 |
|
T10 |
5 |
|
T11 |
5 |
| auto[0] |
auto[1] |
71 |
1 |
|
|
T9 |
5 |
|
T10 |
3 |
|
T11 |
2 |
| auto[1] |
auto[0] |
70 |
1 |
|
|
T9 |
7 |
|
T10 |
5 |
|
T11 |
8 |
| auto[1] |
auto[1] |
78 |
1 |
|
|
T9 |
5 |
|
T10 |
7 |
|
T11 |
5 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
86 |
1 |
|
|
T9 |
3 |
|
T10 |
7 |
|
T11 |
5 |
| auto[0] |
auto[1] |
77 |
1 |
|
|
T9 |
7 |
|
T10 |
3 |
|
T11 |
5 |
| auto[1] |
auto[0] |
64 |
1 |
|
|
T9 |
5 |
|
T10 |
5 |
|
T11 |
5 |
| auto[1] |
auto[1] |
73 |
1 |
|
|
T9 |
5 |
|
T10 |
5 |
|
T11 |
5 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
71 |
1 |
|
|
T9 |
6 |
|
T10 |
1 |
|
T11 |
4 |
| auto[0] |
auto[1] |
66 |
1 |
|
|
T9 |
3 |
|
T10 |
7 |
|
T11 |
4 |
| auto[1] |
auto[0] |
90 |
1 |
|
|
T9 |
8 |
|
T10 |
5 |
|
T11 |
6 |
| auto[1] |
auto[1] |
73 |
1 |
|
|
T9 |
3 |
|
T10 |
7 |
|
T11 |
6 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
82 |
1 |
|
|
T9 |
6 |
|
T10 |
5 |
|
T11 |
5 |
| auto[0] |
auto[1] |
77 |
1 |
|
|
T9 |
8 |
|
T10 |
6 |
|
T11 |
4 |
| auto[1] |
auto[0] |
79 |
1 |
|
|
T9 |
3 |
|
T10 |
6 |
|
T11 |
6 |
| auto[1] |
auto[1] |
62 |
1 |
|
|
T9 |
3 |
|
T10 |
3 |
|
T11 |
5 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
75 |
1 |
|
|
T9 |
7 |
|
T10 |
7 |
|
T11 |
5 |
| auto[0] |
auto[1] |
89 |
1 |
|
|
T9 |
4 |
|
T10 |
8 |
|
T11 |
7 |
| auto[1] |
auto[0] |
69 |
1 |
|
|
T9 |
6 |
|
T10 |
1 |
|
T11 |
5 |
| auto[1] |
auto[1] |
67 |
1 |
|
|
T9 |
3 |
|
T10 |
4 |
|
T11 |
3 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
66 |
1 |
|
|
T9 |
4 |
|
T10 |
6 |
|
T11 |
8 |
| auto[0] |
auto[1] |
82 |
1 |
|
|
T9 |
5 |
|
T10 |
5 |
|
T11 |
9 |
| auto[1] |
auto[0] |
76 |
1 |
|
|
T9 |
5 |
|
T10 |
4 |
|
T11 |
3 |
| auto[1] |
auto[1] |
76 |
1 |
|
|
T9 |
6 |
|
T10 |
5 |
|
T13 |
4 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
76 |
1 |
|
|
T9 |
8 |
|
T10 |
4 |
|
T11 |
3 |
| auto[0] |
auto[1] |
77 |
1 |
|
|
T9 |
5 |
|
T10 |
2 |
|
T11 |
7 |
| auto[1] |
auto[0] |
68 |
1 |
|
|
T9 |
3 |
|
T10 |
4 |
|
T11 |
7 |
| auto[1] |
auto[1] |
79 |
1 |
|
|
T9 |
4 |
|
T10 |
10 |
|
T11 |
3 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
142 |
1 |
|
|
T9 |
12 |
|
T10 |
9 |
|
T11 |
10 |
| auto[1] |
auto[1] |
158 |
1 |
|
|
T9 |
8 |
|
T10 |
11 |
|
T11 |
10 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
70 |
1 |
|
|
T9 |
5 |
|
T10 |
5 |
|
T11 |
3 |
| auto[0] |
auto[1] |
85 |
1 |
|
|
T9 |
7 |
|
T10 |
10 |
|
T11 |
3 |
| auto[1] |
auto[0] |
74 |
1 |
|
|
T9 |
6 |
|
T10 |
3 |
|
T11 |
6 |
| auto[1] |
auto[1] |
71 |
1 |
|
|
T9 |
2 |
|
T10 |
2 |
|
T11 |
8 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
136 |
1 |
|
|
T9 |
5 |
|
T10 |
9 |
|
T11 |
10 |
| auto[1] |
auto[1] |
164 |
1 |
|
|
T9 |
15 |
|
T10 |
11 |
|
T11 |
10 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
53 |
1 |
|
|
T9 |
10 |
|
T59 |
9 |
|
T90 |
13 |
| auto[1] |
47 |
1 |
|
|
T9 |
10 |
|
T59 |
11 |
|
T90 |
7 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
47 |
1 |
|
|
T9 |
12 |
|
T59 |
11 |
|
T90 |
4 |
| auto[1] |
53 |
1 |
|
|
T9 |
8 |
|
T59 |
9 |
|
T90 |
16 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
49 |
1 |
|
|
T9 |
8 |
|
T59 |
10 |
|
T90 |
10 |
| auto[1] |
51 |
1 |
|
|
T9 |
12 |
|
T59 |
10 |
|
T90 |
10 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
55 |
1 |
|
|
T9 |
13 |
|
T59 |
12 |
|
T90 |
8 |
| auto[1] |
45 |
1 |
|
|
T9 |
7 |
|
T59 |
8 |
|
T90 |
12 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
54 |
1 |
|
|
T9 |
9 |
|
T59 |
10 |
|
T90 |
9 |
| auto[1] |
46 |
1 |
|
|
T9 |
11 |
|
T59 |
10 |
|
T90 |
11 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
49 |
1 |
|
|
T9 |
9 |
|
T59 |
13 |
|
T90 |
7 |
| auto[1] |
51 |
1 |
|
|
T9 |
11 |
|
T59 |
7 |
|
T90 |
13 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
41 |
1 |
|
|
T9 |
9 |
|
T59 |
10 |
|
T90 |
8 |
| auto[1] |
59 |
1 |
|
|
T9 |
11 |
|
T59 |
10 |
|
T90 |
12 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
56 |
1 |
|
|
T9 |
12 |
|
T59 |
11 |
|
T90 |
13 |
| auto[1] |
44 |
1 |
|
|
T9 |
8 |
|
T59 |
9 |
|
T90 |
7 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
53 |
1 |
|
|
T9 |
10 |
|
T59 |
9 |
|
T90 |
10 |
| auto[1] |
47 |
1 |
|
|
T9 |
10 |
|
T59 |
11 |
|
T90 |
10 |