Unified Coverage Report :: Cond split page

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 LINE       60
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T255,T51,T256
1	1	Covered	T4,T5,T6

 LINE       72
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Covered	T4,T5,T6
0	1	Excluded	T257,T258,T259	VC_COV_UNR
1	0	Covered	T51,T260,T261

 LINE       79
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T4,T5,T6
0	0	1	Covered	T257,T258,T259
0	1	0	Covered	T51,T260,T261
1	0	0	Covered	T257,T258,T259

 LINE       121
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T4,T5,T6
0	0	1	Covered	T51,T260,T261
0	1	0	Covered	T91,T87,T255
1	0	0	Covered	T255,T256,T262

 LINE       2115
 EXPRESSION (aon_ec_rst_ctl_we & aon_ec_rst_ctl_regwen)
             --------1--------   ----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T51,T52,T53
1	1	Covered	T4,T5,T44

 LINE       2146
 EXPRESSION (aon_ulp_ac_debounce_ctl_we & aon_ulp_ac_debounce_ctl_regwen)
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T51,T52,T260
1	1	Covered	T45,T32,T7

 LINE       2178
 EXPRESSION (aon_ulp_lid_debounce_ctl_we & aon_ulp_lid_debounce_ctl_regwen)
             -------------1-------------   ---------------2---------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T51,T53,T260
1	1	Covered	T45,T32,T7

 LINE       2210
 EXPRESSION (aon_ulp_pwrb_debounce_ctl_we & aon_ulp_pwrb_debounce_ctl_regwen)
             --------------1-------------   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T51,T52,T53
1	1	Covered	T45,T32,T7

 LINE       2330
 EXPRESSION (aon_key_invert_ctl_we & aon_key_invert_ctl_regwen)
             ----------1----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T51,T52,T53
1	1	Covered	T46,T55,T27

 LINE       2659
 EXPRESSION (aon_pin_allowed_ctl_we & aon_pin_allowed_ctl_regwen)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T51,T52,T53
1	1	Covered	T6,T46,T55

 LINE       3750
 EXPRESSION (aon_key_intr_ctl_we & aon_key_intr_ctl_regwen)
             ---------1---------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T51,T52,T260
1	1	Covered	T2,T32,T8

 LINE       4133
 EXPRESSION (aon_key_intr_debounce_ctl_we & aon_key_intr_debounce_ctl_regwen)
             --------------1-------------   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T51,T52,T260
1	1	Covered	T54,T1,T2

 LINE       4165
 EXPRESSION (aon_auto_block_debounce_ctl_we & aon_auto_block_debounce_ctl_regwen)
             ---------------1--------------   -----------------2----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T51,T53,T260
1	1	Covered	T48,T57,T32

 LINE       4225
 EXPRESSION (aon_auto_block_out_ctl_we & aon_auto_block_out_ctl_regwen)
             ------------1------------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T51,T52,T53
1	1	Covered	T48,T57,T32

 LINE       4394
 EXPRESSION (aon_com_pre_sel_ctl_0_we & aon_com_pre_sel_ctl_0_regwen)
             ------------1-----------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T51,T53,T260
1	1	Covered	T54,T1,T3

 LINE       4535
 EXPRESSION (aon_com_pre_sel_ctl_1_we & aon_com_pre_sel_ctl_1_regwen)
             ------------1-----------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T51,T53,T260
1	1	Covered	T54,T1,T3

 LINE       4676
 EXPRESSION (aon_com_pre_sel_ctl_2_we & aon_com_pre_sel_ctl_2_regwen)
             ------------1-----------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T51,T52,T53
1	1	Covered	T54,T1,T3

 LINE       4817
 EXPRESSION (aon_com_pre_sel_ctl_3_we & aon_com_pre_sel_ctl_3_regwen)
             ------------1-----------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T51,T52,T53
1	1	Covered	T54,T1,T3

 LINE       4958
 EXPRESSION (aon_com_pre_det_ctl_0_we & aon_com_pre_det_ctl_0_regwen)
             ------------1-----------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T51,T52,T53
1	1	Covered	T54,T1,T3

 LINE       4990
 EXPRESSION (aon_com_pre_det_ctl_1_we & aon_com_pre_det_ctl_1_regwen)
             ------------1-----------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T51,T52,T53
1	1	Covered	T54,T1,T3

 LINE       5022
 EXPRESSION (aon_com_pre_det_ctl_2_we & aon_com_pre_det_ctl_2_regwen)
             ------------1-----------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T51,T53,T260
1	1	Covered	T54,T1,T3

 LINE       5054
 EXPRESSION (aon_com_pre_det_ctl_3_we & aon_com_pre_det_ctl_3_regwen)
             ------------1-----------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T51,T52,T53
1	1	Covered	T54,T1,T3

 LINE       5086
 EXPRESSION (aon_com_sel_ctl_0_we & aon_com_sel_ctl_0_regwen)
             ----------1---------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T51,T52,T53
1	1	Covered	T54,T1,T26

 LINE       5227
 EXPRESSION (aon_com_sel_ctl_1_we & aon_com_sel_ctl_1_regwen)
             ----------1---------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T51,T52,T260
1	1	Covered	T54,T1,T26

 LINE       5368
 EXPRESSION (aon_com_sel_ctl_2_we & aon_com_sel_ctl_2_regwen)
             ----------1---------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T51,T52,T53
1	1	Covered	T54,T1,T26

 LINE       5509
 EXPRESSION (aon_com_sel_ctl_3_we & aon_com_sel_ctl_3_regwen)
             ----------1---------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T51,T52,T53
1	1	Covered	T54,T1,T26

 LINE       5650
 EXPRESSION (aon_com_det_ctl_0_we & aon_com_det_ctl_0_regwen)
             ----------1---------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T51,T52,T53
1	1	Covered	T54,T1,T26

 LINE       5682
 EXPRESSION (aon_com_det_ctl_1_we & aon_com_det_ctl_1_regwen)
             ----------1---------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T51,T53,T260
1	1	Covered	T54,T1,T26

 LINE       5714
 EXPRESSION (aon_com_det_ctl_2_we & aon_com_det_ctl_2_regwen)
             ----------1---------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T51,T52,T260
1	1	Covered	T54,T1,T26

 LINE       5746
 EXPRESSION (aon_com_det_ctl_3_we & aon_com_det_ctl_3_regwen)
             ----------1---------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T51,T53,T260
1	1	Covered	T54,T1,T26

 LINE       5778
 EXPRESSION (aon_com_out_ctl_0_we & aon_com_out_ctl_0_regwen)
             ----------1---------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T51,T52,T53
1	1	Covered	T54,T1,T26

 LINE       5892
 EXPRESSION (aon_com_out_ctl_1_we & aon_com_out_ctl_1_regwen)
             ----------1---------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T51,T53,T260
1	1	Covered	T54,T1,T26

 LINE       6006
 EXPRESSION (aon_com_out_ctl_2_we & aon_com_out_ctl_2_regwen)
             ----------1---------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T51,T260,T74
1	1	Covered	T54,T1,T26

 LINE       6120
 EXPRESSION (aon_com_out_ctl_3_we & aon_com_out_ctl_3_regwen)
             ----------1---------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T51,T52,T53
1	1	Covered	T54,T1,T26

 LINE       6728
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_INTR_STATE_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       6729
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_INTR_ENABLE_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T43

 LINE       6730
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_INTR_TEST_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T57,T27

 LINE       6731
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_ALERT_TEST_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T27,T29

 LINE       6732
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_REGWEN_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T48,T72,T57

 LINE       6733
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_EC_RST_CTL_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T44

 LINE       6734
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_ULP_AC_DEBOUNCE_CTL_OFFSET)
            ------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T45,T72

 LINE       6735
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_ULP_LID_DEBOUNCE_CTL_OFFSET)
            -------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T45,T71

 LINE       6736
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_ULP_PWRB_DEBOUNCE_CTL_OFFSET)
            -------------------------------------1-------------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T45,T29,T32

 LINE       6737
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_ULP_CTL_OFFSET)
            ------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T45,T72,T27

 LINE       6738
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_ULP_STATUS_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T45,T72

 LINE       6739
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_WKUP_STATUS_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T45,T57

 LINE       6740
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_KEY_INVERT_CTL_OFFSET)
            ----------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T46,T55

 LINE       6741
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_PIN_ALLOWED_CTL_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T45,T46

 LINE       6742
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_PIN_OUT_CTL_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       6743
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_PIN_OUT_VALUE_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T71,T56

 LINE       6744
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_PIN_IN_VALUE_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T48,T72,T27

 LINE       6745
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_KEY_INTR_CTL_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T2,T27

 LINE       6746
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_KEY_INTR_DEBOUNCE_CTL_OFFSET)
            -------------------------------------1-------------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T54,T1,T2

 LINE       6747
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_AUTO_BLOCK_DEBOUNCE_CTL_OFFSET)
            --------------------------------------1--------------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T48,T72

 LINE       6748
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_AUTO_BLOCK_OUT_CTL_OFFSET)
            ------------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T43,T45

 LINE       6749
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_PRE_SEL_CTL_0_OFFSET)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T48,T72

 LINE       6750
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_PRE_SEL_CTL_1_OFFSET)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T45,T71

 LINE       6751
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_PRE_SEL_CTL_2_OFFSET)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T54

 LINE       6752
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_PRE_SEL_CTL_3_OFFSET)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T54,T57,T1

 LINE       6753
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_PRE_DET_CTL_0_OFFSET)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T72,T54,T57

 LINE       6754
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_PRE_DET_CTL_1_OFFSET)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T71,T72,T54

 LINE       6755
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_PRE_DET_CTL_2_OFFSET)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T48,T72

 LINE       6756
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_PRE_DET_CTL_3_OFFSET)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T45,T54,T1

 LINE       6757
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_SEL_CTL_0_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T48,T72

 LINE       6758
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_SEL_CTL_1_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T72

 LINE       6759
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_SEL_CTL_2_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T54,T57

 LINE       6760
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_SEL_CTL_3_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T54,T57

 LINE       6761
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_DET_CTL_0_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T54,T57

 LINE       6762
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_DET_CTL_1_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T72,T54

 LINE       6763
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_DET_CTL_2_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T45,T48

 LINE       6764
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_DET_CTL_3_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T72,T54

 LINE       6765
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_OUT_CTL_0_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T54,T1

 LINE       6766
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_OUT_CTL_1_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T43,T45,T54

 LINE       6767
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_OUT_CTL_2_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T54,T1,T26

 LINE       6768
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_OUT_CTL_3_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T48,T72

 LINE       6769
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COMBO_INTR_STATUS_OFFSET)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T45,T72,T1

 LINE       6770
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_KEY_INTR_STATUS_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T71,T72

 LINE       6773
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       6773
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       6777
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[6] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[7] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[8] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1 & (~reg_be))))) | (addr_hit[12] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[13] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | (addr_hit[17] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[18] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[19] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1 & (~reg_be))))) | (addr_hit[22] & ((|(4'b1 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1 & (~reg_be))))) | (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[28] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[29] & ((|(4'b1 & (~reg_be))))) | (addr_hit[30] & ((|(4'b1 & (~reg_be))))) | (addr_hit[31] & ((|(4'b1 & (~reg_be))))) | (addr_hit[32] & ((|(4'b1 & (~reg_be))))) | (addr_hit[33] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[34] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[35] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[36] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[37] & ((|(4'b1 & (~reg_be))))) | (addr_hit[38] & ((|(4'b1 & (~reg_be))))) | (addr_hit[39] & ((|(4'b1 & (~reg_be))))) | (addr_hit[40] & ((|(4'b1 & (~reg_be))))) | (addr_hit[41] & ((|(4'b1 & (~reg_be))))) | (addr_hit[42] & ((|(4'b0011 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T42
1	0	Covered	T4,T5,T6
1	1	Covered	T91,T87,T255

 LINE       6777
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b0011 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b0011 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b0011 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b0011 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b0011 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b0011 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b0011 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b0111 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b1 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1 & (~reg_be))))) | 
     23  (addr_hit[22] & ((|(4'b1 & (~reg_be))))) | 
     24  (addr_hit[23] & ((|(4'b1 & (~reg_be))))) | 
     25  (addr_hit[24] & ((|(4'b1 & (~reg_be))))) | 
     26  (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | 
     27  (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) | 
     28  (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) | 
     29  (addr_hit[28] & ((|(4'b1111 & (~reg_be))))) | 
     30  (addr_hit[29] & ((|(4'b1 & (~reg_be))))) | 
     31  (addr_hit[30] & ((|(4'b1 & (~reg_be))))) | 
     32  (addr_hit[31] & ((|(4'b1 & (~reg_be))))) | 
     33  (addr_hit[32] & ((|(4'b1 & (~reg_be))))) | 
     34  (addr_hit[33] & ((|(4'b1111 & (~reg_be))))) | 
     35  (addr_hit[34] & ((|(4'b1111 & (~reg_be))))) | 
     36  (addr_hit[35] & ((|(4'b1111 & (~reg_be))))) | 
     37  (addr_hit[36] & ((|(4'b1111 & (~reg_be))))) | 
     38  (addr_hit[37] & ((|(4'b1 & (~reg_be))))) | 
     39  (addr_hit[38] & ((|(4'b1 & (~reg_be))))) | 
     40  (addr_hit[39] & ((|(4'b1 & (~reg_be))))) | 
     41  (addr_hit[40] & ((|(4'b1 & (~reg_be))))) | 
     42  (addr_hit[41] & ((|(4'b1 & (~reg_be))))) | 
     43  (addr_hit[42] & ((|(4'b0011 & (~reg_be))))))

Sensitive Expression == 1	Status	Tests
ALL ZEROS	Covered	T4,T5,T6
43 (addr_hit[42] & ((\|(4'...	Covered	T6,T72,T2
42 (addr_hit[41] & ((\|(4'...	Covered	T45,T72,T1
41 (addr_hit[40] & ((\|(4'...	Covered	T48,T72,T1
40 (addr_hit[39] & ((\|(4'...	Covered	T1,T26,T3
39 (addr_hit[38] & ((\|(4'...	Covered	T1,T26,T3
38 (addr_hit[37] & ((\|(4'...	Covered	T1,T26,T3
37 (addr_hit[36] & ((\|(4'...	Covered	T6,T72,T1
36 (addr_hit[35] & ((\|(4'...	Covered	T6,T45,T48
35 (addr_hit[34] & ((\|(4'...	Covered	T6,T72,T1
34 (addr_hit[33] & ((\|(4'...	Covered	T6,T57,T1
33 (addr_hit[32] & ((\|(4'...	Covered	T6,T1,T26
32 (addr_hit[31] & ((\|(4'...	Covered	T6,T1,T26
31 (addr_hit[30] & ((\|(4'...	Covered	T5,T6,T1
30 (addr_hit[29] & ((\|(4'...	Covered	T48,T72,T1
29 (addr_hit[28] & ((\|(4'...	Covered	T45,T29,T31
28 (addr_hit[27] & ((\|(4'...	Covered	T6,T48,T72
27 (addr_hit[26] & ((\|(4'...	Covered	T71,T72,T57
26 (addr_hit[25] & ((\|(4'...	Covered	T72,T57,T27
25 (addr_hit[24] & ((\|(4'...	Covered	T1,T26,T3
24 (addr_hit[23] & ((\|(4'...	Covered	T6,T1,T26
23 (addr_hit[22] & ((\|(4'...	Covered	T71,T1,T26
22 (addr_hit[21] & ((\|(4'...	Covered	T48,T72,T1
21 (addr_hit[20] & ((\|(4'...	Covered	T48,T57,T8
20 (addr_hit[19] & ((\|(4'...	Covered	T6,T48,T72
19 (addr_hit[18] & ((\|(4'...	Covered	T27,T29,T8
18 (addr_hit[17] & ((\|(4'...	Covered	T6,T27,T32
17 (addr_hit[16] & ((\|(4'...	Covered	T48,T72,T29
16 (addr_hit[15] & ((\|(4'...	Covered	T6,T71,T8
15 (addr_hit[14] & ((\|(4'...	Covered	T8,T9,T36
14 (addr_hit[13] & ((\|(4'...	Covered	T45,T72,T8
13 (addr_hit[12] & ((\|(4'...	Covered	T6,T46,T55
12 (addr_hit[11] & ((\|(4'...	Covered	T6,T45,T1
11 (addr_hit[10] & ((\|(4'...	Covered	T28,T31,T32
10 (addr_hit[9] & ((\|(4'b...	Covered	T45,T27,T7
9 (addr_hit[8] & ((\|(4'b...	Covered	T45,T7,T34
8 (addr_hit[7] & ((\|(4'b...	Covered	T6,T45,T71
7 (addr_hit[6] & ((\|(4'b...	Covered	T6,T72,T27
6 (addr_hit[5] & ((\|(4'b...	Covered	T5,T71,T1
5 (addr_hit[4] & ((\|(4'b...	Covered	T29,T8,T9
4 (addr_hit[3] & ((\|(4'b...	Covered	T6,T27,T29
3 (addr_hit[2] & ((\|(4'b...	Covered	T6,T27,T28
2 (addr_hit[1] & ((\|(4'b...	Covered	T28,T29,T8
1 (addr_hit[0] & ((\|(4'b...	Covered	T5,T42,T43

 LINE       6777
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T43
1	0	Covered	T4,T5,T6
1	1	Covered	T5,T42,T43

 LINE       6777
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T42
1	0	Covered	T5,T6,T43
1	1	Covered	T28,T29,T8

 LINE       6777
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T42
1	0	Covered	T57,T28,T8
1	1	Covered	T6,T27,T28

 LINE       6777
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T42
1	0	Covered	T29,T31,T8
1	1	Covered	T6,T27,T29

 LINE       6777
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T42
1	0	Covered	T48,T72,T57
1	1	Covered	T29,T8,T9

 LINE       6777
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T44
1	1	Covered	T5,T71,T1

 LINE       6777
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T45,T32,T7
1	1	Covered	T6,T72,T27

 LINE       6777
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T45,T29,T32
1	1	Covered	T6,T45,T71

 LINE       6777
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T45,T29,T32
1	1	Covered	T45,T7,T34

 LINE       6777
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T42
1	0	Covered	T72,T27,T32
1	1	Covered	T45,T27,T7

 LINE       6777
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T42
1	0	Covered	T6,T45,T72
1	1	Covered	T28,T31,T32

 LINE       6777
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T42
1	0	Covered	T45,T57,T1
1	1	Covered	T6,T45,T1

 LINE       6777
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T46,T55,T57
1	1	Covered	T6,T46,T55

 LINE       6777
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T46,T55
1	1	Covered	T45,T72,T8

 LINE       6777
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T42
1	0	Covered	T4,T5,T6
1	1	Covered	T8,T9,T36

 LINE       6777
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T42
1	0	Covered	T6,T56,T29
1	1	Covered	T6,T71,T8

 LINE       6777
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T42
1	0	Covered	T72,T27,T8
1	1	Covered	T48,T72,T29

 LINE       6777
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T2,T32
1	1	Covered	T6,T27,T32

 LINE       6777
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T54,T1,T2
1	1	Covered	T27,T29,T8

 LINE       6777
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T48,T57,T29
1	1	Covered	T6,T48,T72

 LINE       6777
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T42
1	0	Covered	T6,T43,T45
1	1	Covered	T48,T57,T8

 LINE       6777
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T42
1	0	Covered	T6,T54,T1
1	1	Covered	T48,T72,T1

 LINE       6777
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T42
1	0	Covered	T6,T45,T54
1	1	Covered	T71,T1,T26

 LINE       6777
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T42
1	0	Covered	T5,T54,T1
1	1	Covered	T6,T1,T26

 LINE       6777
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T42
1	0	Covered	T54,T57,T1
1	1	Covered	T1,T26,T3

 LINE       6777
 SUB-EXPRESSION (addr_hit[25] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T54,T1,T3
1	1	Covered	T72,T57,T27

 LINE       6777
 SUB-EXPRESSION (addr_hit[26] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T54,T1,T3
1	1	Covered	T71,T72,T57

 LINE       6777
 SUB-EXPRESSION (addr_hit[27] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T54,T1,T3
1	1	Covered	T6,T48,T72

 LINE       6777
 SUB-EXPRESSION (addr_hit[28] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T54,T1,T3
1	1	Covered	T45,T29,T31

 LINE       6777
 SUB-EXPRESSION (addr_hit[29] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T42
1	0	Covered	T5,T54,T1
1	1	Covered	T48,T72,T1

 LINE       6777
 SUB-EXPRESSION (addr_hit[30] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T42
1	0	Covered	T72,T54,T57
1	1	Covered	T5,T6,T1

 LINE       6777
 SUB-EXPRESSION (addr_hit[31] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T42
1	0	Covered	T6,T54,T57
1	1	Covered	T6,T1,T26

 LINE       6777
 SUB-EXPRESSION (addr_hit[32] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T42
1	0	Covered	T6,T54,T57
1	1	Covered	T6,T1,T26

 LINE       6777
 SUB-EXPRESSION (addr_hit[33] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T54,T1,T26
1	1	Covered	T6,T57,T1

 LINE       6777
 SUB-EXPRESSION (addr_hit[34] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T54,T1,T26
1	1	Covered	T6,T72,T1

 LINE       6777
 SUB-EXPRESSION (addr_hit[35] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T54,T1,T26
1	1	Covered	T6,T45,T48

 LINE       6777
 SUB-EXPRESSION (addr_hit[36] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T54,T1,T26
1	1	Covered	T6,T72,T1

 LINE       6777
 SUB-EXPRESSION (addr_hit[37] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T42
1	0	Covered	T6,T54,T1
1	1	Covered	T1,T26,T3

 LINE       6777
 SUB-EXPRESSION (addr_hit[38] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T42
1	0	Covered	T43,T45,T54
1	1	Covered	T1,T26,T3

 LINE       6777
 SUB-EXPRESSION (addr_hit[39] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T42
1	0	Covered	T54,T1,T26
1	1	Covered	T1,T26,T3

 LINE       6777
 SUB-EXPRESSION (addr_hit[40] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T42
1	0	Covered	T6,T54,T1
1	1	Covered	T48,T72,T1

 LINE       6777
 SUB-EXPRESSION (addr_hit[41] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T42
1	0	Covered	T1,T26,T3
1	1	Covered	T45,T72,T1

 LINE       6777
 SUB-EXPRESSION (addr_hit[42] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T71,T2,T27
1	1	Covered	T6,T72,T2

 LINE       6824
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T262,T263,T264
1	1	1	Covered	T1,T2,T3

 LINE       6827
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T5,T6,T43
1	1	0	Covered	T255,T256,T262
1	1	1	Covered	T5,T43,T45

 LINE       6830
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T6,T57,T27
1	1	0	Covered	T255,T262,T265
1	1	1	Covered	T28,T8,T9

 LINE       6833
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T6,T27,T29
1	1	0	Covered	T255,T256,T262
1	1	1	Covered	T31,T253,T266

 LINE       6836
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T48,T72,T57
1	1	0	Covered	T255,T51,T53
1	1	1	Covered	T49,T50,T51

 LINE       6839
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T4,T5,T44
1	1	0	Covered	T255,T262,T267
1	1	1	Covered	T4,T5,T44

 LINE       6841
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T6,T45,T72
1	1	0	Covered	T255,T267,T268
1	1	1	Covered	T45,T32,T7

 LINE       6843
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T6,T45,T71
1	1	0	Covered	T255,T256,T262
1	1	1	Covered	T45,T32,T7

 LINE       6845
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T45,T29,T32
1	1	0	Covered	T256,T262,T267
1	1	1	Covered	T45,T32,T7

 LINE       6847
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T45,T72,T27
1	1	0	Covered	T255,T262,T267
1	1	1	Covered	T32,T7,T8