Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
871 |
1 |
|
|
T1 |
8 |
|
T28 |
11 |
|
T29 |
10 |
| auto[1] |
849 |
1 |
|
|
T1 |
12 |
|
T28 |
9 |
|
T29 |
10 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
847 |
1 |
|
|
T1 |
7 |
|
T28 |
8 |
|
T29 |
15 |
| auto[1] |
873 |
1 |
|
|
T1 |
13 |
|
T28 |
12 |
|
T29 |
5 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
818 |
1 |
|
|
T1 |
9 |
|
T28 |
9 |
|
T29 |
10 |
| auto[1] |
902 |
1 |
|
|
T1 |
11 |
|
T28 |
11 |
|
T29 |
10 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
856 |
1 |
|
|
T1 |
9 |
|
T28 |
11 |
|
T29 |
8 |
| auto[1] |
864 |
1 |
|
|
T1 |
11 |
|
T28 |
9 |
|
T29 |
12 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
854 |
1 |
|
|
T1 |
11 |
|
T28 |
8 |
|
T29 |
9 |
| auto[1] |
866 |
1 |
|
|
T1 |
9 |
|
T28 |
12 |
|
T29 |
11 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
839 |
1 |
|
|
T1 |
12 |
|
T28 |
8 |
|
T29 |
13 |
| auto[1] |
881 |
1 |
|
|
T1 |
8 |
|
T28 |
12 |
|
T29 |
7 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
842 |
1 |
|
|
T1 |
10 |
|
T28 |
9 |
|
T29 |
8 |
| auto[1] |
878 |
1 |
|
|
T1 |
10 |
|
T28 |
11 |
|
T29 |
12 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
810 |
1 |
|
|
T1 |
11 |
|
T28 |
7 |
|
T29 |
9 |
| auto[1] |
910 |
1 |
|
|
T1 |
9 |
|
T28 |
13 |
|
T29 |
11 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
851 |
1 |
|
|
T1 |
11 |
|
T28 |
13 |
|
T29 |
8 |
| auto[1] |
869 |
1 |
|
|
T1 |
9 |
|
T28 |
7 |
|
T29 |
12 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
813 |
1 |
|
|
T1 |
9 |
|
T28 |
7 |
|
T29 |
10 |
| auto[1] |
907 |
1 |
|
|
T1 |
11 |
|
T28 |
13 |
|
T29 |
10 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
834 |
1 |
|
|
T1 |
7 |
|
T28 |
9 |
|
T29 |
12 |
| auto[1] |
886 |
1 |
|
|
T1 |
13 |
|
T28 |
11 |
|
T29 |
8 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
805 |
1 |
|
|
T1 |
11 |
|
T28 |
11 |
|
T29 |
11 |
| auto[1] |
915 |
1 |
|
|
T1 |
9 |
|
T28 |
9 |
|
T29 |
9 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
876 |
1 |
|
|
T1 |
7 |
|
T28 |
9 |
|
T29 |
11 |
| auto[1] |
844 |
1 |
|
|
T1 |
13 |
|
T28 |
11 |
|
T29 |
9 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
847 |
1 |
|
|
T1 |
7 |
|
T28 |
8 |
|
T29 |
15 |
| auto[1] |
873 |
1 |
|
|
T1 |
13 |
|
T28 |
12 |
|
T29 |
5 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
883 |
1 |
|
|
T1 |
14 |
|
T28 |
13 |
|
T29 |
8 |
| auto[1] |
837 |
1 |
|
|
T1 |
6 |
|
T28 |
7 |
|
T29 |
12 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
877 |
1 |
|
|
T1 |
12 |
|
T28 |
11 |
|
T29 |
12 |
| auto[1] |
843 |
1 |
|
|
T1 |
8 |
|
T28 |
9 |
|
T29 |
8 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
866 |
1 |
|
|
T1 |
12 |
|
T28 |
6 |
|
T29 |
9 |
| auto[1] |
854 |
1 |
|
|
T1 |
8 |
|
T28 |
14 |
|
T29 |
11 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
875 |
1 |
|
|
T1 |
9 |
|
T28 |
10 |
|
T29 |
11 |
| auto[1] |
845 |
1 |
|
|
T1 |
11 |
|
T28 |
10 |
|
T29 |
9 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
843 |
1 |
|
|
T1 |
12 |
|
T28 |
7 |
|
T29 |
7 |
| auto[1] |
877 |
1 |
|
|
T1 |
8 |
|
T28 |
13 |
|
T29 |
13 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
885 |
1 |
|
|
T1 |
9 |
|
T28 |
9 |
|
T29 |
10 |
| auto[1] |
835 |
1 |
|
|
T1 |
11 |
|
T28 |
11 |
|
T29 |
10 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
862 |
1 |
|
|
T1 |
10 |
|
T28 |
11 |
|
T29 |
10 |
| auto[1] |
858 |
1 |
|
|
T1 |
10 |
|
T28 |
9 |
|
T29 |
10 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
845 |
1 |
|
|
T1 |
9 |
|
T28 |
10 |
|
T29 |
9 |
| auto[1] |
875 |
1 |
|
|
T1 |
11 |
|
T28 |
10 |
|
T29 |
11 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
868 |
1 |
|
|
T1 |
11 |
|
T28 |
10 |
|
T29 |
15 |
| auto[1] |
852 |
1 |
|
|
T1 |
9 |
|
T28 |
10 |
|
T29 |
5 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
805 |
1 |
|
|
T1 |
11 |
|
T28 |
11 |
|
T29 |
11 |
| auto[1] |
915 |
1 |
|
|
T1 |
9 |
|
T28 |
9 |
|
T29 |
9 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
411 |
1 |
|
|
T1 |
7 |
|
T28 |
5 |
|
T29 |
3 |
| auto[0] |
auto[1] |
472 |
1 |
|
|
T1 |
7 |
|
T28 |
8 |
|
T29 |
5 |
| auto[1] |
auto[0] |
407 |
1 |
|
|
T1 |
2 |
|
T28 |
4 |
|
T29 |
7 |
| auto[1] |
auto[1] |
430 |
1 |
|
|
T1 |
4 |
|
T28 |
3 |
|
T29 |
5 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
427 |
1 |
|
|
T1 |
6 |
|
T28 |
5 |
|
T29 |
4 |
| auto[0] |
auto[1] |
450 |
1 |
|
|
T1 |
6 |
|
T28 |
6 |
|
T29 |
8 |
| auto[1] |
auto[0] |
429 |
1 |
|
|
T1 |
3 |
|
T28 |
6 |
|
T29 |
4 |
| auto[1] |
auto[1] |
414 |
1 |
|
|
T1 |
5 |
|
T28 |
3 |
|
T29 |
4 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
419 |
1 |
|
|
T1 |
7 |
|
T28 |
4 |
|
T29 |
4 |
| auto[0] |
auto[1] |
447 |
1 |
|
|
T1 |
5 |
|
T28 |
2 |
|
T29 |
5 |
| auto[1] |
auto[0] |
435 |
1 |
|
|
T1 |
4 |
|
T28 |
4 |
|
T29 |
5 |
| auto[1] |
auto[1] |
419 |
1 |
|
|
T1 |
4 |
|
T28 |
10 |
|
T29 |
6 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
416 |
1 |
|
|
T1 |
6 |
|
T28 |
6 |
|
T29 |
7 |
| auto[0] |
auto[1] |
459 |
1 |
|
|
T1 |
3 |
|
T28 |
4 |
|
T29 |
4 |
| auto[1] |
auto[0] |
423 |
1 |
|
|
T1 |
6 |
|
T28 |
2 |
|
T29 |
6 |
| auto[1] |
auto[1] |
422 |
1 |
|
|
T1 |
5 |
|
T28 |
8 |
|
T29 |
3 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
425 |
1 |
|
|
T1 |
6 |
|
T28 |
3 |
|
T29 |
3 |
| auto[0] |
auto[1] |
418 |
1 |
|
|
T1 |
6 |
|
T28 |
4 |
|
T29 |
4 |
| auto[1] |
auto[0] |
417 |
1 |
|
|
T1 |
4 |
|
T28 |
6 |
|
T29 |
5 |
| auto[1] |
auto[1] |
460 |
1 |
|
|
T1 |
4 |
|
T28 |
7 |
|
T29 |
8 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
430 |
1 |
|
|
T1 |
5 |
|
T28 |
3 |
|
T29 |
5 |
| auto[0] |
auto[1] |
455 |
1 |
|
|
T1 |
4 |
|
T28 |
6 |
|
T29 |
5 |
| auto[1] |
auto[0] |
380 |
1 |
|
|
T1 |
6 |
|
T28 |
4 |
|
T29 |
4 |
| auto[1] |
auto[1] |
455 |
1 |
|
|
T1 |
5 |
|
T28 |
7 |
|
T29 |
6 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
411 |
1 |
|
|
T1 |
4 |
|
T28 |
4 |
|
T29 |
7 |
| auto[0] |
auto[1] |
434 |
1 |
|
|
T1 |
5 |
|
T28 |
6 |
|
T29 |
2 |
| auto[1] |
auto[0] |
402 |
1 |
|
|
T1 |
5 |
|
T28 |
3 |
|
T29 |
3 |
| auto[1] |
auto[1] |
473 |
1 |
|
|
T1 |
6 |
|
T28 |
7 |
|
T29 |
8 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
433 |
1 |
|
|
T1 |
4 |
|
T28 |
5 |
|
T29 |
11 |
| auto[0] |
auto[1] |
435 |
1 |
|
|
T1 |
7 |
|
T28 |
5 |
|
T29 |
4 |
| auto[1] |
auto[0] |
401 |
1 |
|
|
T1 |
3 |
|
T28 |
4 |
|
T29 |
1 |
| auto[1] |
auto[1] |
451 |
1 |
|
|
T1 |
6 |
|
T28 |
6 |
|
T29 |
4 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
440 |
1 |
|
|
T1 |
2 |
|
T28 |
4 |
|
T29 |
4 |
| auto[0] |
auto[1] |
436 |
1 |
|
|
T1 |
5 |
|
T28 |
5 |
|
T29 |
7 |
| auto[1] |
auto[0] |
431 |
1 |
|
|
T1 |
6 |
|
T28 |
7 |
|
T29 |
6 |
| auto[1] |
auto[1] |
413 |
1 |
|
|
T1 |
7 |
|
T28 |
4 |
|
T29 |
3 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
847 |
1 |
|
|
T1 |
7 |
|
T28 |
8 |
|
T29 |
15 |
| auto[1] |
auto[1] |
873 |
1 |
|
|
T1 |
13 |
|
T28 |
12 |
|
T29 |
5 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
424 |
1 |
|
|
T1 |
5 |
|
T28 |
7 |
|
T29 |
4 |
| auto[0] |
auto[1] |
438 |
1 |
|
|
T1 |
5 |
|
T28 |
4 |
|
T29 |
6 |
| auto[1] |
auto[0] |
427 |
1 |
|
|
T1 |
6 |
|
T28 |
6 |
|
T29 |
4 |
| auto[1] |
auto[1] |
431 |
1 |
|
|
T1 |
4 |
|
T28 |
3 |
|
T29 |
6 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
805 |
1 |
|
|
T1 |
11 |
|
T28 |
11 |
|
T29 |
11 |
| auto[1] |
auto[1] |
915 |
1 |
|
|
T1 |
9 |
|
T28 |
9 |
|
T29 |
9 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
149 |
1 |
|
|
T40 |
12 |
|
T109 |
10 |
|
T96 |
11 |
| auto[1] |
131 |
1 |
|
|
T40 |
8 |
|
T109 |
10 |
|
T96 |
9 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
140 |
1 |
|
|
T40 |
11 |
|
T109 |
13 |
|
T96 |
7 |
| auto[1] |
140 |
1 |
|
|
T40 |
9 |
|
T109 |
7 |
|
T96 |
13 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
138 |
1 |
|
|
T40 |
12 |
|
T109 |
11 |
|
T96 |
11 |
| auto[1] |
142 |
1 |
|
|
T40 |
8 |
|
T109 |
9 |
|
T96 |
9 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
125 |
1 |
|
|
T40 |
10 |
|
T109 |
12 |
|
T96 |
8 |
| auto[1] |
155 |
1 |
|
|
T40 |
10 |
|
T109 |
8 |
|
T96 |
12 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
132 |
1 |
|
|
T40 |
6 |
|
T109 |
10 |
|
T96 |
7 |
| auto[1] |
148 |
1 |
|
|
T40 |
14 |
|
T109 |
10 |
|
T96 |
13 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
129 |
1 |
|
|
T40 |
12 |
|
T109 |
9 |
|
T96 |
7 |
| auto[1] |
151 |
1 |
|
|
T40 |
8 |
|
T109 |
11 |
|
T96 |
13 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
140 |
1 |
|
|
T40 |
6 |
|
T109 |
9 |
|
T96 |
12 |
| auto[1] |
140 |
1 |
|
|
T40 |
14 |
|
T109 |
11 |
|
T96 |
8 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
126 |
1 |
|
|
T40 |
7 |
|
T109 |
8 |
|
T96 |
9 |
| auto[1] |
154 |
1 |
|
|
T40 |
13 |
|
T109 |
12 |
|
T96 |
11 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
139 |
1 |
|
|
T40 |
8 |
|
T109 |
10 |
|
T96 |
15 |
| auto[1] |
141 |
1 |
|
|
T40 |
12 |
|
T109 |
10 |
|
T96 |
5 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
139 |
1 |
|
|
T40 |
6 |
|
T109 |
12 |
|
T96 |
12 |
| auto[1] |
141 |
1 |
|
|
T40 |
14 |
|
T109 |
8 |
|
T96 |
8 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
129 |
1 |
|
|
T40 |
8 |
|
T109 |
8 |
|
T96 |
8 |
| auto[1] |
151 |
1 |
|
|
T40 |
12 |
|
T109 |
12 |
|
T96 |
12 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
133 |
1 |
|
|
T40 |
13 |
|
T109 |
8 |
|
T96 |
6 |
| auto[1] |
147 |
1 |
|
|
T40 |
7 |
|
T109 |
12 |
|
T96 |
14 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
148 |
1 |
|
|
T40 |
10 |
|
T109 |
8 |
|
T96 |
9 |
| auto[1] |
132 |
1 |
|
|
T40 |
10 |
|
T109 |
12 |
|
T96 |
11 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
140 |
1 |
|
|
T40 |
11 |
|
T109 |
13 |
|
T96 |
7 |
| auto[1] |
140 |
1 |
|
|
T40 |
9 |
|
T109 |
7 |
|
T96 |
13 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
141 |
1 |
|
|
T40 |
12 |
|
T109 |
10 |
|
T96 |
12 |
| auto[1] |
139 |
1 |
|
|
T40 |
8 |
|
T109 |
10 |
|
T96 |
8 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
142 |
1 |
|
|
T40 |
12 |
|
T109 |
13 |
|
T96 |
9 |
| auto[1] |
138 |
1 |
|
|
T40 |
8 |
|
T109 |
7 |
|
T96 |
11 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
138 |
1 |
|
|
T40 |
9 |
|
T109 |
9 |
|
T96 |
9 |
| auto[1] |
142 |
1 |
|
|
T40 |
11 |
|
T109 |
11 |
|
T96 |
11 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
149 |
1 |
|
|
T40 |
7 |
|
T109 |
12 |
|
T96 |
9 |
| auto[1] |
131 |
1 |
|
|
T40 |
13 |
|
T109 |
8 |
|
T96 |
11 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
122 |
1 |
|
|
T40 |
10 |
|
T109 |
5 |
|
T96 |
9 |
| auto[1] |
158 |
1 |
|
|
T40 |
10 |
|
T109 |
15 |
|
T96 |
11 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
126 |
1 |
|
|
T40 |
7 |
|
T109 |
6 |
|
T96 |
6 |
| auto[1] |
154 |
1 |
|
|
T40 |
13 |
|
T109 |
14 |
|
T96 |
14 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
155 |
1 |
|
|
T40 |
9 |
|
T109 |
9 |
|
T96 |
11 |
| auto[1] |
125 |
1 |
|
|
T40 |
11 |
|
T109 |
11 |
|
T96 |
9 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
122 |
1 |
|
|
T40 |
10 |
|
T109 |
9 |
|
T96 |
4 |
| auto[1] |
158 |
1 |
|
|
T40 |
10 |
|
T109 |
11 |
|
T96 |
16 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
142 |
1 |
|
|
T40 |
8 |
|
T109 |
7 |
|
T96 |
12 |
| auto[1] |
138 |
1 |
|
|
T40 |
12 |
|
T109 |
13 |
|
T96 |
8 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
133 |
1 |
|
|
T40 |
13 |
|
T109 |
8 |
|
T96 |
6 |
| auto[1] |
147 |
1 |
|
|
T40 |
7 |
|
T109 |
12 |
|
T96 |
14 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
72 |
1 |
|
|
T40 |
7 |
|
T109 |
7 |
|
T96 |
6 |
| auto[0] |
auto[1] |
69 |
1 |
|
|
T40 |
5 |
|
T109 |
3 |
|
T96 |
6 |
| auto[1] |
auto[0] |
66 |
1 |
|
|
T40 |
5 |
|
T109 |
4 |
|
T96 |
5 |
| auto[1] |
auto[1] |
73 |
1 |
|
|
T40 |
3 |
|
T109 |
6 |
|
T96 |
3 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
66 |
1 |
|
|
T40 |
6 |
|
T109 |
9 |
|
T96 |
3 |
| auto[0] |
auto[1] |
76 |
1 |
|
|
T40 |
6 |
|
T109 |
4 |
|
T96 |
6 |
| auto[1] |
auto[0] |
59 |
1 |
|
|
T40 |
4 |
|
T109 |
3 |
|
T96 |
5 |
| auto[1] |
auto[1] |
79 |
1 |
|
|
T40 |
4 |
|
T109 |
4 |
|
T96 |
6 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
60 |
1 |
|
|
T40 |
3 |
|
T109 |
4 |
|
T96 |
4 |
| auto[0] |
auto[1] |
78 |
1 |
|
|
T40 |
6 |
|
T109 |
5 |
|
T96 |
5 |
| auto[1] |
auto[0] |
72 |
1 |
|
|
T40 |
3 |
|
T109 |
6 |
|
T96 |
3 |
| auto[1] |
auto[1] |
70 |
1 |
|
|
T40 |
8 |
|
T109 |
5 |
|
T96 |
8 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
64 |
1 |
|
|
T40 |
5 |
|
T109 |
5 |
|
T96 |
4 |
| auto[0] |
auto[1] |
85 |
1 |
|
|
T40 |
2 |
|
T109 |
7 |
|
T96 |
5 |
| auto[1] |
auto[0] |
65 |
1 |
|
|
T40 |
7 |
|
T109 |
4 |
|
T96 |
3 |
| auto[1] |
auto[1] |
66 |
1 |
|
|
T40 |
6 |
|
T109 |
4 |
|
T96 |
8 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
61 |
1 |
|
|
T40 |
5 |
|
T109 |
2 |
|
T96 |
4 |
| auto[0] |
auto[1] |
61 |
1 |
|
|
T40 |
5 |
|
T109 |
3 |
|
T96 |
5 |
| auto[1] |
auto[0] |
79 |
1 |
|
|
T40 |
1 |
|
T109 |
7 |
|
T96 |
8 |
| auto[1] |
auto[1] |
79 |
1 |
|
|
T40 |
9 |
|
T109 |
8 |
|
T96 |
3 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
56 |
1 |
|
|
T40 |
4 |
|
T109 |
2 |
|
T96 |
1 |
| auto[0] |
auto[1] |
70 |
1 |
|
|
T40 |
3 |
|
T109 |
4 |
|
T96 |
5 |
| auto[1] |
auto[0] |
70 |
1 |
|
|
T40 |
3 |
|
T109 |
6 |
|
T96 |
8 |
| auto[1] |
auto[1] |
84 |
1 |
|
|
T40 |
10 |
|
T109 |
8 |
|
T96 |
6 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
57 |
1 |
|
|
T40 |
4 |
|
T109 |
6 |
|
T96 |
2 |
| auto[0] |
auto[1] |
65 |
1 |
|
|
T40 |
6 |
|
T109 |
3 |
|
T96 |
2 |
| auto[1] |
auto[0] |
82 |
1 |
|
|
T40 |
2 |
|
T109 |
6 |
|
T96 |
10 |
| auto[1] |
auto[1] |
76 |
1 |
|
|
T40 |
8 |
|
T109 |
5 |
|
T96 |
6 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
62 |
1 |
|
|
T40 |
4 |
|
T109 |
3 |
|
T96 |
4 |
| auto[0] |
auto[1] |
80 |
1 |
|
|
T40 |
4 |
|
T109 |
4 |
|
T96 |
8 |
| auto[1] |
auto[0] |
67 |
1 |
|
|
T40 |
4 |
|
T109 |
5 |
|
T96 |
4 |
| auto[1] |
auto[1] |
71 |
1 |
|
|
T40 |
8 |
|
T109 |
8 |
|
T96 |
4 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
85 |
1 |
|
|
T40 |
7 |
|
T109 |
4 |
|
T96 |
5 |
| auto[0] |
auto[1] |
63 |
1 |
|
|
T40 |
3 |
|
T109 |
4 |
|
T96 |
4 |
| auto[1] |
auto[0] |
64 |
1 |
|
|
T40 |
5 |
|
T109 |
6 |
|
T96 |
6 |
| auto[1] |
auto[1] |
68 |
1 |
|
|
T40 |
5 |
|
T109 |
6 |
|
T96 |
5 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
140 |
1 |
|
|
T40 |
11 |
|
T109 |
13 |
|
T96 |
7 |
| auto[1] |
auto[1] |
140 |
1 |
|
|
T40 |
9 |
|
T109 |
7 |
|
T96 |
13 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
78 |
1 |
|
|
T40 |
3 |
|
T109 |
5 |
|
T96 |
8 |
| auto[0] |
auto[1] |
77 |
1 |
|
|
T40 |
6 |
|
T109 |
4 |
|
T96 |
3 |
| auto[1] |
auto[0] |
61 |
1 |
|
|
T40 |
5 |
|
T109 |
5 |
|
T96 |
7 |
| auto[1] |
auto[1] |
64 |
1 |
|
|
T40 |
6 |
|
T109 |
6 |
|
T96 |
2 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
133 |
1 |
|
|
T40 |
13 |
|
T109 |
8 |
|
T96 |
6 |
| auto[1] |
auto[1] |
147 |
1 |
|
|
T40 |
7 |
|
T109 |
12 |
|
T96 |
14 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
75 |
1 |
|
|
T40 |
10 |
|
T174 |
13 |
|
T186 |
9 |
| auto[1] |
85 |
1 |
|
|
T40 |
10 |
|
T174 |
7 |
|
T186 |
11 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
71 |
1 |
|
|
T40 |
9 |
|
T174 |
9 |
|
T186 |
11 |
| auto[1] |
89 |
1 |
|
|
T40 |
11 |
|
T174 |
11 |
|
T186 |
9 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
84 |
1 |
|
|
T40 |
12 |
|
T174 |
9 |
|
T186 |
9 |
| auto[1] |
76 |
1 |
|
|
T40 |
8 |
|
T174 |
11 |
|
T186 |
11 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
91 |
1 |
|
|
T40 |
9 |
|
T174 |
11 |
|
T186 |
12 |
| auto[1] |
69 |
1 |
|
|
T40 |
11 |
|
T174 |
9 |
|
T186 |
8 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
82 |
1 |
|
|
T40 |
10 |
|
T174 |
9 |
|
T186 |
11 |
| auto[1] |
78 |
1 |
|
|
T40 |
10 |
|
T174 |
11 |
|
T186 |
9 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
80 |
1 |
|
|
T40 |
10 |
|
T174 |
9 |
|
T186 |
10 |
| auto[1] |
80 |
1 |
|
|
T40 |
10 |
|
T174 |
11 |
|
T186 |
10 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
70 |
1 |
|
|
T40 |
13 |
|
T174 |
5 |
|
T186 |
7 |
| auto[1] |
90 |
1 |
|
|
T40 |
7 |
|
T174 |
15 |
|
T186 |
13 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
80 |
1 |
|
|
T40 |
11 |
|
T174 |
8 |
|
T186 |
11 |
| auto[1] |
80 |
1 |
|
|
T40 |
9 |
|
T174 |
12 |
|
T186 |
9 |