Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.98	99.40	96.51	100.00	98.08	98.85	99.61	93.44

Total tests in report: 915

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
59.51	59.51	78.97	78.97	69.06	69.06	86.99	86.99	10.26	10.26	79.96	79.96	64.16	64.16	27.18	27.18	/workspace/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.473976199
71.56	12.05	84.61	5.64	74.65	5.59	87.44	0.46	46.79	36.54	84.70	4.73	77.07	12.91	45.69	18.51	/workspace/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.1422323977
78.85	7.29	91.64	7.03	83.95	9.30	89.27	1.83	58.33	11.54	90.35	5.66	86.13	9.06	52.30	6.61	/workspace/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.2695768342
83.52	4.67	95.20	3.56	88.42	4.47	89.73	0.46	73.08	14.74	94.75	4.40	90.85	4.72	52.64	0.34	/workspace/coverage/default/42.sysrst_ctrl_edge_detect.3995174913
86.23	2.70	96.47	1.27	90.32	1.90	89.73	0.00	87.18	14.10	96.01	1.26	91.23	0.39	52.64	0.00	/workspace/coverage/default/1.sysrst_ctrl_feature_disable.3383521960
88.66	2.43	98.19	1.72	92.62	2.30	94.98	5.25	90.38	3.21	97.60	1.59	93.74	2.50	53.09	0.44	/workspace/coverage/default/13.sysrst_ctrl_auto_blk_key_output.461537919
90.74	2.09	98.21	0.02	92.69	0.08	94.98	0.00	90.38	0.00	97.63	0.04	94.61	0.87	66.70	13.61	/workspace/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.3788366116
91.90	1.16	98.34	0.13	92.92	0.23	97.49	2.51	90.38	0.00	97.71	0.07	96.24	1.64	70.23	3.53	/workspace/coverage/default/29.sysrst_ctrl_combo_detect.2278032318
92.93	1.03	98.36	0.02	93.83	0.91	98.17	0.68	90.38	0.00	97.74	0.04	96.24	0.00	75.76	5.53	/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.63277181
93.52	0.59	98.43	0.07	93.91	0.08	98.17	0.00	90.38	0.00	97.82	0.07	96.34	0.10	79.58	3.82	/workspace/coverage/default/25.sysrst_ctrl_stress_all.3658841490
93.95	0.43	98.54	0.11	93.96	0.05	98.17	0.00	91.67	1.28	98.00	0.18	96.44	0.10	80.85	1.27	/workspace/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.1230256556
94.35	0.40	98.68	0.13	93.98	0.03	98.17	0.00	92.95	1.28	98.08	0.07	96.53	0.10	82.08	1.22	/workspace/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.3155760289
94.65	0.29	98.69	0.02	94.03	0.05	98.17	0.00	92.95	0.00	98.11	0.04	96.82	0.29	83.74	1.67	/workspace/coverage/default/42.sysrst_ctrl_stress_all.4091924405
94.92	0.28	98.79	0.09	94.46	0.43	98.17	0.00	92.95	0.00	98.26	0.15	97.50	0.67	84.33	0.59	/workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.1365234930
95.18	0.26	98.84	0.06	94.46	0.00	98.17	0.00	92.95	0.00	98.26	0.00	97.59	0.10	85.99	1.67	/workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.612546335
95.43	0.24	98.90	0.06	94.54	0.08	99.54	1.37	92.95	0.00	98.26	0.00	97.59	0.00	86.19	0.20	/workspace/coverage/default/22.sysrst_ctrl_alert_test.2373431893
95.63	0.20	98.94	0.04	94.87	0.33	99.54	0.00	93.59	0.64	98.30	0.04	97.98	0.39	86.19	0.00	/workspace/coverage/default/16.sysrst_ctrl_ultra_low_pwr.1996692612
95.83	0.20	98.99	0.06	94.94	0.08	99.54	0.00	94.23	0.64	98.37	0.07	98.17	0.19	86.53	0.34	/workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.3912500878
96.02	0.19	98.99	0.00	94.97	0.03	99.54	0.00	94.23	0.00	98.37	0.00	98.17	0.00	87.86	1.32	/workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.3989889388
96.18	0.17	98.99	0.00	96.03	1.06	99.54	0.00	94.23	0.00	98.37	0.00	98.17	0.00	87.95	0.10	/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.3454002908
96.32	0.14	99.14	0.15	96.06	0.03	99.54	0.00	94.87	0.64	98.52	0.15	98.17	0.00	87.95	0.00	/workspace/coverage/default/0.sysrst_ctrl_feature_disable.2482747082
96.46	0.14	99.18	0.04	96.11	0.05	99.54	0.00	95.51	0.64	98.56	0.04	98.36	0.19	87.95	0.00	/workspace/coverage/default/24.sysrst_ctrl_edge_detect.3102111247
96.59	0.13	99.22	0.04	96.13	0.03	99.54	0.00	96.15	0.64	98.60	0.04	98.46	0.10	88.05	0.10	/workspace/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.3969245450
96.72	0.13	99.22	0.00	96.13	0.00	99.54	0.00	96.15	0.00	98.60	0.00	98.94	0.48	88.49	0.44	/workspace/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.2541080591
96.85	0.13	99.27	0.06	96.16	0.03	99.54	0.00	96.79	0.64	98.67	0.07	99.04	0.10	88.49	0.00	/workspace/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.1736624503
96.98	0.13	99.33	0.06	96.18	0.03	99.54	0.00	97.44	0.64	98.74	0.07	99.13	0.10	88.49	0.00	/workspace/coverage/default/24.sysrst_ctrl_stress_all.2438178370
97.10	0.12	99.37	0.04	96.21	0.03	99.54	0.00	98.08	0.64	98.78	0.04	99.23	0.10	88.49	0.00	/workspace/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.1522871294
97.20	0.10	99.37	0.00	96.23	0.03	99.54	0.00	98.08	0.00	98.78	0.00	99.33	0.10	89.08	0.59	/workspace/coverage/default/33.sysrst_ctrl_combo_detect.3997363407
97.30	0.10	99.37	0.00	96.26	0.03	100.00	0.46	98.08	0.00	98.78	0.00	99.42	0.10	89.18	0.10	/workspace/coverage/default/0.sysrst_ctrl_sec_cm.1256943071
97.37	0.07	99.38	0.02	96.31	0.05	100.00	0.00	98.08	0.00	98.78	0.00	99.42	0.00	89.62	0.44	/workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.3930913294
97.43	0.06	99.38	0.00	96.31	0.00	100.00	0.00	98.08	0.00	98.78	0.00	99.42	0.00	90.06	0.44	/workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.1022406168
97.48	0.05	99.38	0.00	96.31	0.00	100.00	0.00	98.08	0.00	98.78	0.00	99.42	0.00	90.40	0.34	/workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.1113743105
97.53	0.05	99.38	0.00	96.31	0.00	100.00	0.00	98.08	0.00	98.78	0.00	99.42	0.00	90.74	0.34	/workspace/coverage/default/35.sysrst_ctrl_combo_detect.469000408
97.58	0.05	99.38	0.00	96.31	0.00	100.00	0.00	98.08	0.00	98.78	0.00	99.42	0.00	91.09	0.34	/workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.4237887730
97.62	0.04	99.38	0.00	96.31	0.00	100.00	0.00	98.08	0.00	98.78	0.00	99.42	0.00	91.38	0.29	/workspace/coverage/default/6.sysrst_ctrl_stress_all.1278631280
97.66	0.04	99.38	0.00	96.31	0.00	100.00	0.00	98.08	0.00	98.78	0.00	99.42	0.00	91.67	0.29	/workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.353151020
97.69	0.03	99.38	0.00	96.31	0.00	100.00	0.00	98.08	0.00	98.78	0.00	99.42	0.00	91.87	0.20	/workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.4230680263
97.72	0.03	99.38	0.00	96.31	0.00	100.00	0.00	98.08	0.00	98.78	0.00	99.42	0.00	92.07	0.20	/workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.2872589564
97.75	0.03	99.38	0.00	96.31	0.00	100.00	0.00	98.08	0.00	98.82	0.04	99.42	0.00	92.21	0.15	/workspace/coverage/default/36.sysrst_ctrl_pin_override_test.999086533
97.77	0.02	99.38	0.00	96.31	0.00	100.00	0.00	98.08	0.00	98.82	0.00	99.42	0.00	92.36	0.15	/workspace/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.1997643035
97.79	0.02	99.38	0.00	96.31	0.00	100.00	0.00	98.08	0.00	98.82	0.00	99.42	0.00	92.51	0.15	/workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.2506738615
97.81	0.02	99.38	0.00	96.31	0.00	100.00	0.00	98.08	0.00	98.82	0.00	99.42	0.00	92.65	0.15	/workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.2001401105
97.83	0.02	99.38	0.00	96.31	0.00	100.00	0.00	98.08	0.00	98.82	0.00	99.42	0.00	92.80	0.15	/workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.3819234914
97.85	0.02	99.38	0.00	96.33	0.03	100.00	0.00	98.08	0.00	98.82	0.00	99.52	0.10	92.80	0.00	/workspace/coverage/default/15.sysrst_ctrl_edge_detect.2467958162
97.86	0.01	99.38	0.00	96.33	0.00	100.00	0.00	98.08	0.00	98.82	0.00	99.52	0.00	92.90	0.10	/workspace/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.321201621
97.88	0.01	99.38	0.00	96.33	0.00	100.00	0.00	98.08	0.00	98.82	0.00	99.52	0.00	93.00	0.10	/workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.447412102
97.89	0.01	99.38	0.00	96.33	0.00	100.00	0.00	98.08	0.00	98.82	0.00	99.61	0.10	93.00	0.00	/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.2306497166
97.90	0.01	99.38	0.00	96.41	0.08	100.00	0.00	98.08	0.00	98.82	0.00	99.61	0.00	93.00	0.00	/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.783709850
97.91	0.01	99.40	0.02	96.41	0.00	100.00	0.00	98.08	0.00	98.85	0.04	99.61	0.00	93.00	0.00	/workspace/coverage/default/30.sysrst_ctrl_edge_detect.15560598
97.92	0.01	99.40	0.00	96.46	0.05	100.00	0.00	98.08	0.00	98.85	0.00	99.61	0.00	93.00	0.00	/workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.1268927958
97.92	0.01	99.40	0.00	96.46	0.00	100.00	0.00	98.08	0.00	98.85	0.00	99.61	0.00	93.05	0.05	/workspace/coverage/default/33.sysrst_ctrl_stress_all.688419630
97.93	0.01	99.40	0.00	96.46	0.00	100.00	0.00	98.08	0.00	98.85	0.00	99.61	0.00	93.10	0.05	/workspace/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.3179467706
97.94	0.01	99.40	0.00	96.46	0.00	100.00	0.00	98.08	0.00	98.85	0.00	99.61	0.00	93.14	0.05	/workspace/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.599631872
97.94	0.01	99.40	0.00	96.46	0.00	100.00	0.00	98.08	0.00	98.85	0.00	99.61	0.00	93.19	0.05	/workspace/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.3187864734
97.95	0.01	99.40	0.00	96.46	0.00	100.00	0.00	98.08	0.00	98.85	0.00	99.61	0.00	93.24	0.05	/workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.1078255382
97.96	0.01	99.40	0.00	96.46	0.00	100.00	0.00	98.08	0.00	98.85	0.00	99.61	0.00	93.29	0.05	/workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.4114041123
97.96	0.01	99.40	0.00	96.46	0.00	100.00	0.00	98.08	0.00	98.85	0.00	99.61	0.00	93.34	0.05	/workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.363368457
97.97	0.01	99.40	0.00	96.46	0.00	100.00	0.00	98.08	0.00	98.85	0.00	99.61	0.00	93.39	0.05	/workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.2372754474
97.98	0.01	99.40	0.00	96.46	0.00	100.00	0.00	98.08	0.00	98.85	0.00	99.61	0.00	93.44	0.05	/workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.1629854629
97.98	0.01	99.40	0.00	96.49	0.03	100.00	0.00	98.08	0.00	98.85	0.00	99.61	0.00	93.44	0.00	/workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.1947129967

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.1367596121
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.1796900434
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.3424689945
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.1809923812
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.3687191036
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.990013099
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.2103988651
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.1526422566
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.427838163
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.3203793019
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.3866079565
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.2813675497
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.652379406
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.731514401
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.1555010515
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.1973099082
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.1897047907
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.916619709
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.3686437518
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.2791584267
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.221028517
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.1493707443
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.2567948204
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.1372015785
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.120177243
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.481977206
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.468394316
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.2541678790
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.2354130675
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.2831506840
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.4014716947
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.4115036825
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.1335893798
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.1821849972
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.648924468
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.2789033279
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.211366439
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.3828128704
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.2865927068
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.861218084
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.1554332698
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.749844857
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.3401757305
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.594712781
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.2068842342
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.383355688
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.3324527535
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.1967174205
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.1752675939
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.2795329260
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.1131596752
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.3094748892
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.2155614097
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.2907771082
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.2195635863
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.2283055737
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.2468997649
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.4256274289
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.172546803
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.145737080
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.4150045746
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.474585964
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.3711972954
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.1129087249
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.891538532
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.2401007429
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.3738863471
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.3398648123
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.3851176339
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/workspace/coverage/default/40.sysrst_ctrl_alert_test.280971798
/workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.2600638627
/workspace/coverage/default/40.sysrst_ctrl_combo_detect.626065377
/workspace/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.994251694
/workspace/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.1072793316
/workspace/coverage/default/40.sysrst_ctrl_edge_detect.519387030
/workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.2824893067
/workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.300856286
/workspace/coverage/default/40.sysrst_ctrl_pin_access_test.102096998
/workspace/coverage/default/40.sysrst_ctrl_pin_override_test.1468015589
/workspace/coverage/default/40.sysrst_ctrl_smoke.4196338069
/workspace/coverage/default/40.sysrst_ctrl_stress_all.613663161
/workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.1162402315
/workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.429603097
/workspace/coverage/default/41.sysrst_ctrl_alert_test.3190911389
/workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.223988017
/workspace/coverage/default/41.sysrst_ctrl_combo_detect.651471727
/workspace/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.4111350605
/workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.4183350672
/workspace/coverage/default/41.sysrst_ctrl_edge_detect.4022663948
/workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.2263402325
/workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.638953890
/workspace/coverage/default/41.sysrst_ctrl_pin_access_test.3680916064
/workspace/coverage/default/41.sysrst_ctrl_pin_override_test.2170707272
/workspace/coverage/default/41.sysrst_ctrl_smoke.1923318884
/workspace/coverage/default/41.sysrst_ctrl_stress_all.2682196902
/workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.76082452
/workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.1950364288
/workspace/coverage/default/42.sysrst_ctrl_alert_test.388612927
/workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.1213099568
/workspace/coverage/default/42.sysrst_ctrl_combo_detect.549649240
/workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.2581714051
/workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.4124145437
/workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.2862934583
/workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.3065662191
/workspace/coverage/default/42.sysrst_ctrl_pin_access_test.4223489533
/workspace/coverage/default/42.sysrst_ctrl_pin_override_test.3224900031
/workspace/coverage/default/42.sysrst_ctrl_smoke.2400600788
/workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.895255755
/workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.1439108674
/workspace/coverage/default/43.sysrst_ctrl_alert_test.1724603912
/workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.4216071033
/workspace/coverage/default/43.sysrst_ctrl_combo_detect.3248202418
/workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.1892975031
/workspace/coverage/default/43.sysrst_ctrl_edge_detect.615149368
/workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.3429381933
/workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.2900255563
/workspace/coverage/default/43.sysrst_ctrl_pin_access_test.3147250514
/workspace/coverage/default/43.sysrst_ctrl_pin_override_test.1929064335
/workspace/coverage/default/43.sysrst_ctrl_smoke.3263276255
/workspace/coverage/default/43.sysrst_ctrl_stress_all.810780857
/workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.93716047
/workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.2022044758
/workspace/coverage/default/44.sysrst_ctrl_alert_test.3373612949
/workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.171028767
/workspace/coverage/default/44.sysrst_ctrl_combo_detect.2288008350
/workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.2192877182
/workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.1119437251
/workspace/coverage/default/44.sysrst_ctrl_edge_detect.4154874209
/workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.291440485
/workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.2712675081
/workspace/coverage/default/44.sysrst_ctrl_pin_access_test.1089813594
/workspace/coverage/default/44.sysrst_ctrl_pin_override_test.2000324259
/workspace/coverage/default/44.sysrst_ctrl_smoke.3135443000
/workspace/coverage/default/44.sysrst_ctrl_stress_all.3079571175
/workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.19829168
/workspace/coverage/default/45.sysrst_ctrl_alert_test.3995254764
/workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.1254464885
/workspace/coverage/default/45.sysrst_ctrl_combo_detect.3835023060
/workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.2333539180
/workspace/coverage/default/45.sysrst_ctrl_edge_detect.487458560
/workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.371249714
/workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.3039750346
/workspace/coverage/default/45.sysrst_ctrl_pin_access_test.2915634749
/workspace/coverage/default/45.sysrst_ctrl_pin_override_test.81327916
/workspace/coverage/default/45.sysrst_ctrl_smoke.4060623688
/workspace/coverage/default/45.sysrst_ctrl_stress_all.2102569794
/workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.2561341788
/workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.2888387743
/workspace/coverage/default/46.sysrst_ctrl_alert_test.3599123473
/workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.3872753185
/workspace/coverage/default/46.sysrst_ctrl_combo_detect.3041850746
/workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.3531648239
/workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.2950600763
/workspace/coverage/default/46.sysrst_ctrl_edge_detect.2397329570
/workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.863932238
/workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.79612541
/workspace/coverage/default/46.sysrst_ctrl_pin_access_test.665259032
/workspace/coverage/default/46.sysrst_ctrl_pin_override_test.888935055
/workspace/coverage/default/46.sysrst_ctrl_smoke.2430444657
/workspace/coverage/default/46.sysrst_ctrl_stress_all.44512045
/workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.2813058880
/workspace/coverage/default/47.sysrst_ctrl_alert_test.2230361383
/workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.348419688
/workspace/coverage/default/47.sysrst_ctrl_combo_detect.1468503085
/workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.3641333816
/workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.1833529831
/workspace/coverage/default/47.sysrst_ctrl_edge_detect.1365673843
/workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.3195215594
/workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.2048102750
/workspace/coverage/default/47.sysrst_ctrl_pin_access_test.4089403929
/workspace/coverage/default/47.sysrst_ctrl_pin_override_test.1618996360
/workspace/coverage/default/47.sysrst_ctrl_smoke.298354198
/workspace/coverage/default/47.sysrst_ctrl_stress_all.3299502735
/workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.1889102972
/workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.2305138665
/workspace/coverage/default/48.sysrst_ctrl_alert_test.2637131306
/workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.1953683065
/workspace/coverage/default/48.sysrst_ctrl_combo_detect.3864871270
/workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.2881195962
/workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.2393203875
/workspace/coverage/default/48.sysrst_ctrl_edge_detect.1527703095
/workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.3597664091
/workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.2895954514
/workspace/coverage/default/48.sysrst_ctrl_pin_access_test.309057068
/workspace/coverage/default/48.sysrst_ctrl_pin_override_test.4142749602
/workspace/coverage/default/48.sysrst_ctrl_smoke.2987473584
/workspace/coverage/default/48.sysrst_ctrl_stress_all.717869682
/workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.3114884152
/workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.2696832433
/workspace/coverage/default/49.sysrst_ctrl_alert_test.3380839570
/workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.915155143
/workspace/coverage/default/49.sysrst_ctrl_combo_detect.3368888404
/workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.1800325095
/workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.362569307
/workspace/coverage/default/49.sysrst_ctrl_edge_detect.2580042608
/workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.1171810449
/workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.1708337505
/workspace/coverage/default/49.sysrst_ctrl_pin_access_test.273340840
/workspace/coverage/default/49.sysrst_ctrl_pin_override_test.1464782508
/workspace/coverage/default/49.sysrst_ctrl_smoke.127362470
/workspace/coverage/default/49.sysrst_ctrl_stress_all.1275751708
/workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.3552767755
/workspace/coverage/default/5.sysrst_ctrl_alert_test.3166248423
/workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.1833946758
/workspace/coverage/default/5.sysrst_ctrl_combo_detect.3384299072
/workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.4290993003
/workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.2220190804
/workspace/coverage/default/5.sysrst_ctrl_edge_detect.1462881619
/workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.4278299826
/workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.1404560433
/workspace/coverage/default/5.sysrst_ctrl_pin_access_test.4046806454
/workspace/coverage/default/5.sysrst_ctrl_pin_override_test.2423913127
/workspace/coverage/default/5.sysrst_ctrl_smoke.3564562844
/workspace/coverage/default/5.sysrst_ctrl_stress_all.949592529
/workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.628081241
/workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.2042768695
/workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.2832124147
/workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.1574349944
/workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.3436461361
/workspace/coverage/default/6.sysrst_ctrl_alert_test.3640271990
/workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.2601615656
/workspace/coverage/default/6.sysrst_ctrl_combo_detect.2965194962
/workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.2945762607
/workspace/coverage/default/6.sysrst_ctrl_edge_detect.1743841189
/workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.3263795580
/workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.1352251838
/workspace/coverage/default/6.sysrst_ctrl_pin_access_test.4218191224
/workspace/coverage/default/6.sysrst_ctrl_pin_override_test.2979782511
/workspace/coverage/default/6.sysrst_ctrl_smoke.179092314
/workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.3781880497
/workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.1848259997
/workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.3241636404
/workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.1763853338
/workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.3433502045
/workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.1066763136
/workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.2719413622
/workspace/coverage/default/7.sysrst_ctrl_alert_test.4011226764
/workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.3004704275
/workspace/coverage/default/7.sysrst_ctrl_combo_detect.1500545904
/workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.4147415398
/workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.37161756
/workspace/coverage/default/7.sysrst_ctrl_edge_detect.4136349206
/workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.1532156465
/workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.1340248577
/workspace/coverage/default/7.sysrst_ctrl_pin_access_test.4176712766
/workspace/coverage/default/7.sysrst_ctrl_pin_override_test.2180342024
/workspace/coverage/default/7.sysrst_ctrl_smoke.384145197
/workspace/coverage/default/7.sysrst_ctrl_stress_all.2098846721
/workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.989107177
/workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.2163376269
/workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.1625226024
/workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.1749985599
/workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.627426077
/workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.3104284197
/workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.3745273228
/workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.1614403004
/workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.3413658837
/workspace/coverage/default/8.sysrst_ctrl_alert_test.4177490582
/workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.4207439871
/workspace/coverage/default/8.sysrst_ctrl_combo_detect.1299543902
/workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.756883551
/workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.1268704266
/workspace/coverage/default/8.sysrst_ctrl_edge_detect.3750374192
/workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.2967399629
/workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.4157182088
/workspace/coverage/default/8.sysrst_ctrl_pin_access_test.321738391
/workspace/coverage/default/8.sysrst_ctrl_pin_override_test.1383997038
/workspace/coverage/default/8.sysrst_ctrl_smoke.3695494159
/workspace/coverage/default/8.sysrst_ctrl_stress_all.1538265427
/workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.2062700688
/workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.2115329303
/workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.1309034752
/workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.554555664
/workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.3600842544
/workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.826310788
/workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.261192664
/workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.535769349
/workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.978687996
/workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.3190534411
/workspace/coverage/default/9.sysrst_ctrl_alert_test.1360870417
/workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.2123392815
/workspace/coverage/default/9.sysrst_ctrl_combo_detect.3960750329
/workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.1288579221
/workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.3476428224
/workspace/coverage/default/9.sysrst_ctrl_edge_detect.1518778704
/workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.850942387
/workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.3740953293
/workspace/coverage/default/9.sysrst_ctrl_pin_access_test.968493819
/workspace/coverage/default/9.sysrst_ctrl_pin_override_test.2120099756
/workspace/coverage/default/9.sysrst_ctrl_smoke.902907034
/workspace/coverage/default/9.sysrst_ctrl_stress_all.2489859501
/workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.1289986826
/workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.2162080555
/workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.515838431
/workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.1618458959
/workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.1658608808
/workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.4030488739
/workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.3472950171
/workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.1968463096
/workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.1726230885

Total test records in report: 915

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T5	/workspace/coverage/default/28.sysrst_ctrl_smoke.2311402838	Mar 14 01:29:01 PM PDT 24	Mar 14 01:29:03 PM PDT 24	2134694080 ps
T6	/workspace/coverage/default/13.sysrst_ctrl_auto_blk_key_output.461537919	Mar 14 01:28:22 PM PDT 24	Mar 14 01:28:25 PM PDT 24	3677383904 ps
T1	/workspace/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.473976199	Mar 14 01:28:45 PM PDT 24	Mar 14 01:30:36 PM PDT 24	87930155995 ps
T13	/workspace/coverage/default/34.sysrst_ctrl_alert_test.3169615209	Mar 14 01:29:22 PM PDT 24	Mar 14 01:29:25 PM PDT 24	2019259278 ps
T2	/workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.612546335	Mar 14 01:30:01 PM PDT 24	Mar 14 01:33:30 PM PDT 24	169142592851 ps
T3	/workspace/coverage/default/0.sysrst_ctrl_edge_detect.2003624620	Mar 14 01:27:53 PM PDT 24	Mar 14 01:28:00 PM PDT 24	4638077423 ps
T14	/workspace/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.621032071	Mar 14 01:28:47 PM PDT 24	Mar 14 01:28:55 PM PDT 24	2581947048 ps
T15	/workspace/coverage/default/4.sysrst_ctrl_alert_test.3045835023	Mar 14 01:28:05 PM PDT 24	Mar 14 01:28:07 PM PDT 24	2027978048 ps
T16	/workspace/coverage/default/22.sysrst_ctrl_alert_test.2373431893	Mar 14 01:28:51 PM PDT 24	Mar 14 01:28:53 PM PDT 24	2028126612 ps
T17	/workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.1254464885	Mar 14 01:29:57 PM PDT 24	Mar 14 01:30:02 PM PDT 24	3469538967 ps
T18	/workspace/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.3821078597	Mar 14 01:29:38 PM PDT 24	Mar 14 01:29:50 PM PDT 24	23867789304 ps
T19	/workspace/coverage/default/21.sysrst_ctrl_pin_override_test.992712610	Mar 14 01:28:47 PM PDT 24	Mar 14 01:28:51 PM PDT 24	2518310571 ps
T51	/workspace/coverage/default/37.sysrst_ctrl_pin_access_test.2075901662	Mar 14 01:29:24 PM PDT 24	Mar 14 01:29:30 PM PDT 24	2074171770 ps
T4	/workspace/coverage/default/45.sysrst_ctrl_combo_detect.3835023060	Mar 14 01:29:50 PM PDT 24	Mar 14 01:32:48 PM PDT 24	73602327835 ps
T32	/workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.2719413622	Mar 14 01:30:04 PM PDT 24	Mar 14 01:30:47 PM PDT 24	64160618923 ps
T28	/workspace/coverage/default/12.sysrst_ctrl_in_out_inverted.1837390839	Mar 14 01:28:21 PM PDT 24	Mar 14 01:28:25 PM PDT 24	2461492926 ps
T29	/workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.4157182088	Mar 14 01:28:09 PM PDT 24	Mar 14 01:28:16 PM PDT 24	2465654552 ps
T30	/workspace/coverage/default/10.sysrst_ctrl_pin_override_test.1648663135	Mar 14 01:28:21 PM PDT 24	Mar 14 01:28:23 PM PDT 24	2531219930 ps
T43	/workspace/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.2552110649	Mar 14 01:28:06 PM PDT 24	Mar 14 01:28:49 PM PDT 24	16609326308 ps
T7	/workspace/coverage/default/33.sysrst_ctrl_combo_detect.3997363407	Mar 14 01:29:14 PM PDT 24	Mar 14 01:31:21 PM PDT 24	91911774085 ps
T66	/workspace/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.1014042933	Mar 14 01:29:10 PM PDT 24	Mar 14 01:29:14 PM PDT 24	2615437982 ps
T61	/workspace/coverage/default/17.sysrst_ctrl_in_out_inverted.2654828157	Mar 14 01:28:41 PM PDT 24	Mar 14 01:28:48 PM PDT 24	2460341761 ps
T67	/workspace/coverage/default/20.sysrst_ctrl_pin_override_test.2708529402	Mar 14 01:28:44 PM PDT 24	Mar 14 01:28:47 PM PDT 24	2529251420 ps
T8	/workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.3912500878	Mar 14 01:30:03 PM PDT 24	Mar 14 01:30:44 PM PDT 24	66245406228 ps
T68	/workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.2824893067	Mar 14 01:29:37 PM PDT 24	Mar 14 01:29:44 PM PDT 24	2608668078 ps
T162	/workspace/coverage/default/32.sysrst_ctrl_smoke.3598078364	Mar 14 01:29:08 PM PDT 24	Mar 14 01:29:10 PM PDT 24	2127298123 ps
T9	/workspace/coverage/default/45.sysrst_ctrl_stress_all.2102569794	Mar 14 01:29:56 PM PDT 24	Mar 14 01:30:00 PM PDT 24	7846684233 ps
T10	/workspace/coverage/default/22.sysrst_ctrl_combo_detect.3550173985	Mar 14 01:28:47 PM PDT 24	Mar 14 01:31:27 PM PDT 24	64899899544 ps
T69	/workspace/coverage/default/0.sysrst_ctrl_pin_override_test.568816559	Mar 14 01:27:53 PM PDT 24	Mar 14 01:27:56 PM PDT 24	2529823946 ps
T163	/workspace/coverage/default/46.sysrst_ctrl_smoke.2430444657	Mar 14 01:29:51 PM PDT 24	Mar 14 01:29:57 PM PDT 24	2112436886 ps
T31	/workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.1833946758	Mar 14 01:28:04 PM PDT 24	Mar 14 01:28:09 PM PDT 24	3955461738 ps
T164	/workspace/coverage/default/36.sysrst_ctrl_smoke.556874680	Mar 14 01:29:20 PM PDT 24	Mar 14 01:29:22 PM PDT 24	2139261673 ps
T165	/workspace/coverage/default/10.sysrst_ctrl_smoke.3357971042	Mar 14 01:28:14 PM PDT 24	Mar 14 01:28:17 PM PDT 24	2115279521 ps
T11	/workspace/coverage/default/14.sysrst_ctrl_combo_detect.1781732030	Mar 14 01:28:21 PM PDT 24	Mar 14 01:29:57 PM PDT 24	157406035055 ps
T62	/workspace/coverage/default/33.sysrst_ctrl_in_out_inverted.3497724246	Mar 14 01:29:13 PM PDT 24	Mar 14 01:29:15 PM PDT 24	2594641201 ps
T301	/workspace/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.760584657	Mar 14 01:27:55 PM PDT 24	Mar 14 01:28:07 PM PDT 24	3945241334 ps
T70	/workspace/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.4007710311	Mar 14 01:27:55 PM PDT 24	Mar 14 01:28:04 PM PDT 24	2608707612 ps
T302	/workspace/coverage/default/36.sysrst_ctrl_pin_override_test.999086533	Mar 14 01:29:24 PM PDT 24	Mar 14 01:29:25 PM PDT 24	2634085225 ps
T303	/workspace/coverage/default/23.sysrst_ctrl_pin_access_test.3978608291	Mar 14 01:28:51 PM PDT 24	Mar 14 01:28:55 PM PDT 24	2261824590 ps
T12	/workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.515838431	Mar 14 01:30:08 PM PDT 24	Mar 14 01:31:28 PM PDT 24	118443151156 ps
T63	/workspace/coverage/default/19.sysrst_ctrl_in_out_inverted.7232667	Mar 14 01:28:35 PM PDT 24	Mar 14 01:28:43 PM PDT 24	2488132106 ps
T35	/workspace/coverage/default/25.sysrst_ctrl_stress_all.3658841490	Mar 14 01:28:58 PM PDT 24	Mar 14 01:51:18 PM PDT 24	1859186575824 ps
T37	/workspace/coverage/default/5.sysrst_ctrl_edge_detect.1462881619	Mar 14 01:28:04 PM PDT 24	Mar 14 01:28:06 PM PDT 24	2475687071 ps
T207	/workspace/coverage/default/2.sysrst_ctrl_alert_test.4280829387	Mar 14 01:27:52 PM PDT 24	Mar 14 01:27:58 PM PDT 24	2015700592 ps
T208	/workspace/coverage/default/6.sysrst_ctrl_pin_override_test.2979782511	Mar 14 01:28:08 PM PDT 24	Mar 14 01:28:16 PM PDT 24	2508856817 ps
T55	/workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.3531648239	Mar 14 01:29:49 PM PDT 24	Mar 14 01:31:01 PM PDT 24	49884849716 ps
T209	/workspace/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.377004590	Mar 14 01:29:38 PM PDT 24	Mar 14 01:29:45 PM PDT 24	2613549353 ps
T210	/workspace/coverage/default/16.sysrst_ctrl_pin_override_test.2787949649	Mar 14 01:28:41 PM PDT 24	Mar 14 01:28:49 PM PDT 24	2512878495 ps
T44	/workspace/coverage/default/27.sysrst_ctrl_auto_blk_key_output.2753983575	Mar 14 01:29:02 PM PDT 24	Mar 14 01:29:07 PM PDT 24	3643257738 ps
T211	/workspace/coverage/default/29.sysrst_ctrl_combo_detect.2278032318	Mar 14 01:29:08 PM PDT 24	Mar 14 01:33:33 PM PDT 24	107868771698 ps
T45	/workspace/coverage/default/5.sysrst_ctrl_stress_all.949592529	Mar 14 01:28:04 PM PDT 24	Mar 14 01:31:29 PM PDT 24	79582456930 ps
T259	/workspace/coverage/default/13.sysrst_ctrl_alert_test.1867923863	Mar 14 01:28:22 PM PDT 24	Mar 14 01:28:27 PM PDT 24	2012077697 ps
T64	/workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.1340248577	Mar 14 01:28:04 PM PDT 24	Mar 14 01:28:13 PM PDT 24	2450705730 ps
T71	/workspace/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.3467777166	Mar 14 01:29:21 PM PDT 24	Mar 14 01:29:40 PM PDT 24	26595388205 ps
T42	/workspace/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.2695768342	Mar 14 01:28:47 PM PDT 24	Mar 14 01:30:06 PM PDT 24	109083854435 ps
T46	/workspace/coverage/default/3.sysrst_ctrl_auto_blk_key_output.3071891336	Mar 14 01:27:53 PM PDT 24	Mar 14 01:27:57 PM PDT 24	3600393045 ps
T244	/workspace/coverage/default/33.sysrst_ctrl_alert_test.2832987138	Mar 14 01:29:13 PM PDT 24	Mar 14 01:29:19 PM PDT 24	2012123652 ps
T245	/workspace/coverage/default/34.sysrst_ctrl_smoke.422410138	Mar 14 01:29:16 PM PDT 24	Mar 14 01:29:18 PM PDT 24	2135681330 ps
T72	/workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.2001401105	Mar 14 01:30:04 PM PDT 24	Mar 14 01:32:17 PM PDT 24	99663820004 ps
T47	/workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.3004704275	Mar 14 01:28:09 PM PDT 24	Mar 14 01:28:10 PM PDT 24	3527570177 ps
T246	/workspace/coverage/default/27.sysrst_ctrl_smoke.265421896	Mar 14 01:29:00 PM PDT 24	Mar 14 01:29:06 PM PDT 24	2113942954 ps
T73	/workspace/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.649149428	Mar 14 01:29:28 PM PDT 24	Mar 14 01:29:38 PM PDT 24	23805067755 ps
T247	/workspace/coverage/default/8.sysrst_ctrl_combo_detect.1299543902	Mar 14 01:28:16 PM PDT 24	Mar 14 01:34:04 PM PDT 24	127364109795 ps
T25	/workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.1439108674	Mar 14 01:29:52 PM PDT 24	Mar 14 01:29:56 PM PDT 24	9243976530 ps
T26	/workspace/coverage/default/38.sysrst_ctrl_stress_all.3164046015	Mar 14 01:29:39 PM PDT 24	Mar 14 01:30:11 PM PDT 24	18100032362 ps
T36	/workspace/coverage/default/42.sysrst_ctrl_edge_detect.3995174913	Mar 14 01:29:50 PM PDT 24	Mar 14 01:29:59 PM PDT 24	3373107014 ps
T48	/workspace/coverage/default/29.sysrst_ctrl_auto_blk_key_output.2228501902	Mar 14 01:29:01 PM PDT 24	Mar 14 01:49:05 PM PDT 24	434558743820 ps
T52	/workspace/coverage/default/15.sysrst_ctrl_stress_all.2809259973	Mar 14 01:28:41 PM PDT 24	Mar 14 01:29:46 PM PDT 24	89874840845 ps
T53	/workspace/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.1926404680	Mar 14 01:29:00 PM PDT 24	Mar 14 01:29:01 PM PDT 24	2755734426 ps
T54	/workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.850942387	Mar 14 01:28:16 PM PDT 24	Mar 14 01:28:19 PM PDT 24	2621098123 ps
T27	/workspace/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.3969245450	Mar 14 01:28:55 PM PDT 24	Mar 14 01:29:26 PM PDT 24	43964282842 ps
T38	/workspace/coverage/default/4.sysrst_ctrl_edge_detect.2082494504	Mar 14 01:27:55 PM PDT 24	Mar 14 01:31:04 PM PDT 24	275700343925 ps
T77	/workspace/coverage/default/0.sysrst_ctrl_alert_test.1660637806	Mar 14 01:27:48 PM PDT 24	Mar 14 01:27:51 PM PDT 24	2029349880 ps
T113	/workspace/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.1591562182	Mar 14 01:29:16 PM PDT 24	Mar 14 01:29:23 PM PDT 24	2612039025 ps
T74	/workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.3930913294	Mar 14 01:30:02 PM PDT 24	Mar 14 01:30:30 PM PDT 24	42989471122 ps
T190	/workspace/coverage/default/14.sysrst_ctrl_pin_access_test.3125485887	Mar 14 01:28:21 PM PDT 24	Mar 14 01:28:27 PM PDT 24	2137902894 ps
T191	/workspace/coverage/default/25.sysrst_ctrl_smoke.2321142898	Mar 14 01:28:54 PM PDT 24	Mar 14 01:29:00 PM PDT 24	2110047327 ps
T49	/workspace/coverage/default/30.sysrst_ctrl_auto_blk_key_output.3237938050	Mar 14 01:29:10 PM PDT 24	Mar 14 01:29:17 PM PDT 24	3436291543 ps
T65	/workspace/coverage/default/4.sysrst_ctrl_stress_all.1809178560	Mar 14 01:28:03 PM PDT 24	Mar 14 01:28:17 PM PDT 24	9586592767 ps
T39	/workspace/coverage/default/8.sysrst_ctrl_edge_detect.3750374192	Mar 14 01:28:09 PM PDT 24	Mar 14 01:28:17 PM PDT 24	4189017473 ps
T397	/workspace/coverage/default/49.sysrst_ctrl_smoke.127362470	Mar 14 01:29:50 PM PDT 24	Mar 14 01:29:52 PM PDT 24	2138638765 ps
T41	/workspace/coverage/default/30.sysrst_ctrl_edge_detect.15560598	Mar 14 01:29:07 PM PDT 24	Mar 14 01:29:09 PM PDT 24	3249416835 ps
T398	/workspace/coverage/default/21.sysrst_ctrl_pin_access_test.3124687809	Mar 14 01:28:44 PM PDT 24	Mar 14 01:28:46 PM PDT 24	2172056026 ps
T50	/workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.348419688	Mar 14 01:29:58 PM PDT 24	Mar 14 01:30:01 PM PDT 24	3298069458 ps
T399	/workspace/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.4237937755	Mar 14 01:28:24 PM PDT 24	Mar 14 01:28:31 PM PDT 24	2610929766 ps
T396	/workspace/coverage/default/18.sysrst_ctrl_pin_override_test.2572908030	Mar 14 01:28:34 PM PDT 24	Mar 14 01:28:42 PM PDT 24	2511110094 ps
T89	/workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.627426077	Mar 14 01:30:03 PM PDT 24	Mar 14 01:31:10 PM PDT 24	26828088710 ps
T400	/workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.362569307	Mar 14 01:30:04 PM PDT 24	Mar 14 01:30:08 PM PDT 24	4311533154 ps
T40	/workspace/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.1422323977	Mar 14 01:29:16 PM PDT 24	Mar 14 01:32:59 PM PDT 24	148295537085 ps
T229	/workspace/coverage/default/17.sysrst_ctrl_pin_override_test.1913619928	Mar 14 01:28:34 PM PDT 24	Mar 14 01:28:37 PM PDT 24	2541603839 ps
T230	/workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.2895954514	Mar 14 01:29:58 PM PDT 24	Mar 14 01:30:01 PM PDT 24	2468601481 ps
T78	/workspace/coverage/default/40.sysrst_ctrl_stress_all.613663161	Mar 14 01:29:39 PM PDT 24	Mar 14 01:30:35 PM PDT 24	88342224527 ps
T104	/workspace/coverage/default/20.sysrst_ctrl_stress_all.471546401	Mar 14 01:28:48 PM PDT 24	Mar 14 01:29:00 PM PDT 24	6631020169 ps
T105	/workspace/coverage/default/26.sysrst_ctrl_smoke.32226315	Mar 14 01:28:57 PM PDT 24	Mar 14 01:29:03 PM PDT 24	2111234911 ps
T56	/workspace/coverage/default/35.sysrst_ctrl_ultra_low_pwr.3789698537	Mar 14 01:29:22 PM PDT 24	Mar 14 01:29:29 PM PDT 24	3727144414 ps
T106	/workspace/coverage/default/8.sysrst_ctrl_stress_all.1538265427	Mar 14 01:28:07 PM PDT 24	Mar 14 01:28:19 PM PDT 24	14102370254 ps
T57	/workspace/coverage/default/12.sysrst_ctrl_ultra_low_pwr.2174979356	Mar 14 01:28:22 PM PDT 24	Mar 14 01:28:24 PM PDT 24	3731600129 ps
T107	/workspace/coverage/default/15.sysrst_ctrl_pin_access_test.3478766832	Mar 14 01:28:38 PM PDT 24	Mar 14 01:28:45 PM PDT 24	2034882203 ps
T108	/workspace/coverage/default/31.sysrst_ctrl_smoke.2940214899	Mar 14 01:29:10 PM PDT 24	Mar 14 01:29:14 PM PDT 24	2113938388 ps
T82	/workspace/coverage/default/33.sysrst_ctrl_auto_blk_key_output.3073402781	Mar 14 01:29:11 PM PDT 24	Mar 14 01:29:15 PM PDT 24	3821554442 ps
T90	/workspace/coverage/default/36.sysrst_ctrl_combo_detect.870564916	Mar 14 01:29:20 PM PDT 24	Mar 14 01:30:46 PM PDT 24	129209255446 ps
T295	/workspace/coverage/default/6.sysrst_ctrl_stress_all.1278631280	Mar 14 01:28:06 PM PDT 24	Mar 14 01:28:17 PM PDT 24	8165595669 ps
T401	/workspace/coverage/default/49.sysrst_ctrl_alert_test.3380839570	Mar 14 01:30:06 PM PDT 24	Mar 14 01:30:12 PM PDT 24	2012949214 ps
T402	/workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.2123392815	Mar 14 01:28:15 PM PDT 24	Mar 14 01:28:41 PM PDT 24	37865788125 ps
T83	/workspace/coverage/default/13.sysrst_ctrl_stress_all.3529713378	Mar 14 01:28:23 PM PDT 24	Mar 14 01:34:43 PM PDT 24	139766273072 ps
T403	/workspace/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.2274182584	Mar 14 01:28:34 PM PDT 24	Mar 14 01:28:37 PM PDT 24	2690580855 ps
T404	/workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.863932238	Mar 14 01:29:52 PM PDT 24	Mar 14 01:29:59 PM PDT 24	2611650962 ps
T251	/workspace/coverage/default/41.sysrst_ctrl_combo_detect.651471727	Mar 14 01:29:36 PM PDT 24	Mar 14 01:29:57 PM PDT 24	121646925394 ps
T296	/workspace/coverage/default/15.sysrst_ctrl_auto_blk_key_output.2915598777	Mar 14 01:28:35 PM PDT 24	Mar 14 01:28:37 PM PDT 24	3330535985 ps
T405	/workspace/coverage/default/16.sysrst_ctrl_auto_blk_key_output.3949865967	Mar 14 01:28:36 PM PDT 24	Mar 14 01:28:54 PM PDT 24	22943646773 ps
T406	/workspace/coverage/default/4.sysrst_ctrl_auto_blk_key_output.2238277126	Mar 14 01:28:06 PM PDT 24	Mar 14 01:28:09 PM PDT 24	3973034617 ps
T248	/workspace/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.3155760289	Mar 14 01:28:44 PM PDT 24	Mar 14 01:32:31 PM PDT 24	97573514841 ps
T407	/workspace/coverage/default/28.sysrst_ctrl_in_out_inverted.1593162142	Mar 14 01:28:57 PM PDT 24	Mar 14 01:29:01 PM PDT 24	2462263136 ps
T159	/workspace/coverage/default/28.sysrst_ctrl_edge_detect.1754380046	Mar 14 01:28:59 PM PDT 24	Mar 14 01:29:09 PM PDT 24	4964749821 ps
T408	/workspace/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.2089415999	Mar 14 01:28:39 PM PDT 24	Mar 14 01:28:42 PM PDT 24	2622720130 ps
T91	/workspace/coverage/default/16.sysrst_ctrl_stress_all.1262632030	Mar 14 01:28:35 PM PDT 24	Mar 14 01:28:46 PM PDT 24	23870003558 ps
T300	/workspace/coverage/default/34.sysrst_ctrl_combo_detect.1056736284	Mar 14 01:29:21 PM PDT 24	Mar 14 01:31:36 PM PDT 24	108236383826 ps
T334	/workspace/coverage/default/5.sysrst_ctrl_pin_override_test.2423913127	Mar 14 01:28:07 PM PDT 24	Mar 14 01:28:09 PM PDT 24	2561681917 ps
T92	/workspace/coverage/default/15.sysrst_ctrl_combo_detect.1507883945	Mar 14 01:28:37 PM PDT 24	Mar 14 01:29:09 PM PDT 24	45319017764 ps
T409	/workspace/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.112713352	Mar 14 01:28:06 PM PDT 24	Mar 14 01:28:14 PM PDT 24	2728396794 ps
T249	/workspace/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.2520655862	Mar 14 01:29:38 PM PDT 24	Mar 14 01:31:29 PM PDT 24	78666457763 ps
T410	/workspace/coverage/default/9.sysrst_ctrl_pin_access_test.968493819	Mar 14 01:28:16 PM PDT 24	Mar 14 01:28:22 PM PDT 24	2228921848 ps
T411	/workspace/coverage/default/17.sysrst_ctrl_alert_test.2134906275	Mar 14 01:28:38 PM PDT 24	Mar 14 01:28:41 PM PDT 24	2044801504 ps
T412	/workspace/coverage/default/13.sysrst_ctrl_smoke.494420940	Mar 14 01:28:22 PM PDT 24	Mar 14 01:28:28 PM PDT 24	2111267411 ps
T160	/workspace/coverage/default/16.sysrst_ctrl_edge_detect.1935689070	Mar 14 01:28:39 PM PDT 24	Mar 14 01:28:42 PM PDT 24	3200758461 ps
T212	/workspace/coverage/default/26.sysrst_ctrl_pin_override_test.3467414845	Mar 14 01:28:57 PM PDT 24	Mar 14 01:29:00 PM PDT 24	2522169520 ps
T213	/workspace/coverage/default/44.sysrst_ctrl_alert_test.3373612949	Mar 14 01:29:51 PM PDT 24	Mar 14 01:29:54 PM PDT 24	2015858012 ps
T93	/workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.2881195962	Mar 14 01:29:58 PM PDT 24	Mar 14 01:30:59 PM PDT 24	22579346178 ps
T214	/workspace/coverage/default/23.sysrst_ctrl_in_out_inverted.798223688	Mar 14 01:28:47 PM PDT 24	Mar 14 01:28:55 PM PDT 24	2454539541 ps
T215	/workspace/coverage/default/36.sysrst_ctrl_pin_access_test.2684457391	Mar 14 01:29:20 PM PDT 24	Mar 14 01:29:21 PM PDT 24	2175164895 ps
T216	/workspace/coverage/default/36.sysrst_ctrl_alert_test.950323121	Mar 14 01:29:22 PM PDT 24	Mar 14 01:29:28 PM PDT 24	2015384228 ps
T217	/workspace/coverage/default/35.sysrst_ctrl_combo_detect.469000408	Mar 14 01:29:21 PM PDT 24	Mar 14 01:37:20 PM PDT 24	174003476832 ps
T58	/workspace/coverage/default/39.sysrst_ctrl_ultra_low_pwr.2674314914	Mar 14 01:29:37 PM PDT 24	Mar 14 01:29:39 PM PDT 24	6483217087 ps
T126	/workspace/coverage/default/25.sysrst_ctrl_edge_detect.3019271100	Mar 14 01:28:59 PM PDT 24	Mar 14 01:29:07 PM PDT 24	4901302923 ps
T127	/workspace/coverage/default/25.sysrst_ctrl_in_out_inverted.1670509866	Mar 14 01:28:56 PM PDT 24	Mar 14 01:29:01 PM PDT 24	2441240261 ps
T128	/workspace/coverage/default/47.sysrst_ctrl_combo_detect.1468503085	Mar 14 01:29:58 PM PDT 24	Mar 14 01:30:22 PM PDT 24	58496163246 ps
T59	/workspace/coverage/default/15.sysrst_ctrl_ultra_low_pwr.2416654726	Mar 14 01:28:38 PM PDT 24	Mar 14 01:28:43 PM PDT 24	13407542751 ps
T129	/workspace/coverage/default/4.sysrst_ctrl_pin_access_test.3383387957	Mar 14 01:28:08 PM PDT 24	Mar 14 01:28:12 PM PDT 24	2169980928 ps
T130	/workspace/coverage/default/29.sysrst_ctrl_in_out_inverted.1525155271	Mar 14 01:29:01 PM PDT 24	Mar 14 01:29:08 PM PDT 24	2454412045 ps
T131	/workspace/coverage/default/44.sysrst_ctrl_stress_all.3079571175	Mar 14 01:29:55 PM PDT 24	Mar 14 01:30:38 PM PDT 24	60080995915 ps
T94	/workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.2042768695	Mar 14 01:30:03 PM PDT 24	Mar 14 01:32:56 PM PDT 24	85224609953 ps
T132	/workspace/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.1597465062	Mar 14 01:27:55 PM PDT 24	Mar 14 01:30:34 PM PDT 24	60255603765 ps
T413	/workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.4124145437	Mar 14 01:29:39 PM PDT 24	Mar 14 01:29:42 PM PDT 24	3105841954 ps
T161	/workspace/coverage/default/21.sysrst_ctrl_edge_detect.1743599967	Mar 14 01:28:47 PM PDT 24	Mar 14 01:35:42 PM PDT 24	610949639953 ps
T114	/workspace/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.935730691	Mar 14 01:28:45 PM PDT 24	Mar 14 01:30:47 PM PDT 24	45256404204 ps
T414	/workspace/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.3577803244	Mar 14 01:29:24 PM PDT 24	Mar 14 01:29:27 PM PDT 24	2626512914 ps
T415	/workspace/coverage/default/3.sysrst_ctrl_pin_access_test.1413569139	Mar 14 01:27:46 PM PDT 24	Mar 14 01:27:52 PM PDT 24	2151004788 ps
T250	/workspace/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.2593376390	Mar 14 01:27:52 PM PDT 24	Mar 14 01:28:52 PM PDT 24	90862810915 ps
T416	/workspace/coverage/default/31.sysrst_ctrl_in_out_inverted.2492690267	Mar 14 01:29:07 PM PDT 24	Mar 14 01:29:10 PM PDT 24	2502139341 ps
T80	/workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.4290993003	Mar 14 01:28:04 PM PDT 24	Mar 14 01:31:41 PM PDT 24	78351598023 ps
T95	/workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.1625226024	Mar 14 01:30:00 PM PDT 24	Mar 14 01:30:16 PM PDT 24	25358472014 ps
T146	/workspace/coverage/default/14.sysrst_ctrl_edge_detect.674874453	Mar 14 01:28:22 PM PDT 24	Mar 14 01:33:50 PM PDT 24	1005317558290 ps
T417	/workspace/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.1780181438	Mar 14 01:29:25 PM PDT 24	Mar 14 01:29:32 PM PDT 24	2610793316 ps
T205	/workspace/coverage/default/10.sysrst_ctrl_edge_detect.567362003	Mar 14 01:28:20 PM PDT 24	Mar 14 01:28:22 PM PDT 24	2580510503 ps
T241	/workspace/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.3386284391	Mar 14 01:28:23 PM PDT 24	Mar 14 01:28:43 PM PDT 24	29110357658 ps
T418	/workspace/coverage/default/34.sysrst_ctrl_auto_blk_key_output.2134151036	Mar 14 01:29:20 PM PDT 24	Mar 14 01:29:27 PM PDT 24	3314831111 ps
T419	/workspace/coverage/default/15.sysrst_ctrl_smoke.974307504	Mar 14 01:28:23 PM PDT 24	Mar 14 01:28:29 PM PDT 24	2111860800 ps
T420	/workspace/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.1915819566	Mar 14 01:29:09 PM PDT 24	Mar 14 01:29:16 PM PDT 24	3543813731 ps
T421	/workspace/coverage/default/19.sysrst_ctrl_pin_access_test.1731284284	Mar 14 01:28:37 PM PDT 24	Mar 14 01:28:44 PM PDT 24	2079447928 ps
T422	/workspace/coverage/default/27.sysrst_ctrl_pin_override_test.905917972	Mar 14 01:29:00 PM PDT 24	Mar 14 01:29:06 PM PDT 24	2512596570 ps
T423	/workspace/coverage/default/33.sysrst_ctrl_smoke.2272881200	Mar 14 01:29:09 PM PDT 24	Mar 14 01:29:12 PM PDT 24	2123320407 ps
T424	/workspace/coverage/default/14.sysrst_ctrl_smoke.3710353596	Mar 14 01:28:21 PM PDT 24	Mar 14 01:28:23 PM PDT 24	2124785824 ps
T60	/workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.989107177	Mar 14 01:28:04 PM PDT 24	Mar 14 01:29:43 PM PDT 24	206668846660 ps
T425	/workspace/coverage/default/11.sysrst_ctrl_stress_all.3620658700	Mar 14 01:28:20 PM PDT 24	Mar 14 01:28:24 PM PDT 24	8603314801 ps
T75	/workspace/coverage/default/1.sysrst_ctrl_feature_disable.3383521960	Mar 14 01:27:54 PM PDT 24	Mar 14 01:28:21 PM PDT 24	39015794382 ps
T324	/workspace/coverage/default/33.sysrst_ctrl_pin_access_test.630446873	Mar 14 01:29:11 PM PDT 24	Mar 14 01:29:17 PM PDT 24	2112619552 ps
T325	/workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.2888387743	Mar 14 01:29:51 PM PDT 24	Mar 14 01:29:52 PM PDT 24	6897040776 ps
T326	/workspace/coverage/default/30.sysrst_ctrl_pin_override_test.853811143	Mar 14 01:29:06 PM PDT 24	Mar 14 01:29:08 PM PDT 24	2617806403 ps
T297	/workspace/coverage/default/0.sysrst_ctrl_auto_blk_key_output.2908432184	Mar 14 01:27:52 PM PDT 24	Mar 14 01:28:01 PM PDT 24	3161910257 ps
T327	/workspace/coverage/default/28.sysrst_ctrl_pin_access_test.2345073278	Mar 14 01:28:58 PM PDT 24	Mar 14 01:29:05 PM PDT 24	2096724136 ps
T242	/workspace/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.4055410660	Mar 14 01:28:33 PM PDT 24	Mar 14 01:29:31 PM PDT 24	37106418114 ps
T328	/workspace/coverage/default/0.sysrst_ctrl_in_out_inverted.2515070107	Mar 14 01:27:51 PM PDT 24	Mar 14 01:27:55 PM PDT 24	2467748734 ps
T329	/workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.3065662191	Mar 14 01:29:38 PM PDT 24	Mar 14 01:29:40 PM PDT 24	2457473229 ps
T330	/workspace/coverage/default/26.sysrst_ctrl_alert_test.1808849152	Mar 14 01:28:57 PM PDT 24	Mar 14 01:28:58 PM PDT 24	2055218257 ps
T243	/workspace/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.994251694	Mar 14 01:29:37 PM PDT 24	Mar 14 01:34:12 PM PDT 24	99175278344 ps
T76	/workspace/coverage/default/38.sysrst_ctrl_ultra_low_pwr.2581781940	Mar 14 01:29:36 PM PDT 24	Mar 14 01:29:44 PM PDT 24	5601341996 ps
T192	/workspace/coverage/default/49.sysrst_ctrl_edge_detect.2580042608	Mar 14 01:30:02 PM PDT 24	Mar 14 01:30:09 PM PDT 24	2689538816 ps
T426	/workspace/coverage/default/24.sysrst_ctrl_ultra_low_pwr.1111522936	Mar 14 01:28:55 PM PDT 24	Mar 14 01:28:59 PM PDT 24	2378649398 ps
T335	/workspace/coverage/default/4.sysrst_ctrl_ultra_low_pwr.2043223556	Mar 14 01:28:09 PM PDT 24	Mar 14 01:28:11 PM PDT 24	9402722317 ps
T371	/workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.3433502045	Mar 14 01:30:03 PM PDT 24	Mar 14 01:31:57 PM PDT 24	90834096947 ps
T193	/workspace/coverage/default/27.sysrst_ctrl_stress_all.2611190277	Mar 14 01:28:59 PM PDT 24	Mar 14 01:31:51 PM PDT 24	247501815097 ps
T268	/workspace/coverage/default/4.sysrst_ctrl_sec_cm.3341651131	Mar 14 01:28:07 PM PDT 24	Mar 14 01:29:01 PM PDT 24	22070410294 ps
T286	/workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.1618458959	Mar 14 01:30:14 PM PDT 24	Mar 14 01:31:19 PM PDT 24	101180737789 ps
T287	/workspace/coverage/default/1.sysrst_ctrl_in_out_inverted.702303121	Mar 14 01:27:55 PM PDT 24	Mar 14 01:28:05 PM PDT 24	2454084120 ps
T288	/workspace/coverage/default/41.sysrst_ctrl_smoke.1923318884	Mar 14 01:29:37 PM PDT 24	Mar 14 01:29:43 PM PDT 24	2107778637 ps
T289	/workspace/coverage/default/18.sysrst_ctrl_alert_test.3768086938	Mar 14 01:28:41 PM PDT 24	Mar 14 01:28:44 PM PDT 24	2026140333 ps
T290	/workspace/coverage/default/32.sysrst_ctrl_pin_override_test.2863867703	Mar 14 01:29:13 PM PDT 24	Mar 14 01:29:21 PM PDT 24	2511215435 ps
T291	/workspace/coverage/default/36.sysrst_ctrl_stress_all.2106473858	Mar 14 01:29:22 PM PDT 24	Mar 14 01:31:16 PM PDT 24	172432657415 ps
T292	/workspace/coverage/default/39.sysrst_ctrl_pin_access_test.2316649172	Mar 14 01:29:39 PM PDT 24	Mar 14 01:29:45 PM PDT 24	2206686756 ps
T293	/workspace/coverage/default/13.sysrst_ctrl_in_out_inverted.1476496572	Mar 14 01:28:23 PM PDT 24	Mar 14 01:28:26 PM PDT 24	2462835283 ps
T294	/workspace/coverage/default/34.sysrst_ctrl_in_out_inverted.688465428	Mar 14 01:29:13 PM PDT 24	Mar 14 01:29:20 PM PDT 24	2455000189 ps
T133	/workspace/coverage/default/18.sysrst_ctrl_edge_detect.3740969944	Mar 14 01:28:38 PM PDT 24	Mar 14 01:28:42 PM PDT 24	3267281594 ps
T427	/workspace/coverage/default/33.sysrst_ctrl_pin_override_test.3351998772	Mar 14 01:29:09 PM PDT 24	Mar 14 01:29:12 PM PDT 24	2549348920 ps
T109	/workspace/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.2541080591	Mar 14 01:28:23 PM PDT 24	Mar 14 01:29:32 PM PDT 24	109123052498 ps
T316	/workspace/coverage/default/12.sysrst_ctrl_pin_override_test.3609109547	Mar 14 01:28:29 PM PDT 24	Mar 14 01:28:32 PM PDT 24	2523459975 ps
T317	/workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.4278299826	Mar 14 01:28:06 PM PDT 24	Mar 14 01:28:09 PM PDT 24	2626866757 ps
T318	/workspace/coverage/default/43.sysrst_ctrl_alert_test.1724603912	Mar 14 01:29:53 PM PDT 24	Mar 14 01:29:59 PM PDT 24	2013830443 ps
T319	/workspace/coverage/default/39.sysrst_ctrl_alert_test.3629184614	Mar 14 01:29:39 PM PDT 24	Mar 14 01:29:41 PM PDT 24	2032355375 ps
T320	/workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.1629854629	Mar 14 01:30:09 PM PDT 24	Mar 14 01:31:47 PM PDT 24	75922506695 ps
T321	/workspace/coverage/default/10.sysrst_ctrl_pin_access_test.3895695234	Mar 14 01:28:19 PM PDT 24	Mar 14 01:28:22 PM PDT 24	2189309018 ps
T231	/workspace/coverage/default/29.sysrst_ctrl_stress_all.1298261851	Mar 14 01:29:07 PM PDT 24	Mar 14 01:29:51 PM PDT 24	15877767096 ps
T322	/workspace/coverage/default/29.sysrst_ctrl_pin_access_test.2832316978	Mar 14 01:29:01 PM PDT 24	Mar 14 01:29:06 PM PDT 24	2048223432 ps
T175	/workspace/coverage/default/37.sysrst_ctrl_edge_detect.2583339192	Mar 14 01:29:26 PM PDT 24	Mar 14 01:29:34 PM PDT 24	2567588106 ps
T110	/workspace/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.1230256556	Mar 14 01:29:14 PM PDT 24	Mar 14 01:30:26 PM PDT 24	108181863676 ps
T428	/workspace/coverage/default/42.sysrst_ctrl_smoke.2400600788	Mar 14 01:29:40 PM PDT 24	Mar 14 01:29:47 PM PDT 24	2109238261 ps
T135	/workspace/coverage/default/41.sysrst_ctrl_edge_detect.4022663948	Mar 14 01:29:43 PM PDT 24	Mar 14 01:29:57 PM PDT 24	4805617081 ps
T429	/workspace/coverage/default/3.sysrst_ctrl_pin_override_test.3598085419	Mar 14 01:27:53 PM PDT 24	Mar 14 01:27:58 PM PDT 24	2518753735 ps
T430	/workspace/coverage/default/4.sysrst_ctrl_in_out_inverted.1062188477	Mar 14 01:28:05 PM PDT 24	Mar 14 01:28:07 PM PDT 24	2491407008 ps
T206	/workspace/coverage/default/2.sysrst_ctrl_edge_detect.1679481278	Mar 14 01:27:49 PM PDT 24	Mar 14 01:27:53 PM PDT 24	3095517194 ps
T331	/workspace/coverage/default/15.sysrst_ctrl_in_out_inverted.646465048	Mar 14 01:28:25 PM PDT 24	Mar 14 01:28:33 PM PDT 24	2450349024 ps
T431	/workspace/coverage/default/17.sysrst_ctrl_stress_all.4282292400	Mar 14 01:28:36 PM PDT 24	Mar 14 01:29:13 PM PDT 24	13057207129 ps
T432	/workspace/coverage/default/43.sysrst_ctrl_stress_all.810780857	Mar 14 01:29:57 PM PDT 24	Mar 14 01:30:02 PM PDT 24	6694008523 ps
T359	/workspace/coverage/default/6.sysrst_ctrl_combo_detect.2965194962	Mar 14 01:28:06 PM PDT 24	Mar 14 01:29:35 PM PDT 24	64968315774 ps
T433	/workspace/coverage/default/21.sysrst_ctrl_ultra_low_pwr.1443292062	Mar 14 01:28:46 PM PDT 24	Mar 14 01:28:51 PM PDT 24	3302399123 ps
T434	/workspace/coverage/default/48.sysrst_ctrl_alert_test.2637131306	Mar 14 01:29:58 PM PDT 24	Mar 14 01:30:01 PM PDT 24	2019098329 ps
T111	/workspace/coverage/default/0.sysrst_ctrl_ultra_low_pwr.2133054799	Mar 14 01:27:52 PM PDT 24	Mar 14 01:27:57 PM PDT 24	2863357306 ps
T112	/workspace/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.1522871294	Mar 14 01:29:23 PM PDT 24	Mar 14 01:30:08 PM PDT 24	71339726476 ps
T96	/workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.3781880497	Mar 14 01:28:06 PM PDT 24	Mar 14 01:29:40 PM PDT 24	130221616911 ps
T177	/workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.1066763136	Mar 14 01:30:02 PM PDT 24	Mar 14 01:31:36 PM PDT 24	107991454548 ps
T178	/workspace/coverage/default/6.sysrst_ctrl_smoke.179092314	Mar 14 01:28:09 PM PDT 24	Mar 14 01:28:14 PM PDT 24	2114823344 ps
T179	/workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3131905083	Mar 14 01:27:53 PM PDT 24	Mar 14 01:27:56 PM PDT 24	2528698506 ps
T136	/workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.2561341788	Mar 14 01:29:50 PM PDT 24	Mar 14 01:38:21 PM PDT 24	189124853956 ps
T180	/workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.535769349	Mar 14 01:30:05 PM PDT 24	Mar 14 01:31:19 PM PDT 24	104483296410 ps
T181	/workspace/coverage/default/31.sysrst_ctrl_auto_blk_key_output.3284055473	Mar 14 01:29:08 PM PDT 24	Mar 14 01:29:11 PM PDT 24	3140589943 ps
T182	/workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.2333539180	Mar 14 01:29:54 PM PDT 24	Mar 14 01:30:02 PM PDT 24	2552529043 ps
T183	/workspace/coverage/default/7.sysrst_ctrl_pin_access_test.4176712766	Mar 14 01:28:07 PM PDT 24	Mar 14 01:28:09 PM PDT 24	2208775542 ps
T435	/workspace/coverage/default/3.sysrst_ctrl_alert_test.1721114835	Mar 14 01:28:04 PM PDT 24	Mar 14 01:28:06 PM PDT 24	2040443144 ps
T436	/workspace/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.571617686	Mar 14 01:29:00 PM PDT 24	Mar 14 01:29:23 PM PDT 24	16478940765 ps
T437	/workspace/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.1540351255	Mar 14 01:28:20 PM PDT 24	Mar 14 01:28:31 PM PDT 24	3710462330 ps
T438	/workspace/coverage/default/37.sysrst_ctrl_pin_override_test.291142994	Mar 14 01:29:23 PM PDT 24	Mar 14 01:29:25 PM PDT 24	2588865904 ps
T439	/workspace/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.2835426052	Mar 14 01:29:39 PM PDT 24	Mar 14 01:29:46 PM PDT 24	2614074478 ps
T440	/workspace/coverage/default/24.sysrst_ctrl_pin_override_test.1865697991	Mar 14 01:28:50 PM PDT 24	Mar 14 01:28:52 PM PDT 24	2545654467 ps
T441	/workspace/coverage/default/18.sysrst_ctrl_stress_all.2538222455	Mar 14 01:28:34 PM PDT 24	Mar 14 01:28:58 PM PDT 24	11080459321 ps
T442	/workspace/coverage/default/19.sysrst_ctrl_smoke.2765679868	Mar 14 01:28:36 PM PDT 24	Mar 14 01:28:42 PM PDT 24	2111243098 ps
T176	/workspace/coverage/default/34.sysrst_ctrl_edge_detect.564866994	Mar 14 01:29:19 PM PDT 24	Mar 14 01:29:23 PM PDT 24	4407273554 ps
T187	/workspace/coverage/default/9.sysrst_ctrl_edge_detect.1518778704	Mar 14 01:28:19 PM PDT 24	Mar 14 01:28:26 PM PDT 24	3210162905 ps
T443	/workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.2862934583	Mar 14 01:29:38 PM PDT 24	Mar 14 01:29:40 PM PDT 24	2668598767 ps
T444	/workspace/coverage/default/37.sysrst_ctrl_auto_blk_key_output.2208585884	Mar 14 01:29:28 PM PDT 24	Mar 14 01:29:31 PM PDT 24	3307985018 ps
T445	/workspace/coverage/default/45.sysrst_ctrl_smoke.4060623688	Mar 14 01:29:50 PM PDT 24	Mar 14 01:29:54 PM PDT 24	2111365753 ps
T446	/workspace/coverage/default/9.sysrst_ctrl_pin_override_test.2120099756	Mar 14 01:28:16 PM PDT 24	Mar 14 01:28:19 PM PDT 24	2530315364 ps
T447	/workspace/coverage/default/48.sysrst_ctrl_pin_override_test.4142749602	Mar 14 01:29:58 PM PDT 24	Mar 14 01:30:00 PM PDT 24	2553984062 ps
T448	/workspace/coverage/default/35.sysrst_ctrl_smoke.2054820569	Mar 14 01:29:21 PM PDT 24	Mar 14 01:29:23 PM PDT 24	2133040773 ps
T449	/workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.1366219179	Mar 14 01:27:52 PM PDT 24	Mar 14 01:27:53 PM PDT 24	2291291844 ps
T450	/workspace/coverage/default/14.sysrst_ctrl_auto_blk_key_output.4216721609	Mar 14 01:28:23 PM PDT 24	Mar 14 01:28:32 PM PDT 24	3073779180 ps
T451	/workspace/coverage/default/0.sysrst_ctrl_pin_access_test.1481626285	Mar 14 01:27:48 PM PDT 24	Mar 14 01:27:50 PM PDT 24	2098323459 ps
T452	/workspace/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.940742554	Mar 14 01:28:35 PM PDT 24	Mar 14 01:28:39 PM PDT 24	2619676658 ps
T453	/workspace/coverage/default/47.sysrst_ctrl_pin_override_test.1618996360	Mar 14 01:29:55 PM PDT 24	Mar 14 01:29:57 PM PDT 24	2521714616 ps
T454	/workspace/coverage/default/23.sysrst_ctrl_smoke.4080085401	Mar 14 01:28:45 PM PDT 24	Mar 14 01:28:49 PM PDT 24	2118312040 ps
T455	/workspace/coverage/default/28.sysrst_ctrl_auto_blk_key_output.1492599007	Mar 14 01:28:57 PM PDT 24	Mar 14 01:29:05 PM PDT 24	3309844947 ps
T134	/workspace/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.184902388	Mar 14 01:28:38 PM PDT 24	Mar 14 01:29:20 PM PDT 24	66536519366 ps