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Summary for Variable cp_z3_wakeup

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_z3_wakeup

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 120 1 T11 13 T33 8 T40 5
auto[1] 100 1 T11 7 T33 12 T40 15


Summary for Cross key0_inXval

Samples crossed: cp_key0_in cfg.vif.key0_in
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for key0_inXval

Bins
cp_key0_incfg.vif.key0_inCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 49 1 T11 5 T33 8 T40 6
auto[0] auto[1] 51 1 T11 3 T33 3 T40 3
auto[1] auto[0] 62 1 T11 5 T33 3 T40 9
auto[1] auto[1] 58 1 T11 7 T33 6 T40 2


Summary for Cross key0_outXval

Samples crossed: cp_key0_out cfg.vif.key0_out
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for key0_outXval

Bins
cp_key0_outcfg.vif.key0_outCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 48 1 T11 8 T33 6 T40 3
auto[0] auto[1] 58 1 T11 5 T33 4 T40 4
auto[1] auto[0] 55 1 T11 3 T33 2 T40 8
auto[1] auto[1] 59 1 T11 4 T33 8 T40 5


Summary for Cross key1_inXval

Samples crossed: cp_key1_in cfg.vif.key1_in
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for key1_inXval

Bins
cp_key1_incfg.vif.key1_inCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 49 1 T11 3 T33 6 T40 4
auto[0] auto[1] 53 1 T11 5 T33 4 T40 5
auto[1] auto[0] 61 1 T11 6 T33 5 T40 4
auto[1] auto[1] 57 1 T11 6 T33 5 T40 7


Summary for Cross key1_outXval

Samples crossed: cp_key1_out cfg.vif.key1_out
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for key1_outXval

Bins
cp_key1_outcfg.vif.key1_outCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 61 1 T11 5 T33 8 T40 5
auto[0] auto[1] 53 1 T11 6 T33 5 T40 4
auto[1] auto[0] 61 1 T11 5 T33 4 T40 5
auto[1] auto[1] 45 1 T11 4 T33 3 T40 6


Summary for Cross key2_inXval

Samples crossed: cp_key2_in cfg.vif.key2_in
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for key2_inXval

Bins
cp_key2_incfg.vif.key2_inCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 66 1 T11 8 T33 8 T40 6
auto[0] auto[1] 56 1 T11 4 T33 4 T40 6
auto[1] auto[0] 50 1 T11 7 T33 5 T40 5
auto[1] auto[1] 48 1 T11 1 T33 3 T40 3


Summary for Cross key2_outXval

Samples crossed: cp_key2_out cfg.vif.key2_out
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for key2_outXval

Bins
cp_key2_outcfg.vif.key2_outCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 57 1 T11 8 T33 4 T40 4
auto[0] auto[1] 50 1 T11 7 T33 1 T40 4
auto[1] auto[0] 56 1 T11 4 T33 8 T40 7
auto[1] auto[1] 57 1 T11 1 T33 7 T40 5


Summary for Cross pwrb_inXval

Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for pwrb_inXval

Bins
cp_pwrb_incfg.vif.pwrb_inCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 59 1 T11 6 T33 5 T40 5
auto[0] auto[1] 55 1 T11 6 T33 5 T40 7
auto[1] auto[0] 58 1 T11 3 T33 10 T40 3
auto[1] auto[1] 48 1 T11 5 T40 5 T267 3


Summary for Cross pwrb_outXval

Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for pwrb_outXval

Bins
cp_pwrb_outcfg.vif.pwrb_outCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 47 1 T11 5 T33 1 T40 4
auto[0] auto[1] 58 1 T11 4 T33 8 T40 7
auto[1] auto[0] 55 1 T11 5 T33 7 T40 3
auto[1] auto[1] 60 1 T11 6 T33 4 T40 6


Summary for Cross ac_presentXval

Samples crossed: cp_ac_present cfg.vif.ac_present
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for ac_presentXval

Bins
cp_ac_presentcfg.vif.ac_presentCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 53 1 T11 1 T33 7 T40 4
auto[0] auto[1] 55 1 T11 5 T33 2 T40 7
auto[1] auto[0] 69 1 T11 8 T33 9 T40 4
auto[1] auto[1] 43 1 T11 6 T33 2 T40 5


Summary for Cross bat_disableXval

Samples crossed: cp_bat_disable cfg.vif.bat_disable
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 2 0 2 100.00
Automatically Generated Cross Bins 2 0 2 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for bat_disableXval

Bins
cp_bat_disablecfg.vif.bat_disableCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 102 1 T11 10 T33 11 T40 10
auto[1] auto[1] 118 1 T11 10 T33 9 T40 10


User Defined Cross Bins for bat_disableXval

Excluded/Illegal bins
NAMECOUNTSTATUS
invalid0 0 Excluded
invalid1 0 Excluded


Summary for Cross lid_openXval

Samples crossed: cp_lid_open cfg.vif.lid_open
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for lid_openXval

Bins
cp_lid_opencfg.vif.lid_openCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 62 1 T11 8 T33 3 T40 4
auto[0] auto[1] 45 1 T11 2 T33 5 T40 6
auto[1] auto[0] 63 1 T11 4 T33 5 T40 6
auto[1] auto[1] 50 1 T11 6 T33 7 T40 4


Summary for Cross z3_wakeupXval

Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 2 0 2 100.00
Automatically Generated Cross Bins 2 0 2 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for z3_wakeupXval

Bins
cp_z3_wakeupcfg.vif.z3_wakeupCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 120 1 T11 13 T33 8 T40 5
auto[1] auto[1] 100 1 T11 7 T33 12 T40 15


User Defined Cross Bins for z3_wakeupXval

Excluded/Illegal bins
NAMECOUNTSTATUS
invalid0 0 Excluded
invalid1 0 Excluded

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