Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.62	99.29	96.38	100.00	96.15	98.74	99.42	93.36

Total tests in report: 910

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
66.21	66.21	82.61	82.61	72.83	72.83	86.30	86.30	31.41	31.41	84.33	84.33	73.89	73.89	32.09	32.09	/workspace/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.1707922288
74.31	8.10	89.46	6.85	82.46	9.63	95.66	9.36	42.31	10.90	89.83	5.51	82.76	8.86	37.67	5.58	/workspace/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.2674304998
79.21	4.91	92.26	2.80	86.58	4.12	97.03	1.37	42.95	0.64	92.16	2.33	85.55	2.79	57.97	20.30	/workspace/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.2492221998
83.09	3.88	94.55	2.30	88.60	2.02	97.03	0.00	57.69	14.74	94.12	1.96	91.23	5.68	58.40	0.43	/workspace/coverage/default/0.sysrst_ctrl_edge_detect.2482334540
85.56	2.47	96.08	1.53	90.55	1.95	97.49	0.46	66.03	8.33	95.49	1.37	94.80	3.56	58.50	0.11	/workspace/coverage/default/26.sysrst_ctrl_ultra_low_pwr.2129143496
87.87	2.30	97.20	1.12	92.19	1.64	97.49	0.00	78.21	12.18	96.67	1.18	94.80	0.00	58.50	0.00	/workspace/coverage/default/0.sysrst_ctrl_feature_disable.2940058446
89.34	1.47	97.67	0.47	92.67	0.48	97.49	0.00	82.69	4.49	97.08	0.41	95.95	1.16	61.80	3.29	/workspace/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.2654104899
90.60	1.27	97.74	0.07	93.83	1.16	98.17	0.68	82.69	0.00	97.19	0.11	95.95	0.00	68.65	6.85	/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.2229337486
91.47	0.86	97.82	0.07	93.91	0.08	98.17	0.00	83.33	0.64	97.30	0.11	96.15	0.19	73.59	4.94	/workspace/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.1586602005
92.29	0.83	97.82	0.00	93.96	0.05	98.17	0.00	83.33	0.00	97.30	0.00	96.15	0.00	79.33	5.74	/workspace/coverage/default/2.sysrst_ctrl_stress_all.3319742630
93.07	0.77	98.21	0.39	94.34	0.38	98.17	0.00	86.54	3.21	97.67	0.37	97.21	1.06	79.33	0.00	/workspace/coverage/default/22.sysrst_ctrl_edge_detect.1790801748
93.64	0.57	98.38	0.17	94.41	0.08	98.17	0.00	89.74	3.21	97.89	0.22	97.50	0.29	79.38	0.05	/workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.2307075376
94.16	0.52	98.40	0.02	94.41	0.00	98.17	0.00	90.38	0.64	97.93	0.04	97.50	0.00	82.36	2.98	/workspace/coverage/default/49.sysrst_ctrl_combo_detect.3501926519
94.66	0.49	98.64	0.24	94.51	0.10	98.17	0.00	92.95	2.56	98.08	0.15	97.88	0.39	82.36	0.00	/workspace/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.2901872334
94.97	0.32	98.75	0.11	94.54	0.03	98.17	0.00	92.95	0.00	98.08	0.00	97.88	0.00	84.43	2.07	/workspace/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.1513837028
95.28	0.31	98.92	0.17	94.67	0.13	98.17	0.00	94.23	1.28	98.34	0.26	98.17	0.29	84.48	0.05	/workspace/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.52356276
95.52	0.24	98.97	0.06	94.74	0.08	99.54	1.37	94.23	0.00	98.34	0.00	98.17	0.00	84.64	0.16	/workspace/coverage/default/0.sysrst_ctrl_alert_test.1265130376
95.72	0.20	98.97	0.00	94.77	0.03	99.54	0.00	94.23	0.00	98.34	0.00	98.27	0.10	85.92	1.28	/workspace/coverage/default/44.sysrst_ctrl_stress_all.1700997884
95.88	0.16	99.01	0.04	94.79	0.03	99.54	0.00	94.87	0.64	98.37	0.04	98.36	0.10	86.18	0.27	/workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.765449353
96.02	0.14	99.05	0.04	94.99	0.20	99.54	0.00	94.87	0.00	98.45	0.07	99.04	0.67	86.18	0.00	/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.4099483707
96.16	0.14	99.05	0.00	95.90	0.91	99.54	0.00	94.87	0.00	98.45	0.00	99.04	0.00	86.24	0.05	/workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.3409769882
96.28	0.13	99.10	0.06	95.93	0.03	99.54	0.00	95.51	0.64	98.52	0.07	99.13	0.10	86.24	0.00	/workspace/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.3957200623
96.40	0.12	99.14	0.04	95.96	0.03	99.54	0.00	96.15	0.64	98.56	0.04	99.23	0.10	86.24	0.00	/workspace/coverage/default/26.sysrst_ctrl_edge_detect.3458822231
96.52	0.12	99.16	0.02	95.96	0.00	99.54	0.00	96.15	0.00	98.56	0.00	99.23	0.00	87.04	0.80	/workspace/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.3200594496
96.63	0.11	99.16	0.00	95.96	0.00	99.54	0.00	96.15	0.00	98.56	0.00	99.23	0.00	87.78	0.74	/workspace/coverage/default/31.sysrst_ctrl_stress_all.770050701
96.72	0.10	99.16	0.00	95.98	0.03	100.00	0.46	96.15	0.00	98.56	0.00	99.33	0.10	87.89	0.11	/workspace/coverage/default/0.sysrst_ctrl_sec_cm.2292323513
96.82	0.09	99.16	0.00	96.01	0.03	100.00	0.00	96.15	0.00	98.56	0.00	99.33	0.00	88.52	0.64	/workspace/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.3717863934
96.90	0.08	99.16	0.00	96.03	0.03	100.00	0.00	96.15	0.00	98.56	0.00	99.33	0.00	89.05	0.53	/workspace/coverage/default/42.sysrst_ctrl_stress_all.137791211
96.97	0.07	99.16	0.00	96.03	0.00	100.00	0.00	96.15	0.00	98.56	0.00	99.33	0.00	89.53	0.48	/workspace/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.1040399821
97.03	0.06	99.16	0.00	96.08	0.05	100.00	0.00	96.15	0.00	98.56	0.00	99.33	0.00	89.90	0.37	/workspace/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.2069085974
97.08	0.06	99.18	0.02	96.08	0.00	100.00	0.00	96.15	0.00	98.56	0.00	99.33	0.00	90.28	0.37	/workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.182278651
97.14	0.06	99.22	0.04	96.18	0.10	100.00	0.00	96.15	0.00	98.60	0.04	99.33	0.00	90.49	0.21	/workspace/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.3148405601
97.19	0.05	99.22	0.00	96.18	0.00	100.00	0.00	96.15	0.00	98.60	0.00	99.33	0.00	90.86	0.37	/workspace/coverage/default/14.sysrst_ctrl_combo_detect.2070688806
97.22	0.03	99.22	0.00	96.18	0.00	100.00	0.00	96.15	0.00	98.60	0.00	99.33	0.00	91.07	0.21	/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.552594456
97.25	0.03	99.22	0.00	96.18	0.00	100.00	0.00	96.15	0.00	98.60	0.00	99.33	0.00	91.29	0.21	/workspace/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.3581212436
97.27	0.02	99.22	0.00	96.18	0.00	100.00	0.00	96.15	0.00	98.60	0.00	99.33	0.00	91.45	0.16	/workspace/coverage/default/13.sysrst_ctrl_combo_detect.3379698037
97.30	0.02	99.22	0.00	96.18	0.00	100.00	0.00	96.15	0.00	98.60	0.00	99.33	0.00	91.60	0.16	/workspace/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.1577759432
97.32	0.02	99.22	0.00	96.18	0.00	100.00	0.00	96.15	0.00	98.60	0.00	99.33	0.00	91.76	0.16	/workspace/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.3276602346
97.34	0.02	99.22	0.00	96.18	0.00	100.00	0.00	96.15	0.00	98.60	0.00	99.33	0.00	91.92	0.16	/workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.2328697088
97.36	0.02	99.22	0.00	96.23	0.05	100.00	0.00	96.15	0.00	98.60	0.00	99.42	0.10	91.92	0.00	/workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.1011264128
97.38	0.02	99.25	0.04	96.23	0.00	100.00	0.00	96.15	0.00	98.67	0.07	99.42	0.00	91.92	0.00	/workspace/coverage/default/10.sysrst_ctrl_stress_all.646047217
97.39	0.02	99.25	0.00	96.23	0.00	100.00	0.00	96.15	0.00	98.67	0.00	99.42	0.00	92.03	0.11	/workspace/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.3243291813
97.41	0.02	99.25	0.00	96.23	0.00	100.00	0.00	96.15	0.00	98.67	0.00	99.42	0.00	92.14	0.11	/workspace/coverage/default/23.sysrst_ctrl_combo_detect.3840772097
97.42	0.02	99.25	0.00	96.23	0.00	100.00	0.00	96.15	0.00	98.67	0.00	99.42	0.00	92.24	0.11	/workspace/coverage/default/24.sysrst_ctrl_ultra_low_pwr.1879414048
97.44	0.02	99.25	0.00	96.23	0.00	100.00	0.00	96.15	0.00	98.67	0.00	99.42	0.00	92.35	0.11	/workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.3755314822
97.46	0.02	99.25	0.00	96.23	0.00	100.00	0.00	96.15	0.00	98.67	0.00	99.42	0.00	92.45	0.11	/workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.811735892
97.47	0.02	99.25	0.00	96.23	0.00	100.00	0.00	96.15	0.00	98.67	0.00	99.42	0.00	92.56	0.11	/workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.2686356112
97.49	0.02	99.25	0.00	96.23	0.00	100.00	0.00	96.15	0.00	98.67	0.00	99.42	0.00	92.67	0.11	/workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.756006359
97.50	0.02	99.25	0.00	96.23	0.00	100.00	0.00	96.15	0.00	98.67	0.00	99.42	0.00	92.77	0.11	/workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.498646064
97.52	0.02	99.25	0.00	96.23	0.00	100.00	0.00	96.15	0.00	98.67	0.00	99.42	0.00	92.88	0.11	/workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.3724708197
97.53	0.02	99.25	0.00	96.23	0.00	100.00	0.00	96.15	0.00	98.67	0.00	99.42	0.00	92.99	0.11	/workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.1075568687
97.54	0.01	99.27	0.02	96.23	0.00	100.00	0.00	96.15	0.00	98.71	0.04	99.42	0.00	92.99	0.00	/workspace/coverage/default/10.sysrst_ctrl_edge_detect.2042248495
97.55	0.01	99.29	0.02	96.23	0.00	100.00	0.00	96.15	0.00	98.74	0.04	99.42	0.00	92.99	0.00	/workspace/coverage/default/17.sysrst_ctrl_edge_detect.3791429494
97.55	0.01	99.29	0.00	96.23	0.00	100.00	0.00	96.15	0.00	98.74	0.00	99.42	0.00	93.04	0.05	/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.504128781
97.56	0.01	99.29	0.00	96.23	0.00	100.00	0.00	96.15	0.00	98.74	0.00	99.42	0.00	93.09	0.05	/workspace/coverage/default/0.sysrst_ctrl_combo_detect.1992421708
97.57	0.01	99.29	0.00	96.23	0.00	100.00	0.00	96.15	0.00	98.74	0.00	99.42	0.00	93.15	0.05	/workspace/coverage/default/12.sysrst_ctrl_combo_detect.2899022168
97.58	0.01	99.29	0.00	96.23	0.00	100.00	0.00	96.15	0.00	98.74	0.00	99.42	0.00	93.20	0.05	/workspace/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.291799118
97.59	0.01	99.29	0.00	96.23	0.00	100.00	0.00	96.15	0.00	98.74	0.00	99.42	0.00	93.25	0.05	/workspace/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.2033080837
97.59	0.01	99.29	0.00	96.23	0.00	100.00	0.00	96.15	0.00	98.74	0.00	99.42	0.00	93.30	0.05	/workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.2407927723
97.60	0.01	99.29	0.00	96.23	0.00	100.00	0.00	96.15	0.00	98.74	0.00	99.42	0.00	93.36	0.05	/workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.3816855650
97.61	0.01	99.29	0.00	96.28	0.05	100.00	0.00	96.15	0.00	98.74	0.00	99.42	0.00	93.36	0.00	/workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.3330954742
97.61	0.01	99.29	0.00	96.31	0.03	100.00	0.00	96.15	0.00	98.74	0.00	99.42	0.00	93.36	0.00	/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.1239478362
97.61	0.01	99.29	0.00	96.33	0.03	100.00	0.00	96.15	0.00	98.74	0.00	99.42	0.00	93.36	0.00	/workspace/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.1401370900
97.62	0.01	99.29	0.00	96.36	0.03	100.00	0.00	96.15	0.00	98.74	0.00	99.42	0.00	93.36	0.00	/workspace/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.1164520889

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.314112496
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.863785130
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.873866934
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.3887992828
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.123116911
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.450390086
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.2206953510
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.3960347211
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.33235399
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.1493700898
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.3112697240
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.1129840834
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.3963096938
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.3573790002
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.1511431335
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.27188743
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.2663345854
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.779778951
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.3936979733
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.166486690
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.4205059010
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.361886258
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.3249848079
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.3998165698
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.997395066
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.965518059
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.3656105749
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.531056148
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.1048388187
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.327953516
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.2106477598
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.1236415370
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.2891699878
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.1687587041
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.2789995466
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.4010260936
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.2644931296
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.717369461
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.1972398327
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.566208079
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.3173383272
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.3494261273
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.2518319709
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.4193707545
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.4033854365
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.4274880464
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.1589478869
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.1416837595
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.1918453535
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.1267147646
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.665577037
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.2734821913
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.2071073075
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.2987756280
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.1360405110
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.4013797424
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.2781695376
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.3593065255
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/workspace/coverage/default/4.sysrst_ctrl_ultra_low_pwr.1713432227
/workspace/coverage/default/40.sysrst_ctrl_alert_test.3179037283
/workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.4098466791
/workspace/coverage/default/40.sysrst_ctrl_combo_detect.1237594418
/workspace/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.1542540120
/workspace/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.1704645073
/workspace/coverage/default/40.sysrst_ctrl_edge_detect.1103867818
/workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.3723279838
/workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.2856145962
/workspace/coverage/default/40.sysrst_ctrl_pin_access_test.2326094535
/workspace/coverage/default/40.sysrst_ctrl_pin_override_test.1700306556
/workspace/coverage/default/40.sysrst_ctrl_smoke.3885269914
/workspace/coverage/default/40.sysrst_ctrl_stress_all.2579594117
/workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.2784374994
/workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.998625986
/workspace/coverage/default/41.sysrst_ctrl_alert_test.642045434
/workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.642962418
/workspace/coverage/default/41.sysrst_ctrl_combo_detect.4087567402
/workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.2431743244
/workspace/coverage/default/41.sysrst_ctrl_edge_detect.1134372985
/workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.632011942
/workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.954130109
/workspace/coverage/default/41.sysrst_ctrl_pin_access_test.1126975599
/workspace/coverage/default/41.sysrst_ctrl_pin_override_test.1675467954
/workspace/coverage/default/41.sysrst_ctrl_smoke.57609502
/workspace/coverage/default/41.sysrst_ctrl_stress_all.4094649786
/workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.1292083237
/workspace/coverage/default/42.sysrst_ctrl_alert_test.1142127848
/workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.3400287072
/workspace/coverage/default/42.sysrst_ctrl_combo_detect.298063444
/workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.290433754
/workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.3744269397
/workspace/coverage/default/42.sysrst_ctrl_edge_detect.2133807175
/workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.3984288891
/workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.2539667356
/workspace/coverage/default/42.sysrst_ctrl_pin_access_test.3726391693
/workspace/coverage/default/42.sysrst_ctrl_pin_override_test.1742338072
/workspace/coverage/default/42.sysrst_ctrl_smoke.1756310219
/workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.2303503557
/workspace/coverage/default/43.sysrst_ctrl_alert_test.1163714184
/workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.3253938757
/workspace/coverage/default/43.sysrst_ctrl_combo_detect.29653318
/workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.3020493812
/workspace/coverage/default/43.sysrst_ctrl_edge_detect.1054842187
/workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.2896512153
/workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.1023890284
/workspace/coverage/default/43.sysrst_ctrl_pin_access_test.3725638635
/workspace/coverage/default/43.sysrst_ctrl_pin_override_test.208075107
/workspace/coverage/default/43.sysrst_ctrl_smoke.3888036644
/workspace/coverage/default/43.sysrst_ctrl_stress_all.1032738734
/workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.2400948716
/workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.1555463843
/workspace/coverage/default/44.sysrst_ctrl_alert_test.1382086408
/workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.2572612646
/workspace/coverage/default/44.sysrst_ctrl_combo_detect.3604905063
/workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.2517946938
/workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.490499702
/workspace/coverage/default/44.sysrst_ctrl_edge_detect.2226841794
/workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.1296561761
/workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.1708925560
/workspace/coverage/default/44.sysrst_ctrl_pin_access_test.3263781491
/workspace/coverage/default/44.sysrst_ctrl_pin_override_test.3020547522
/workspace/coverage/default/44.sysrst_ctrl_smoke.104622767
/workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.1807166777
/workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.2470476145
/workspace/coverage/default/45.sysrst_ctrl_alert_test.1165053207
/workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.2741987932
/workspace/coverage/default/45.sysrst_ctrl_combo_detect.3525913616
/workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.1587694621
/workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.543696326
/workspace/coverage/default/45.sysrst_ctrl_edge_detect.1204661281
/workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.1621525839
/workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.4282310752
/workspace/coverage/default/45.sysrst_ctrl_pin_access_test.2848165303
/workspace/coverage/default/45.sysrst_ctrl_pin_override_test.2117781550
/workspace/coverage/default/45.sysrst_ctrl_smoke.2149286205
/workspace/coverage/default/45.sysrst_ctrl_stress_all.2973377201
/workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.2781078935
/workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.497257236
/workspace/coverage/default/46.sysrst_ctrl_alert_test.3341667142
/workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.1688869785
/workspace/coverage/default/46.sysrst_ctrl_combo_detect.1351460982
/workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.962447203
/workspace/coverage/default/46.sysrst_ctrl_edge_detect.2569027334
/workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.2584483591
/workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.2013938334
/workspace/coverage/default/46.sysrst_ctrl_pin_access_test.3882507514
/workspace/coverage/default/46.sysrst_ctrl_pin_override_test.774718930
/workspace/coverage/default/46.sysrst_ctrl_smoke.661399638
/workspace/coverage/default/46.sysrst_ctrl_stress_all.817946484
/workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.3603698374
/workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.799368093
/workspace/coverage/default/47.sysrst_ctrl_alert_test.3732696478
/workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.2155695774
/workspace/coverage/default/47.sysrst_ctrl_combo_detect.2629694938
/workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.4106675006
/workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.2878308449
/workspace/coverage/default/47.sysrst_ctrl_edge_detect.3621142727
/workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.1805359142
/workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.3585403485
/workspace/coverage/default/47.sysrst_ctrl_pin_access_test.657771741
/workspace/coverage/default/47.sysrst_ctrl_pin_override_test.2987876349
/workspace/coverage/default/47.sysrst_ctrl_smoke.4059732848
/workspace/coverage/default/47.sysrst_ctrl_stress_all.3536789281
/workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.3781971211
/workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.528057638
/workspace/coverage/default/48.sysrst_ctrl_alert_test.2368320685
/workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.1790062919
/workspace/coverage/default/48.sysrst_ctrl_combo_detect.1597613648
/workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.377269083
/workspace/coverage/default/48.sysrst_ctrl_edge_detect.1660826065
/workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.1103859082
/workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.1555904578
/workspace/coverage/default/48.sysrst_ctrl_pin_access_test.3454898810
/workspace/coverage/default/48.sysrst_ctrl_pin_override_test.2342185924
/workspace/coverage/default/48.sysrst_ctrl_smoke.3814376116
/workspace/coverage/default/48.sysrst_ctrl_stress_all.77998296
/workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.53051412
/workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.3421222926
/workspace/coverage/default/49.sysrst_ctrl_alert_test.673397749
/workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.2979514619
/workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.2969202959
/workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.2989052797
/workspace/coverage/default/49.sysrst_ctrl_edge_detect.1608236468
/workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.1144371275
/workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.145274375
/workspace/coverage/default/49.sysrst_ctrl_pin_access_test.1251006454
/workspace/coverage/default/49.sysrst_ctrl_pin_override_test.2877133437
/workspace/coverage/default/49.sysrst_ctrl_smoke.3143156019
/workspace/coverage/default/49.sysrst_ctrl_stress_all.1651619213
/workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.2341633238
/workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.423029522
/workspace/coverage/default/5.sysrst_ctrl_alert_test.531203057
/workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.1576303900
/workspace/coverage/default/5.sysrst_ctrl_combo_detect.1469401011
/workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.14364841
/workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.3345296767
/workspace/coverage/default/5.sysrst_ctrl_edge_detect.4006557241
/workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.3731747470
/workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.3645850437
/workspace/coverage/default/5.sysrst_ctrl_pin_access_test.2143575555
/workspace/coverage/default/5.sysrst_ctrl_pin_override_test.1646584528
/workspace/coverage/default/5.sysrst_ctrl_smoke.740766426
/workspace/coverage/default/5.sysrst_ctrl_stress_all.660755528
/workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.3487664536
/workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.1344302549
/workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.376515601
/workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.1431164619
/workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.527394171
/workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.2900513907
/workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.286099397
/workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.1001351868
/workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.836230300
/workspace/coverage/default/6.sysrst_ctrl_alert_test.4042014241
/workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.56633786
/workspace/coverage/default/6.sysrst_ctrl_combo_detect.2740970596
/workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.2930429334
/workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.4287382667
/workspace/coverage/default/6.sysrst_ctrl_edge_detect.996692892
/workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.742559380
/workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.3328715271
/workspace/coverage/default/6.sysrst_ctrl_pin_access_test.4035492982
/workspace/coverage/default/6.sysrst_ctrl_pin_override_test.1386848239
/workspace/coverage/default/6.sysrst_ctrl_smoke.1533675536
/workspace/coverage/default/6.sysrst_ctrl_stress_all.955836283
/workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.475790109
/workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.1732164138
/workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.1819132360
/workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.961750879
/workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.3104046983
/workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.283142605
/workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.1304627883
/workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.449439144
/workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.3430924950
/workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.561164770
/workspace/coverage/default/7.sysrst_ctrl_alert_test.275558397
/workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.105556767
/workspace/coverage/default/7.sysrst_ctrl_combo_detect.1334367735
/workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.2899896578
/workspace/coverage/default/7.sysrst_ctrl_edge_detect.2773442604
/workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.4155195663
/workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.889317346
/workspace/coverage/default/7.sysrst_ctrl_pin_access_test.930040058
/workspace/coverage/default/7.sysrst_ctrl_pin_override_test.672088627
/workspace/coverage/default/7.sysrst_ctrl_smoke.1389234211
/workspace/coverage/default/7.sysrst_ctrl_stress_all.2658080027
/workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.3402525666
/workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.3612223732
/workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.677867692
/workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.637907409
/workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.2418747336
/workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.4241523062
/workspace/coverage/default/8.sysrst_ctrl_alert_test.986027421
/workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.2303853852
/workspace/coverage/default/8.sysrst_ctrl_combo_detect.4117323631
/workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.1767285846
/workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.1133387751
/workspace/coverage/default/8.sysrst_ctrl_edge_detect.948197621
/workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.1389734806
/workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.3603184684
/workspace/coverage/default/8.sysrst_ctrl_pin_access_test.3928572785
/workspace/coverage/default/8.sysrst_ctrl_pin_override_test.2466485375
/workspace/coverage/default/8.sysrst_ctrl_smoke.3759761226
/workspace/coverage/default/8.sysrst_ctrl_stress_all.1054720252
/workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.305304313
/workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.4290961887
/workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.898525515
/workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.1791659520
/workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.3593708360
/workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.3656557314
/workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.816434911
/workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.1096877687
/workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.887907203
/workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.4171295486
/workspace/coverage/default/9.sysrst_ctrl_alert_test.3457797281
/workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.3944062737
/workspace/coverage/default/9.sysrst_ctrl_combo_detect.414487342
/workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.3640533798
/workspace/coverage/default/9.sysrst_ctrl_edge_detect.1167401424
/workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.1220650931
/workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.3119975844
/workspace/coverage/default/9.sysrst_ctrl_pin_access_test.4023891828
/workspace/coverage/default/9.sysrst_ctrl_pin_override_test.3758132186
/workspace/coverage/default/9.sysrst_ctrl_smoke.72697282
/workspace/coverage/default/9.sysrst_ctrl_stress_all.973330460
/workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.2241798582
/workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.1041094715
/workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.2550434849
/workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.495104102
/workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.1743437545
/workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.3583504947
/workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.2361068488
/workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.3170950670
/workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.323654219

Total test records in report: 910

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T5	/workspace/coverage/default/37.sysrst_ctrl_smoke.3893780049	Mar 17 12:56:41 PM PDT 24	Mar 17 12:56:47 PM PDT 24	2111260756 ps
T1	/workspace/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.2674304998	Mar 17 12:55:41 PM PDT 24	Mar 17 12:56:35 PM PDT 24	80023192821 ps
T6	/workspace/coverage/default/18.sysrst_ctrl_pin_override_test.1719836042	Mar 17 12:55:47 PM PDT 24	Mar 17 12:55:54 PM PDT 24	2508523947 ps
T13	/workspace/coverage/default/3.sysrst_ctrl_pin_access_test.3916545284	Mar 17 12:55:34 PM PDT 24	Mar 17 12:55:40 PM PDT 24	2219920214 ps
T2	/workspace/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.1371620346	Mar 17 12:55:34 PM PDT 24	Mar 17 12:56:05 PM PDT 24	44596416686 ps
T3	/workspace/coverage/default/16.sysrst_ctrl_combo_detect.2782973143	Mar 17 12:55:49 PM PDT 24	Mar 17 12:56:23 PM PDT 24	26103363619 ps
T4	/workspace/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.1707922288	Mar 17 12:56:34 PM PDT 24	Mar 17 12:57:20 PM PDT 24	156215285034 ps
T14	/workspace/coverage/default/38.sysrst_ctrl_pin_override_test.1030298570	Mar 17 12:56:49 PM PDT 24	Mar 17 12:56:51 PM PDT 24	2529586959 ps
T15	/workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.182278651	Mar 17 12:57:20 PM PDT 24	Mar 17 12:58:10 PM PDT 24	75747434977 ps
T7	/workspace/coverage/default/18.sysrst_ctrl_stress_all.2325116951	Mar 17 12:55:51 PM PDT 24	Mar 17 12:56:28 PM PDT 24	69711830928 ps
T16	/workspace/coverage/default/5.sysrst_ctrl_pin_access_test.2143575555	Mar 17 12:55:45 PM PDT 24	Mar 17 12:55:51 PM PDT 24	2087756544 ps
T52	/workspace/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.2164418135	Mar 17 12:55:59 PM PDT 24	Mar 17 12:56:07 PM PDT 24	2612370531 ps
T8	/workspace/coverage/default/16.sysrst_ctrl_ultra_low_pwr.1353108753	Mar 17 12:55:57 PM PDT 24	Mar 17 12:55:59 PM PDT 24	6139103589 ps
T9	/workspace/coverage/default/27.sysrst_ctrl_ultra_low_pwr.4000735485	Mar 17 12:56:21 PM PDT 24	Mar 17 12:56:23 PM PDT 24	10359825698 ps
T10	/workspace/coverage/default/5.sysrst_ctrl_edge_detect.4006557241	Mar 17 12:55:40 PM PDT 24	Mar 17 12:55:50 PM PDT 24	3145323420 ps
T21	/workspace/coverage/default/2.sysrst_ctrl_stress_all.3319742630	Mar 17 12:55:20 PM PDT 24	Mar 17 12:58:24 PM PDT 24	149502931629 ps
T53	/workspace/coverage/default/21.sysrst_ctrl_ultra_low_pwr.2595509139	Mar 17 12:55:55 PM PDT 24	Mar 17 12:56:01 PM PDT 24	3083005883 ps
T54	/workspace/coverage/default/9.sysrst_ctrl_pin_override_test.3758132186	Mar 17 12:55:37 PM PDT 24	Mar 17 12:55:41 PM PDT 24	2524261274 ps
T55	/workspace/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.2695463885	Mar 17 12:56:28 PM PDT 24	Mar 17 12:56:30 PM PDT 24	2911005185 ps
T11	/workspace/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.2492221998	Mar 17 12:56:22 PM PDT 24	Mar 17 12:57:23 PM PDT 24	78337223005 ps
T56	/workspace/coverage/default/30.sysrst_ctrl_pin_override_test.1746038349	Mar 17 12:56:29 PM PDT 24	Mar 17 12:56:32 PM PDT 24	2537397090 ps
T22	/workspace/coverage/default/20.sysrst_ctrl_in_out_inverted.539307559	Mar 17 12:55:59 PM PDT 24	Mar 17 12:56:06 PM PDT 24	2448522095 ps
T67	/workspace/coverage/default/43.sysrst_ctrl_pin_override_test.208075107	Mar 17 12:56:51 PM PDT 24	Mar 17 12:56:59 PM PDT 24	2514630277 ps
T42	/workspace/coverage/default/5.sysrst_ctrl_stress_all.660755528	Mar 17 12:55:30 PM PDT 24	Mar 17 12:55:37 PM PDT 24	8026311461 ps
T23	/workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.290433754	Mar 17 12:56:50 PM PDT 24	Mar 17 12:58:50 PM PDT 24	42611323125 ps
T265	/workspace/coverage/default/43.sysrst_ctrl_alert_test.1163714184	Mar 17 12:56:57 PM PDT 24	Mar 17 12:56:58 PM PDT 24	2084677078 ps
T12	/workspace/coverage/default/26.sysrst_ctrl_ultra_low_pwr.2129143496	Mar 17 12:56:18 PM PDT 24	Mar 17 12:56:27 PM PDT 24	7940904678 ps
T57	/workspace/coverage/default/11.sysrst_ctrl_ultra_low_pwr.1466237033	Mar 17 12:55:38 PM PDT 24	Mar 17 12:55:40 PM PDT 24	8343957190 ps
T27	/workspace/coverage/default/37.sysrst_ctrl_combo_detect.767005168	Mar 17 12:56:42 PM PDT 24	Mar 17 01:04:30 PM PDT 24	204048572206 ps
T375	/workspace/coverage/default/34.sysrst_ctrl_smoke.1614971891	Mar 17 12:56:33 PM PDT 24	Mar 17 12:56:39 PM PDT 24	2110473344 ps
T376	/workspace/coverage/default/16.sysrst_ctrl_pin_access_test.219449299	Mar 17 12:57:07 PM PDT 24	Mar 17 12:57:13 PM PDT 24	2061872067 ps
T377	/workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.1144371275	Mar 17 12:57:14 PM PDT 24	Mar 17 12:57:18 PM PDT 24	2618343945 ps
T43	/workspace/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.2774114010	Mar 17 12:56:17 PM PDT 24	Mar 17 12:57:11 PM PDT 24	29401281293 ps
T60	/workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.145274375	Mar 17 12:57:13 PM PDT 24	Mar 17 12:57:16 PM PDT 24	2494510273 ps
T378	/workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.1220650931	Mar 17 12:55:38 PM PDT 24	Mar 17 12:55:40 PM PDT 24	2652458985 ps
T285	/workspace/coverage/default/45.sysrst_ctrl_alert_test.1165053207	Mar 17 12:57:06 PM PDT 24	Mar 17 12:57:12 PM PDT 24	2015375750 ps
T61	/workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.2539667356	Mar 17 12:56:50 PM PDT 24	Mar 17 12:56:54 PM PDT 24	2466496299 ps
T379	/workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.3744269397	Mar 17 12:56:50 PM PDT 24	Mar 17 12:56:54 PM PDT 24	2597846055 ps
T286	/workspace/coverage/default/9.sysrst_ctrl_alert_test.3457797281	Mar 17 12:55:49 PM PDT 24	Mar 17 12:55:56 PM PDT 24	2009075680 ps
T380	/workspace/coverage/default/20.sysrst_ctrl_alert_test.1042883993	Mar 17 12:55:59 PM PDT 24	Mar 17 12:56:01 PM PDT 24	2037530185 ps
T381	/workspace/coverage/default/42.sysrst_ctrl_alert_test.1142127848	Mar 17 12:56:51 PM PDT 24	Mar 17 12:56:53 PM PDT 24	2042178723 ps
T58	/workspace/coverage/default/14.sysrst_ctrl_ultra_low_pwr.3294170907	Mar 17 12:55:45 PM PDT 24	Mar 17 12:55:49 PM PDT 24	3640689357 ps
T30	/workspace/coverage/default/31.sysrst_ctrl_edge_detect.811607239	Mar 17 12:56:34 PM PDT 24	Mar 17 12:56:37 PM PDT 24	4160577450 ps
T37	/workspace/coverage/default/30.sysrst_ctrl_edge_detect.1070120054	Mar 17 12:56:30 PM PDT 24	Mar 17 12:56:35 PM PDT 24	3232110568 ps
T62	/workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.3603184684	Mar 17 12:55:34 PM PDT 24	Mar 17 12:55:43 PM PDT 24	2480502775 ps
T34	/workspace/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.1040399821	Mar 17 12:55:41 PM PDT 24	Mar 17 12:56:33 PM PDT 24	19570831907 ps
T59	/workspace/coverage/default/33.sysrst_ctrl_ultra_low_pwr.579627340	Mar 17 12:56:34 PM PDT 24	Mar 17 12:57:04 PM PDT 24	397951275036 ps
T89	/workspace/coverage/default/0.sysrst_ctrl_pin_override_test.102990835	Mar 17 12:55:16 PM PDT 24	Mar 17 12:55:23 PM PDT 24	2509636845 ps
T90	/workspace/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.3673813254	Mar 17 12:56:42 PM PDT 24	Mar 17 12:56:45 PM PDT 24	2631464122 ps
T28	/workspace/coverage/default/22.sysrst_ctrl_combo_detect.3195986445	Mar 17 12:55:59 PM PDT 24	Mar 17 12:58:09 PM PDT 24	195174902179 ps
T204	/workspace/coverage/default/34.sysrst_ctrl_pin_access_test.2796416250	Mar 17 12:56:36 PM PDT 24	Mar 17 12:56:40 PM PDT 24	2132349289 ps
T205	/workspace/coverage/default/47.sysrst_ctrl_alert_test.3732696478	Mar 17 12:57:10 PM PDT 24	Mar 17 12:57:11 PM PDT 24	2050142279 ps
T44	/workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.56633786	Mar 17 12:55:46 PM PDT 24	Mar 17 12:55:51 PM PDT 24	3330829339 ps
T221	/workspace/coverage/default/37.sysrst_ctrl_pin_access_test.2360473431	Mar 17 12:56:32 PM PDT 24	Mar 17 12:56:39 PM PDT 24	2204682143 ps
T222	/workspace/coverage/default/31.sysrst_ctrl_pin_access_test.1365454333	Mar 17 12:56:32 PM PDT 24	Mar 17 12:56:38 PM PDT 24	2205305792 ps
T38	/workspace/coverage/default/23.sysrst_ctrl_edge_detect.242011023	Mar 17 12:56:19 PM PDT 24	Mar 17 12:56:25 PM PDT 24	4496137838 ps
T127	/workspace/coverage/default/25.sysrst_ctrl_combo_detect.730801970	Mar 17 12:56:17 PM PDT 24	Mar 17 12:57:02 PM PDT 24	34727494424 ps
T220	/workspace/coverage/default/43.sysrst_ctrl_smoke.3888036644	Mar 17 12:56:50 PM PDT 24	Mar 17 12:56:53 PM PDT 24	2139782510 ps
T29	/workspace/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.3717863934	Mar 17 12:55:59 PM PDT 24	Mar 17 01:01:09 PM PDT 24	127506066747 ps
T45	/workspace/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.2069085974	Mar 17 12:56:51 PM PDT 24	Mar 17 12:57:18 PM PDT 24	41761952743 ps
T63	/workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.1555904578	Mar 17 12:57:08 PM PDT 24	Mar 17 12:57:16 PM PDT 24	2465871614 ps
T190	/workspace/coverage/default/21.sysrst_ctrl_pin_override_test.1666240415	Mar 17 12:55:59 PM PDT 24	Mar 17 12:56:06 PM PDT 24	2510437038 ps
T191	/workspace/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.274966080	Mar 17 12:55:51 PM PDT 24	Mar 17 12:55:59 PM PDT 24	2611543924 ps
T46	/workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.4106675006	Mar 17 12:57:03 PM PDT 24	Mar 17 12:57:54 PM PDT 24	74696240865 ps
T47	/workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.1344302549	Mar 17 12:57:16 PM PDT 24	Mar 17 12:58:00 PM PDT 24	65363609392 ps
T64	/workspace/coverage/default/37.sysrst_ctrl_in_out_inverted.2179716410	Mar 17 12:56:34 PM PDT 24	Mar 17 12:56:42 PM PDT 24	2470734682 ps
T192	/workspace/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.2970190041	Mar 17 12:55:57 PM PDT 24	Mar 17 12:56:01 PM PDT 24	2618104762 ps
T193	/workspace/coverage/default/47.sysrst_ctrl_stress_all.3536789281	Mar 17 12:57:03 PM PDT 24	Mar 17 12:57:22 PM PDT 24	6980215297 ps
T257	/workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.1103859082	Mar 17 12:57:06 PM PDT 24	Mar 17 12:57:13 PM PDT 24	2612713289 ps
T258	/workspace/coverage/default/11.sysrst_ctrl_pin_access_test.1934912625	Mar 17 12:55:47 PM PDT 24	Mar 17 12:55:49 PM PDT 24	2210420267 ps
T259	/workspace/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.633244617	Mar 17 12:56:21 PM PDT 24	Mar 17 12:56:27 PM PDT 24	2615587813 ps
T71	/workspace/coverage/default/32.sysrst_ctrl_ultra_low_pwr.605091999	Mar 17 12:56:30 PM PDT 24	Mar 17 12:56:32 PM PDT 24	4999794802 ps
T260	/workspace/coverage/default/40.sysrst_ctrl_pin_access_test.2326094535	Mar 17 12:56:37 PM PDT 24	Mar 17 12:56:44 PM PDT 24	2203393094 ps
T48	/workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.677867692	Mar 17 12:57:24 PM PDT 24	Mar 17 12:57:58 PM PDT 24	24086676114 ps
T65	/workspace/coverage/default/14.sysrst_ctrl_in_out_inverted.3561396016	Mar 17 12:55:47 PM PDT 24	Mar 17 12:55:51 PM PDT 24	2457855425 ps
T248	/workspace/coverage/default/46.sysrst_ctrl_smoke.661399638	Mar 17 12:57:04 PM PDT 24	Mar 17 12:57:06 PM PDT 24	2124145936 ps
T68	/workspace/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.2789925584	Mar 17 12:55:55 PM PDT 24	Mar 17 12:56:55 PM PDT 24	43212155668 ps
T249	/workspace/coverage/default/10.sysrst_ctrl_smoke.1433557683	Mar 17 12:55:50 PM PDT 24	Mar 17 12:55:54 PM PDT 24	2117488603 ps
T66	/workspace/coverage/default/16.sysrst_ctrl_in_out_inverted.72965779	Mar 17 12:55:44 PM PDT 24	Mar 17 12:55:48 PM PDT 24	2455564996 ps
T31	/workspace/coverage/default/1.sysrst_ctrl_edge_detect.1440722037	Mar 17 12:55:16 PM PDT 24	Mar 17 12:55:22 PM PDT 24	4619314581 ps
T250	/workspace/coverage/default/6.sysrst_ctrl_combo_detect.2740970596	Mar 17 12:55:45 PM PDT 24	Mar 17 12:59:09 PM PDT 24	158394827141 ps
T72	/workspace/coverage/default/23.sysrst_ctrl_ultra_low_pwr.2245894062	Mar 17 12:56:11 PM PDT 24	Mar 17 12:56:21 PM PDT 24	9936491372 ps
T251	/workspace/coverage/default/36.sysrst_ctrl_in_out_inverted.4180122635	Mar 17 12:56:31 PM PDT 24	Mar 17 12:56:35 PM PDT 24	2449610624 ps
T382	/workspace/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.1518849372	Mar 17 12:56:38 PM PDT 24	Mar 17 12:56:47 PM PDT 24	2609163884 ps
T49	/workspace/coverage/default/42.sysrst_ctrl_stress_all.137791211	Mar 17 12:56:51 PM PDT 24	Mar 17 12:57:39 PM PDT 24	68704537467 ps
T383	/workspace/coverage/default/26.sysrst_ctrl_pin_override_test.3579984916	Mar 17 12:56:15 PM PDT 24	Mar 17 12:56:22 PM PDT 24	2510902572 ps
T384	/workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.1296561761	Mar 17 12:56:56 PM PDT 24	Mar 17 12:57:04 PM PDT 24	2610328007 ps
T385	/workspace/coverage/default/6.sysrst_ctrl_alert_test.4042014241	Mar 17 12:55:42 PM PDT 24	Mar 17 12:55:48 PM PDT 24	2011435971 ps
T35	/workspace/coverage/default/14.sysrst_ctrl_edge_detect.859512441	Mar 17 12:55:50 PM PDT 24	Mar 17 12:55:52 PM PDT 24	3620886883 ps
T128	/workspace/coverage/default/47.sysrst_ctrl_smoke.4059732848	Mar 17 12:57:05 PM PDT 24	Mar 17 12:57:07 PM PDT 24	2140871881 ps
T129	/workspace/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.735588017	Mar 17 12:55:41 PM PDT 24	Mar 17 12:55:45 PM PDT 24	4822001638 ps
T36	/workspace/coverage/default/29.sysrst_ctrl_edge_detect.1562985138	Mar 17 12:56:26 PM PDT 24	Mar 17 12:56:29 PM PDT 24	4177892033 ps
T130	/workspace/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.3045292959	Mar 17 12:56:18 PM PDT 24	Mar 17 12:56:20 PM PDT 24	2682519092 ps
T131	/workspace/coverage/default/30.sysrst_ctrl_alert_test.1413772033	Mar 17 12:56:30 PM PDT 24	Mar 17 12:56:36 PM PDT 24	2011092311 ps
T69	/workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.1431164619	Mar 17 12:57:15 PM PDT 24	Mar 17 01:01:07 PM PDT 24	84608176382 ps
T169	/workspace/coverage/default/31.sysrst_ctrl_pin_override_test.3150541864	Mar 17 12:56:24 PM PDT 24	Mar 17 12:56:28 PM PDT 24	2515808977 ps
T170	/workspace/coverage/default/16.sysrst_ctrl_pin_override_test.1742893351	Mar 17 12:55:44 PM PDT 24	Mar 17 12:55:46 PM PDT 24	2533470145 ps
T171	/workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.3328715271	Mar 17 12:55:42 PM PDT 24	Mar 17 12:55:44 PM PDT 24	2475213074 ps
T386	/workspace/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.870760546	Mar 17 12:55:31 PM PDT 24	Mar 17 12:55:34 PM PDT 24	2623851918 ps
T91	/workspace/coverage/default/29.sysrst_ctrl_combo_detect.3102245234	Mar 17 12:56:24 PM PDT 24	Mar 17 12:57:31 PM PDT 24	101736115763 ps
T70	/workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.836230300	Mar 17 12:57:15 PM PDT 24	Mar 17 12:57:33 PM PDT 24	26096849035 ps
T110	/workspace/coverage/default/38.sysrst_ctrl_ultra_low_pwr.1298073624	Mar 17 12:56:37 PM PDT 24	Mar 17 12:56:42 PM PDT 24	3616361149 ps
T111	/workspace/coverage/default/2.sysrst_ctrl_smoke.1574879421	Mar 17 12:55:41 PM PDT 24	Mar 17 12:55:43 PM PDT 24	2182402209 ps
T112	/workspace/coverage/default/34.sysrst_ctrl_pin_override_test.2021282766	Mar 17 12:56:33 PM PDT 24	Mar 17 12:56:41 PM PDT 24	2513248696 ps
T113	/workspace/coverage/default/6.sysrst_ctrl_pin_access_test.4035492982	Mar 17 12:55:38 PM PDT 24	Mar 17 12:55:41 PM PDT 24	2144708371 ps
T114	/workspace/coverage/default/41.sysrst_ctrl_stress_all.4094649786	Mar 17 12:56:52 PM PDT 24	Mar 17 12:56:57 PM PDT 24	7156381663 ps
T115	/workspace/coverage/default/5.sysrst_ctrl_pin_override_test.1646584528	Mar 17 12:55:35 PM PDT 24	Mar 17 12:55:38 PM PDT 24	2532237802 ps
T116	/workspace/coverage/default/20.sysrst_ctrl_pin_override_test.2322393030	Mar 17 12:55:54 PM PDT 24	Mar 17 12:55:57 PM PDT 24	2541942332 ps
T117	/workspace/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.262095265	Mar 17 12:55:28 PM PDT 24	Mar 17 12:56:15 PM PDT 24	36016351560 ps
T79	/workspace/coverage/default/12.sysrst_ctrl_edge_detect.1410256973	Mar 17 12:55:51 PM PDT 24	Mar 17 12:55:54 PM PDT 24	4143545743 ps
T92	/workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.898525515	Mar 17 12:57:21 PM PDT 24	Mar 17 12:58:28 PM PDT 24	24583993677 ps
T206	/workspace/coverage/default/0.sysrst_ctrl_alert_test.1265130376	Mar 17 12:55:16 PM PDT 24	Mar 17 12:55:23 PM PDT 24	2012240344 ps
T207	/workspace/coverage/default/0.sysrst_ctrl_stress_all.107419782	Mar 17 12:55:15 PM PDT 24	Mar 17 12:55:20 PM PDT 24	6783382969 ps
T208	/workspace/coverage/default/48.sysrst_ctrl_combo_detect.1597613648	Mar 17 12:57:16 PM PDT 24	Mar 17 12:58:01 PM PDT 24	139761124218 ps
T209	/workspace/coverage/default/8.sysrst_ctrl_alert_test.986027421	Mar 17 12:55:45 PM PDT 24	Mar 17 12:55:48 PM PDT 24	2018507688 ps
T210	/workspace/coverage/default/4.sysrst_ctrl_in_out_inverted.2015809788	Mar 17 12:55:23 PM PDT 24	Mar 17 12:55:28 PM PDT 24	2473327182 ps
T50	/workspace/coverage/default/3.sysrst_ctrl_auto_blk_key_output.3653834562	Mar 17 12:55:22 PM PDT 24	Mar 17 12:58:14 PM PDT 24	142343799527 ps
T211	/workspace/coverage/default/19.sysrst_ctrl_ultra_low_pwr.902665062	Mar 17 12:55:53 PM PDT 24	Mar 17 12:55:55 PM PDT 24	3113977838 ps
T73	/workspace/coverage/default/17.sysrst_ctrl_ultra_low_pwr.4182289195	Mar 17 12:55:59 PM PDT 24	Mar 17 12:56:00 PM PDT 24	5489680858 ps
T93	/workspace/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.346763603	Mar 17 12:56:32 PM PDT 24	Mar 17 12:56:50 PM PDT 24	26358817821 ps
T51	/workspace/coverage/default/23.sysrst_ctrl_auto_blk_key_output.2640702066	Mar 17 12:56:08 PM PDT 24	Mar 17 12:57:31 PM PDT 24	126983228271 ps
T41	/workspace/coverage/default/37.sysrst_ctrl_stress_all.2209759102	Mar 17 12:56:39 PM PDT 24	Mar 17 12:56:46 PM PDT 24	9232071791 ps
T174	/workspace/coverage/default/47.sysrst_ctrl_edge_detect.3621142727	Mar 17 12:57:05 PM PDT 24	Mar 17 12:57:09 PM PDT 24	4732248253 ps
T94	/workspace/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.2901872334	Mar 17 12:56:33 PM PDT 24	Mar 17 12:56:52 PM PDT 24	26601476993 ps
T252	/workspace/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.1513837028	Mar 17 12:56:41 PM PDT 24	Mar 17 12:58:33 PM PDT 24	163091688514 ps
T33	/workspace/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.3148405601	Mar 17 12:56:41 PM PDT 24	Mar 17 12:57:21 PM PDT 24	65996061059 ps
T95	/workspace/coverage/default/5.sysrst_ctrl_combo_detect.1469401011	Mar 17 12:55:31 PM PDT 24	Mar 17 12:58:52 PM PDT 24	146160969751 ps
T387	/workspace/coverage/default/14.sysrst_ctrl_pin_access_test.412258299	Mar 17 12:55:42 PM PDT 24	Mar 17 12:55:48 PM PDT 24	2126850374 ps
T39	/workspace/coverage/default/27.sysrst_ctrl_edge_detect.2309133199	Mar 17 12:56:19 PM PDT 24	Mar 17 12:56:30 PM PDT 24	4568635000 ps
T278	/workspace/coverage/default/0.sysrst_ctrl_sec_cm.2292323513	Mar 17 12:55:19 PM PDT 24	Mar 17 12:57:11 PM PDT 24	42012592312 ps
T296	/workspace/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.2621955497	Mar 17 12:55:53 PM PDT 24	Mar 17 12:56:05 PM PDT 24	4230029983 ps
T297	/workspace/coverage/default/15.sysrst_ctrl_stress_all.1192521434	Mar 17 12:55:42 PM PDT 24	Mar 17 12:56:15 PM PDT 24	15550110009 ps
T298	/workspace/coverage/default/24.sysrst_ctrl_smoke.859952377	Mar 17 12:56:21 PM PDT 24	Mar 17 12:56:23 PM PDT 24	2117526617 ps
T274	/workspace/coverage/default/4.sysrst_ctrl_combo_detect.1486342100	Mar 17 12:55:35 PM PDT 24	Mar 17 01:01:58 PM PDT 24	139197983065 ps
T299	/workspace/coverage/default/30.sysrst_ctrl_pin_access_test.376483707	Mar 17 12:56:30 PM PDT 24	Mar 17 12:56:33 PM PDT 24	2057525068 ps
T300	/workspace/coverage/default/8.sysrst_ctrl_pin_override_test.2466485375	Mar 17 12:55:39 PM PDT 24	Mar 17 12:55:47 PM PDT 24	2510559922 ps
T74	/workspace/coverage/default/3.sysrst_ctrl_ultra_low_pwr.2555192669	Mar 17 12:55:27 PM PDT 24	Mar 17 12:55:34 PM PDT 24	4998547859 ps
T146	/workspace/coverage/default/42.sysrst_ctrl_pin_access_test.3726391693	Mar 17 12:56:49 PM PDT 24	Mar 17 12:56:56 PM PDT 24	2206853382 ps
T147	/workspace/coverage/default/2.sysrst_ctrl_sec_cm.2482852783	Mar 17 12:55:23 PM PDT 24	Mar 17 12:55:35 PM PDT 24	22133508385 ps
T126	/workspace/coverage/default/11.sysrst_ctrl_auto_blk_key_output.2560869955	Mar 17 12:55:46 PM PDT 24	Mar 17 12:55:50 PM PDT 24	3693558705 ps
T148	/workspace/coverage/default/12.sysrst_ctrl_alert_test.125110135	Mar 17 12:55:40 PM PDT 24	Mar 17 12:55:42 PM PDT 24	2031279110 ps
T149	/workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.3660578858	Mar 17 12:55:17 PM PDT 24	Mar 17 12:55:20 PM PDT 24	2217854503 ps
T150	/workspace/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.3243291813	Mar 17 12:55:52 PM PDT 24	Mar 17 12:57:51 PM PDT 24	189465400342 ps
T75	/workspace/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.1401370900	Mar 17 12:55:44 PM PDT 24	Mar 17 12:56:50 PM PDT 24	28275128074 ps
T151	/workspace/coverage/default/40.sysrst_ctrl_pin_override_test.1700306556	Mar 17 12:56:39 PM PDT 24	Mar 17 12:56:42 PM PDT 24	2532485082 ps
T152	/workspace/coverage/default/10.sysrst_ctrl_edge_detect.2042248495	Mar 17 12:55:45 PM PDT 24	Mar 17 12:55:52 PM PDT 24	4572793646 ps
T160	/workspace/coverage/default/45.sysrst_ctrl_edge_detect.1204661281	Mar 17 12:57:06 PM PDT 24	Mar 17 12:57:09 PM PDT 24	3450122544 ps
T76	/workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.475790109	Mar 17 12:55:33 PM PDT 24	Mar 17 12:55:36 PM PDT 24	5402776495 ps
T388	/workspace/coverage/default/15.sysrst_ctrl_alert_test.2308697743	Mar 17 12:57:07 PM PDT 24	Mar 17 12:57:13 PM PDT 24	2015436850 ps
T389	/workspace/coverage/default/13.sysrst_ctrl_auto_blk_key_output.408633628	Mar 17 12:55:41 PM PDT 24	Mar 17 12:55:51 PM PDT 24	4036841698 ps
T390	/workspace/coverage/default/45.sysrst_ctrl_pin_access_test.2848165303	Mar 17 12:56:59 PM PDT 24	Mar 17 12:57:02 PM PDT 24	2131846658 ps
T334	/workspace/coverage/default/9.sysrst_ctrl_stress_all.973330460	Mar 17 12:55:48 PM PDT 24	Mar 17 12:57:49 PM PDT 24	322155837206 ps
T391	/workspace/coverage/default/4.sysrst_ctrl_pin_access_test.1721015320	Mar 17 12:55:23 PM PDT 24	Mar 17 12:55:25 PM PDT 24	2107692799 ps
T392	/workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.962447203	Mar 17 12:57:06 PM PDT 24	Mar 17 12:57:13 PM PDT 24	5036351749 ps
T393	/workspace/coverage/default/35.sysrst_ctrl_alert_test.811607728	Mar 17 12:56:39 PM PDT 24	Mar 17 12:56:45 PM PDT 24	2012628714 ps
T32	/workspace/coverage/default/0.sysrst_ctrl_edge_detect.2482334540	Mar 17 12:55:15 PM PDT 24	Mar 17 12:55:28 PM PDT 24	4427531779 ps
T40	/workspace/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.2654104899	Mar 17 12:57:07 PM PDT 24	Mar 17 12:57:32 PM PDT 24	127326253541 ps
T236	/workspace/coverage/default/26.sysrst_ctrl_alert_test.4197248052	Mar 17 12:56:12 PM PDT 24	Mar 17 12:56:14 PM PDT 24	2064022552 ps
T237	/workspace/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.3461739410	Mar 17 12:55:17 PM PDT 24	Mar 17 12:55:28 PM PDT 24	4402836509 ps
T132	/workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.497257236	Mar 17 12:57:04 PM PDT 24	Mar 17 12:57:09 PM PDT 24	10342538446 ps
T238	/workspace/coverage/default/48.sysrst_ctrl_pin_access_test.3454898810	Mar 17 12:57:10 PM PDT 24	Mar 17 12:57:12 PM PDT 24	2026555845 ps
T88	/workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.1767285846	Mar 17 12:55:38 PM PDT 24	Mar 17 12:56:20 PM PDT 24	65857132824 ps
T239	/workspace/coverage/default/49.sysrst_ctrl_combo_detect.3501926519	Mar 17 12:57:13 PM PDT 24	Mar 17 01:05:19 PM PDT 24	185364812244 ps
T240	/workspace/coverage/default/15.sysrst_ctrl_in_out_inverted.1493376095	Mar 17 12:55:41 PM PDT 24	Mar 17 12:55:44 PM PDT 24	2481783452 ps
T241	/workspace/coverage/default/23.sysrst_ctrl_in_out_inverted.2592036550	Mar 17 12:56:06 PM PDT 24	Mar 17 12:56:08 PM PDT 24	2471413542 ps
T242	/workspace/coverage/default/7.sysrst_ctrl_combo_detect.1334367735	Mar 17 12:55:29 PM PDT 24	Mar 17 12:56:58 PM PDT 24	139365370880 ps
T253	/workspace/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.2113075895	Mar 17 12:56:22 PM PDT 24	Mar 17 01:00:14 PM PDT 24	145291579776 ps
T309	/workspace/coverage/default/18.sysrst_ctrl_in_out_inverted.3133124761	Mar 17 12:55:56 PM PDT 24	Mar 17 12:56:03 PM PDT 24	2444254938 ps
T394	/workspace/coverage/default/32.sysrst_ctrl_pin_override_test.515795269	Mar 17 12:56:27 PM PDT 24	Mar 17 12:56:34 PM PDT 24	2508037111 ps
T261	/workspace/coverage/default/13.sysrst_ctrl_combo_detect.3379698037	Mar 17 12:57:03 PM PDT 24	Mar 17 01:01:39 PM PDT 24	111724859457 ps
T395	/workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.2989052797	Mar 17 12:57:16 PM PDT 24	Mar 17 12:57:20 PM PDT 24	2575483016 ps
T254	/workspace/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.3200594496	Mar 17 12:55:56 PM PDT 24	Mar 17 12:56:33 PM PDT 24	94203288112 ps
T396	/workspace/coverage/default/44.sysrst_ctrl_alert_test.1382086408	Mar 17 12:56:56 PM PDT 24	Mar 17 12:57:02 PM PDT 24	2008945669 ps
T397	/workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2814232995	Mar 17 12:55:25 PM PDT 24	Mar 17 12:55:32 PM PDT 24	2319770886 ps
T81	/workspace/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.182999536	Mar 17 12:56:06 PM PDT 24	Mar 17 12:56:42 PM PDT 24	49321139368 ps
T398	/workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.1389734806	Mar 17 12:55:37 PM PDT 24	Mar 17 12:55:45 PM PDT 24	2611128102 ps
T399	/workspace/coverage/default/20.sysrst_ctrl_ultra_low_pwr.4191953536	Mar 17 12:55:58 PM PDT 24	Mar 17 12:56:02 PM PDT 24	6085299512 ps
T400	/workspace/coverage/default/26.sysrst_ctrl_in_out_inverted.2395310811	Mar 17 12:56:13 PM PDT 24	Mar 17 12:56:20 PM PDT 24	2456888234 ps
T401	/workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.4282310752	Mar 17 12:56:58 PM PDT 24	Mar 17 12:57:03 PM PDT 24	2459666546 ps
T402	/workspace/coverage/default/38.sysrst_ctrl_alert_test.2923195402	Mar 17 12:56:36 PM PDT 24	Mar 17 12:56:38 PM PDT 24	2029144436 ps
T403	/workspace/coverage/default/1.sysrst_ctrl_pin_override_test.997778692	Mar 17 12:55:15 PM PDT 24	Mar 17 12:55:17 PM PDT 24	2608938387 ps
T96	/workspace/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.1491794128	Mar 17 12:55:46 PM PDT 24	Mar 17 12:56:37 PM PDT 24	78418566255 ps
T270	/workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.1732164138	Mar 17 12:57:15 PM PDT 24	Mar 17 12:57:55 PM PDT 24	63052486916 ps
T404	/workspace/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.46370043	Mar 17 12:55:25 PM PDT 24	Mar 17 12:55:28 PM PDT 24	2622108726 ps
T83	/workspace/coverage/default/0.sysrst_ctrl_ultra_low_pwr.2767059449	Mar 17 12:55:15 PM PDT 24	Mar 17 12:55:25 PM PDT 24	7025052858 ps
T279	/workspace/coverage/default/3.sysrst_ctrl_sec_cm.1781679799	Mar 17 12:55:25 PM PDT 24	Mar 17 12:56:22 PM PDT 24	42025337494 ps
T405	/workspace/coverage/default/10.sysrst_ctrl_in_out_inverted.2222087931	Mar 17 12:55:45 PM PDT 24	Mar 17 12:55:48 PM PDT 24	2485141372 ps
T406	/workspace/coverage/default/24.sysrst_ctrl_auto_blk_key_output.1340050096	Mar 17 12:56:11 PM PDT 24	Mar 17 12:56:14 PM PDT 24	3337959152 ps
T267	/workspace/coverage/default/33.sysrst_ctrl_stress_all.4028146967	Mar 17 12:56:32 PM PDT 24	Mar 17 12:57:01 PM PDT 24	132924295583 ps
T336	/workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.4241523062	Mar 17 12:57:28 PM PDT 24	Mar 17 12:58:00 PM PDT 24	91890981062 ps
T407	/workspace/coverage/default/7.sysrst_ctrl_stress_all.2658080027	Mar 17 12:55:29 PM PDT 24	Mar 17 12:55:48 PM PDT 24	6775403037 ps
T408	/workspace/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.917682754	Mar 17 12:56:06 PM PDT 24	Mar 17 12:56:16 PM PDT 24	3753813688 ps
T294	/workspace/coverage/default/4.sysrst_ctrl_sec_cm.1044972749	Mar 17 12:55:36 PM PDT 24	Mar 17 12:57:31 PM PDT 24	42011182360 ps
T305	/workspace/coverage/default/31.sysrst_ctrl_stress_all.770050701	Mar 17 12:56:27 PM PDT 24	Mar 17 01:05:02 PM PDT 24	208024537022 ps
T184	/workspace/coverage/default/38.sysrst_ctrl_edge_detect.2197875475	Mar 17 12:56:43 PM PDT 24	Mar 17 12:56:51 PM PDT 24	5629126006 ps
T409	/workspace/coverage/default/49.sysrst_ctrl_pin_access_test.1251006454	Mar 17 12:57:16 PM PDT 24	Mar 17 12:57:19 PM PDT 24	2106950982 ps
T262	/workspace/coverage/default/21.sysrst_ctrl_combo_detect.2912791298	Mar 17 12:55:56 PM PDT 24	Mar 17 01:02:33 PM PDT 24	154420870443 ps
T410	/workspace/coverage/default/48.sysrst_ctrl_edge_detect.1660826065	Mar 17 12:57:16 PM PDT 24	Mar 17 12:57:20 PM PDT 24	2470335575 ps
T333	/workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.1001351868	Mar 17 12:57:17 PM PDT 24	Mar 17 01:00:31 PM PDT 24	73281596381 ps
T411	/workspace/coverage/default/38.sysrst_ctrl_pin_access_test.2910327151	Mar 17 12:56:49 PM PDT 24	Mar 17 12:56:53 PM PDT 24	2129380028 ps
T412	/workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.490499702	Mar 17 12:56:57 PM PDT 24	Mar 17 12:57:00 PM PDT 24	4899608569 ps
T310	/workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.3585403485	Mar 17 12:57:03 PM PDT 24	Mar 17 12:57:07 PM PDT 24	2479107092 ps
T413	/workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.1621525839	Mar 17 12:57:05 PM PDT 24	Mar 17 12:57:13 PM PDT 24	2608931250 ps
T414	/workspace/coverage/default/30.sysrst_ctrl_smoke.2792433188	Mar 17 12:56:32 PM PDT 24	Mar 17 12:56:36 PM PDT 24	2122893499 ps
T86	/workspace/coverage/default/31.sysrst_ctrl_ultra_low_pwr.20927402	Mar 17 12:56:24 PM PDT 24	Mar 17 01:00:55 PM PDT 24	2711648559833 ps
T313	/workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.4290961887	Mar 17 12:55:39 PM PDT 24	Mar 17 12:55:46 PM PDT 24	5221517172 ps
T97	/workspace/coverage/default/44.sysrst_ctrl_stress_all.1700997884	Mar 17 12:57:00 PM PDT 24	Mar 17 12:57:56 PM PDT 24	77923314912 ps
T415	/workspace/coverage/default/7.sysrst_ctrl_smoke.1389234211	Mar 17 12:55:36 PM PDT 24	Mar 17 12:55:38 PM PDT 24	2140711357 ps
T98	/workspace/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.2596202328	Mar 17 12:56:34 PM PDT 24	Mar 17 12:57:39 PM PDT 24	99989686994 ps
T416	/workspace/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.289894229	Mar 17 12:55:47 PM PDT 24	Mar 17 12:55:55 PM PDT 24	2611820823 ps
T417	/workspace/coverage/default/27.sysrst_ctrl_in_out_inverted.1931893172	Mar 17 12:56:22 PM PDT 24	Mar 17 12:56:23 PM PDT 24	2509826798 ps
T418	/workspace/coverage/default/24.sysrst_ctrl_in_out_inverted.3744076720	Mar 17 12:56:06 PM PDT 24	Mar 17 12:56:10 PM PDT 24	2475522290 ps
T347	/workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.3170950670	Mar 17 12:57:22 PM PDT 24	Mar 17 12:58:31 PM PDT 24	55673537407 ps
T419	/workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.3645850437	Mar 17 12:55:30 PM PDT 24	Mar 17 12:55:33 PM PDT 24	2471828378 ps
T80	/workspace/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.2853396539	Mar 17 12:55:16 PM PDT 24	Mar 17 12:56:10 PM PDT 24	79544419991 ps
T420	/workspace/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.1239789576	Mar 17 12:56:34 PM PDT 24	Mar 17 12:56:44 PM PDT 24	5076749291 ps
T311	/workspace/coverage/default/17.sysrst_ctrl_in_out_inverted.3168978307	Mar 17 12:55:49 PM PDT 24	Mar 17 12:55:54 PM PDT 24	2475300961 ps
T421	/workspace/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.904431725	Mar 17 12:55:22 PM PDT 24	Mar 17 12:55:30 PM PDT 24	2611419011 ps
T422	/workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.3612223732	Mar 17 12:55:29 PM PDT 24	Mar 17 12:55:33 PM PDT 24	5710048941 ps
T423	/workspace/coverage/default/30.sysrst_ctrl_auto_blk_key_output.1839197529	Mar 17 12:56:32 PM PDT 24	Mar 17 12:56:44 PM PDT 24	18126996339 ps
T273	/workspace/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.477468496	Mar 17 12:56:33 PM PDT 24	Mar 17 12:58:24 PM PDT 24	104525545813 ps
T424	/workspace/coverage/default/44.sysrst_ctrl_smoke.104622767	Mar 17 12:56:59 PM PDT 24	Mar 17 12:57:01 PM PDT 24	2137084979 ps
T268	/workspace/coverage/default/28.sysrst_ctrl_combo_detect.4233517284	Mar 17 12:56:20 PM PDT 24	Mar 17 12:57:22 PM PDT 24	92615088788 ps
T425	/workspace/coverage/default/24.sysrst_ctrl_alert_test.4192587721	Mar 17 12:56:22 PM PDT 24	Mar 17 12:56:24 PM PDT 24	2037804086 ps
T426	/workspace/coverage/default/17.sysrst_ctrl_pin_override_test.877055261	Mar 17 12:55:53 PM PDT 24	Mar 17 12:56:00 PM PDT 24	2512046329 ps
T256	/workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.2328697088	Mar 17 12:55:30 PM PDT 24	Mar 17 12:56:12 PM PDT 24	59656107441 ps
T427	/workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1388067448	Mar 17 12:55:14 PM PDT 24	Mar 17 12:55:16 PM PDT 24	2526451398 ps
T428	/workspace/coverage/default/8.sysrst_ctrl_smoke.3759761226	Mar 17 12:55:33 PM PDT 24	Mar 17 12:55:34 PM PDT 24	2156821367 ps
T429	/workspace/coverage/default/47.sysrst_ctrl_pin_access_test.657771741	Mar 17 12:57:03 PM PDT 24	Mar 17 12:57:04 PM PDT 24	2117126645 ps
T332	/workspace/coverage/default/42.sysrst_ctrl_combo_detect.298063444	Mar 17 12:56:51 PM PDT 24	Mar 17 12:58:24 PM PDT 24	108864544518 ps
T161	/workspace/coverage/default/46.sysrst_ctrl_edge_detect.2569027334	Mar 17 12:57:02 PM PDT 24	Mar 17 12:57:04 PM PDT 24	2683884494 ps
T176	/workspace/coverage/default/4.sysrst_ctrl_stress_all.2949050132	Mar 17 12:55:35 PM PDT 24	Mar 17 12:55:44 PM PDT 24	13280411824 ps
T99	/workspace/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.2938854005	Mar 17 12:56:41 PM PDT 24	Mar 17 12:57:24 PM PDT 24	31143812401 ps
T177	/workspace/coverage/default/8.sysrst_ctrl_combo_detect.4117323631	Mar 17 12:55:49 PM PDT 24	Mar 17 01:02:32 PM PDT 24	146611184656 ps
T178	/workspace/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.724144592	Mar 17 12:55:21 PM PDT 24	Mar 17 12:57:17 PM PDT 24	44701562288 ps
T179	/workspace/coverage/default/27.sysrst_ctrl_combo_detect.1706691238	Mar 17 12:56:23 PM PDT 24	Mar 17 12:57:19 PM PDT 24	85598989469 ps
T180	/workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.3731747470	Mar 17 12:55:48 PM PDT 24	Mar 17 12:56:00 PM PDT 24	2611579839 ps
T181	/workspace/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.3795750749	Mar 17 12:55:49 PM PDT 24	Mar 17 12:55:57 PM PDT 24	2611403062 ps
T182	/workspace/coverage/default/4.sysrst_ctrl_pin_override_test.4235061157	Mar 17 12:55:44 PM PDT 24	Mar 17 12:55:49 PM PDT 24	2517667698 ps
T183	/workspace/coverage/default/29.sysrst_ctrl_in_out_inverted.2284775925	Mar 17 12:56:19 PM PDT 24	Mar 17 12:56:20 PM PDT 24	2537438662 ps
T430	/workspace/coverage/default/37.sysrst_ctrl_auto_blk_key_output.1642498373	Mar 17 12:56:48 PM PDT 24	Mar 17 12:56:49 PM PDT 24	3190754876 ps
T431	/workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.1171956271	Mar 17 12:55:22 PM PDT 24	Mar 17 12:55:29 PM PDT 24	2393193368 ps
T432	/workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.4155195663	Mar 17 12:55:34 PM PDT 24	Mar 17 12:55:42 PM PDT 24	2613145719 ps
T433	/workspace/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.1893290314	Mar 17 12:56:26 PM PDT 24	Mar 17 12:56:27 PM PDT 24	2648861376 ps
T434	/workspace/coverage/default/34.sysrst_ctrl_in_out_inverted.1831715679	Mar 17 12:56:34 PM PDT 24	Mar 17 12:56:43 PM PDT 24	2433240325 ps
T435	/workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.3984288891	Mar 17 12:56:50 PM PDT 24	Mar 17 12:56:58 PM PDT 24	2613825473 ps
T436	/workspace/coverage/default/44.sysrst_ctrl_pin_override_test.3020547522	Mar 17 12:56:58 PM PDT 24	Mar 17 12:57:00 PM PDT 24	2558333805 ps
T348	/workspace/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.3959199089	Mar 17 12:55:52 PM PDT 24	Mar 17 12:58:00 PM PDT 24	46622187038 ps
T437	/workspace/coverage/default/25.sysrst_ctrl_alert_test.658730956	Mar 17 12:56:12 PM PDT 24	Mar 17 12:56:18 PM PDT 24	2013936345 ps
T100	/workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.1819132360	Mar 17 12:57:20 PM PDT 24	Mar 17 12:58:23 PM PDT 24	25333465015 ps