Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
880 |
1 |
|
|
T6 |
6 |
|
T20 |
11 |
|
T29 |
11 |
| auto[1] |
940 |
1 |
|
|
T6 |
14 |
|
T20 |
9 |
|
T29 |
9 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
904 |
1 |
|
|
T6 |
11 |
|
T20 |
9 |
|
T29 |
8 |
| auto[1] |
916 |
1 |
|
|
T6 |
9 |
|
T20 |
11 |
|
T29 |
12 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
941 |
1 |
|
|
T6 |
11 |
|
T20 |
11 |
|
T29 |
5 |
| auto[1] |
879 |
1 |
|
|
T6 |
9 |
|
T20 |
9 |
|
T29 |
15 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
910 |
1 |
|
|
T6 |
8 |
|
T20 |
11 |
|
T29 |
10 |
| auto[1] |
910 |
1 |
|
|
T6 |
12 |
|
T20 |
9 |
|
T29 |
10 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
882 |
1 |
|
|
T6 |
9 |
|
T20 |
12 |
|
T29 |
11 |
| auto[1] |
938 |
1 |
|
|
T6 |
11 |
|
T20 |
8 |
|
T29 |
9 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
898 |
1 |
|
|
T6 |
11 |
|
T20 |
11 |
|
T29 |
11 |
| auto[1] |
922 |
1 |
|
|
T6 |
9 |
|
T20 |
9 |
|
T29 |
9 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
930 |
1 |
|
|
T6 |
9 |
|
T20 |
11 |
|
T29 |
5 |
| auto[1] |
890 |
1 |
|
|
T6 |
11 |
|
T20 |
9 |
|
T29 |
15 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
938 |
1 |
|
|
T6 |
12 |
|
T20 |
7 |
|
T29 |
12 |
| auto[1] |
882 |
1 |
|
|
T6 |
8 |
|
T20 |
13 |
|
T29 |
8 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
920 |
1 |
|
|
T6 |
12 |
|
T20 |
10 |
|
T29 |
10 |
| auto[1] |
900 |
1 |
|
|
T6 |
8 |
|
T20 |
10 |
|
T29 |
10 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
893 |
1 |
|
|
T6 |
11 |
|
T20 |
10 |
|
T29 |
7 |
| auto[1] |
927 |
1 |
|
|
T6 |
9 |
|
T20 |
10 |
|
T29 |
13 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
899 |
1 |
|
|
T6 |
13 |
|
T20 |
11 |
|
T29 |
12 |
| auto[1] |
921 |
1 |
|
|
T6 |
7 |
|
T20 |
9 |
|
T29 |
8 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
909 |
1 |
|
|
T6 |
12 |
|
T20 |
7 |
|
T29 |
10 |
| auto[1] |
911 |
1 |
|
|
T6 |
8 |
|
T20 |
13 |
|
T29 |
10 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
914 |
1 |
|
|
T6 |
11 |
|
T20 |
8 |
|
T29 |
9 |
| auto[1] |
906 |
1 |
|
|
T6 |
9 |
|
T20 |
12 |
|
T29 |
11 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
904 |
1 |
|
|
T6 |
11 |
|
T20 |
9 |
|
T29 |
8 |
| auto[1] |
916 |
1 |
|
|
T6 |
9 |
|
T20 |
11 |
|
T29 |
12 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
929 |
1 |
|
|
T6 |
8 |
|
T20 |
11 |
|
T29 |
10 |
| auto[1] |
891 |
1 |
|
|
T6 |
12 |
|
T20 |
9 |
|
T29 |
10 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
894 |
1 |
|
|
T6 |
7 |
|
T20 |
7 |
|
T29 |
11 |
| auto[1] |
926 |
1 |
|
|
T6 |
13 |
|
T20 |
13 |
|
T29 |
9 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
879 |
1 |
|
|
T6 |
14 |
|
T20 |
7 |
|
T29 |
9 |
| auto[1] |
941 |
1 |
|
|
T6 |
6 |
|
T20 |
13 |
|
T29 |
11 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
893 |
1 |
|
|
T6 |
8 |
|
T20 |
6 |
|
T29 |
13 |
| auto[1] |
927 |
1 |
|
|
T6 |
12 |
|
T20 |
14 |
|
T29 |
7 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
918 |
1 |
|
|
T6 |
11 |
|
T20 |
6 |
|
T29 |
12 |
| auto[1] |
902 |
1 |
|
|
T6 |
9 |
|
T20 |
14 |
|
T29 |
8 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
892 |
1 |
|
|
T6 |
10 |
|
T20 |
10 |
|
T29 |
9 |
| auto[1] |
928 |
1 |
|
|
T6 |
10 |
|
T20 |
10 |
|
T29 |
11 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
943 |
1 |
|
|
T6 |
10 |
|
T20 |
10 |
|
T29 |
12 |
| auto[1] |
877 |
1 |
|
|
T6 |
10 |
|
T20 |
10 |
|
T29 |
8 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
933 |
1 |
|
|
T6 |
9 |
|
T20 |
11 |
|
T29 |
13 |
| auto[1] |
887 |
1 |
|
|
T6 |
11 |
|
T20 |
9 |
|
T29 |
7 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
907 |
1 |
|
|
T6 |
9 |
|
T20 |
14 |
|
T29 |
8 |
| auto[1] |
913 |
1 |
|
|
T6 |
11 |
|
T20 |
6 |
|
T29 |
12 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
909 |
1 |
|
|
T6 |
12 |
|
T20 |
7 |
|
T29 |
10 |
| auto[1] |
911 |
1 |
|
|
T6 |
8 |
|
T20 |
13 |
|
T29 |
10 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
497 |
1 |
|
|
T6 |
6 |
|
T20 |
5 |
|
T29 |
1 |
| auto[0] |
auto[1] |
432 |
1 |
|
|
T6 |
2 |
|
T20 |
6 |
|
T29 |
9 |
| auto[1] |
auto[0] |
444 |
1 |
|
|
T6 |
5 |
|
T20 |
6 |
|
T29 |
4 |
| auto[1] |
auto[1] |
447 |
1 |
|
|
T6 |
7 |
|
T20 |
3 |
|
T29 |
6 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
464 |
1 |
|
|
T6 |
4 |
|
T20 |
3 |
|
T29 |
4 |
| auto[0] |
auto[1] |
430 |
1 |
|
|
T6 |
3 |
|
T20 |
4 |
|
T29 |
7 |
| auto[1] |
auto[0] |
446 |
1 |
|
|
T6 |
4 |
|
T20 |
8 |
|
T29 |
6 |
| auto[1] |
auto[1] |
480 |
1 |
|
|
T6 |
9 |
|
T20 |
5 |
|
T29 |
3 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
409 |
1 |
|
|
T6 |
6 |
|
T20 |
5 |
|
T29 |
6 |
| auto[0] |
auto[1] |
470 |
1 |
|
|
T6 |
8 |
|
T20 |
2 |
|
T29 |
3 |
| auto[1] |
auto[0] |
473 |
1 |
|
|
T6 |
3 |
|
T20 |
7 |
|
T29 |
5 |
| auto[1] |
auto[1] |
468 |
1 |
|
|
T6 |
3 |
|
T20 |
6 |
|
T29 |
6 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
424 |
1 |
|
|
T6 |
4 |
|
T20 |
4 |
|
T29 |
8 |
| auto[0] |
auto[1] |
469 |
1 |
|
|
T6 |
4 |
|
T20 |
2 |
|
T29 |
5 |
| auto[1] |
auto[0] |
474 |
1 |
|
|
T6 |
7 |
|
T20 |
7 |
|
T29 |
3 |
| auto[1] |
auto[1] |
453 |
1 |
|
|
T6 |
5 |
|
T20 |
7 |
|
T29 |
4 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
470 |
1 |
|
|
T6 |
7 |
|
T20 |
2 |
|
T29 |
1 |
| auto[0] |
auto[1] |
448 |
1 |
|
|
T6 |
4 |
|
T20 |
4 |
|
T29 |
11 |
| auto[1] |
auto[0] |
460 |
1 |
|
|
T6 |
2 |
|
T20 |
9 |
|
T29 |
4 |
| auto[1] |
auto[1] |
442 |
1 |
|
|
T6 |
7 |
|
T20 |
5 |
|
T29 |
4 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
461 |
1 |
|
|
T6 |
8 |
|
T20 |
2 |
|
T29 |
3 |
| auto[0] |
auto[1] |
431 |
1 |
|
|
T6 |
2 |
|
T20 |
8 |
|
T29 |
6 |
| auto[1] |
auto[0] |
477 |
1 |
|
|
T6 |
4 |
|
T20 |
5 |
|
T29 |
9 |
| auto[1] |
auto[1] |
451 |
1 |
|
|
T6 |
6 |
|
T20 |
5 |
|
T29 |
2 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
472 |
1 |
|
|
T6 |
4 |
|
T20 |
5 |
|
T29 |
5 |
| auto[0] |
auto[1] |
461 |
1 |
|
|
T6 |
5 |
|
T20 |
6 |
|
T29 |
8 |
| auto[1] |
auto[0] |
421 |
1 |
|
|
T6 |
7 |
|
T20 |
5 |
|
T29 |
2 |
| auto[1] |
auto[1] |
466 |
1 |
|
|
T6 |
4 |
|
T20 |
4 |
|
T29 |
5 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
462 |
1 |
|
|
T6 |
5 |
|
T20 |
7 |
|
T29 |
5 |
| auto[0] |
auto[1] |
445 |
1 |
|
|
T6 |
4 |
|
T20 |
7 |
|
T29 |
3 |
| auto[1] |
auto[0] |
437 |
1 |
|
|
T6 |
8 |
|
T20 |
4 |
|
T29 |
7 |
| auto[1] |
auto[1] |
476 |
1 |
|
|
T6 |
3 |
|
T20 |
2 |
|
T29 |
5 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
447 |
1 |
|
|
T6 |
3 |
|
T20 |
5 |
|
T29 |
5 |
| auto[0] |
auto[1] |
467 |
1 |
|
|
T6 |
8 |
|
T20 |
3 |
|
T29 |
4 |
| auto[1] |
auto[0] |
433 |
1 |
|
|
T6 |
3 |
|
T20 |
6 |
|
T29 |
6 |
| auto[1] |
auto[1] |
473 |
1 |
|
|
T6 |
6 |
|
T20 |
6 |
|
T29 |
5 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
904 |
1 |
|
|
T6 |
11 |
|
T20 |
9 |
|
T29 |
8 |
| auto[1] |
auto[1] |
916 |
1 |
|
|
T6 |
9 |
|
T20 |
11 |
|
T29 |
12 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
486 |
1 |
|
|
T6 |
5 |
|
T20 |
6 |
|
T29 |
5 |
| auto[0] |
auto[1] |
457 |
1 |
|
|
T6 |
5 |
|
T20 |
4 |
|
T29 |
7 |
| auto[1] |
auto[0] |
434 |
1 |
|
|
T6 |
7 |
|
T20 |
4 |
|
T29 |
5 |
| auto[1] |
auto[1] |
443 |
1 |
|
|
T6 |
3 |
|
T20 |
6 |
|
T29 |
3 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
909 |
1 |
|
|
T6 |
12 |
|
T20 |
7 |
|
T29 |
10 |
| auto[1] |
auto[1] |
911 |
1 |
|
|
T6 |
8 |
|
T20 |
13 |
|
T29 |
10 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
147 |
1 |
|
|
T38 |
8 |
|
T170 |
10 |
|
T353 |
16 |
| auto[1] |
153 |
1 |
|
|
T38 |
12 |
|
T170 |
10 |
|
T353 |
4 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
149 |
1 |
|
|
T38 |
9 |
|
T170 |
6 |
|
T353 |
8 |
| auto[1] |
151 |
1 |
|
|
T38 |
11 |
|
T170 |
14 |
|
T353 |
12 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
143 |
1 |
|
|
T38 |
9 |
|
T170 |
13 |
|
T353 |
7 |
| auto[1] |
157 |
1 |
|
|
T38 |
11 |
|
T170 |
7 |
|
T353 |
13 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
153 |
1 |
|
|
T38 |
13 |
|
T170 |
12 |
|
T353 |
11 |
| auto[1] |
147 |
1 |
|
|
T38 |
7 |
|
T170 |
8 |
|
T353 |
9 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
141 |
1 |
|
|
T38 |
10 |
|
T170 |
11 |
|
T353 |
10 |
| auto[1] |
159 |
1 |
|
|
T38 |
10 |
|
T170 |
9 |
|
T353 |
10 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
161 |
1 |
|
|
T38 |
11 |
|
T170 |
10 |
|
T353 |
11 |
| auto[1] |
139 |
1 |
|
|
T38 |
9 |
|
T170 |
10 |
|
T353 |
9 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
159 |
1 |
|
|
T38 |
10 |
|
T170 |
12 |
|
T353 |
9 |
| auto[1] |
141 |
1 |
|
|
T38 |
10 |
|
T170 |
8 |
|
T353 |
11 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
142 |
1 |
|
|
T38 |
9 |
|
T170 |
9 |
|
T353 |
6 |
| auto[1] |
158 |
1 |
|
|
T38 |
11 |
|
T170 |
11 |
|
T353 |
14 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
148 |
1 |
|
|
T38 |
12 |
|
T170 |
12 |
|
T353 |
11 |
| auto[1] |
152 |
1 |
|
|
T38 |
8 |
|
T170 |
8 |
|
T353 |
9 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
148 |
1 |
|
|
T38 |
7 |
|
T170 |
10 |
|
T353 |
9 |
| auto[1] |
152 |
1 |
|
|
T38 |
13 |
|
T170 |
10 |
|
T353 |
11 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
164 |
1 |
|
|
T38 |
10 |
|
T170 |
10 |
|
T353 |
13 |
| auto[1] |
136 |
1 |
|
|
T38 |
10 |
|
T170 |
10 |
|
T353 |
7 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
138 |
1 |
|
|
T38 |
7 |
|
T170 |
10 |
|
T353 |
9 |
| auto[1] |
162 |
1 |
|
|
T38 |
13 |
|
T170 |
10 |
|
T353 |
11 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
146 |
1 |
|
|
T38 |
8 |
|
T170 |
11 |
|
T353 |
10 |
| auto[1] |
154 |
1 |
|
|
T38 |
12 |
|
T170 |
9 |
|
T353 |
10 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
149 |
1 |
|
|
T38 |
9 |
|
T170 |
6 |
|
T353 |
8 |
| auto[1] |
151 |
1 |
|
|
T38 |
11 |
|
T170 |
14 |
|
T353 |
12 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
158 |
1 |
|
|
T38 |
10 |
|
T170 |
12 |
|
T353 |
10 |
| auto[1] |
142 |
1 |
|
|
T38 |
10 |
|
T170 |
8 |
|
T353 |
10 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
144 |
1 |
|
|
T38 |
12 |
|
T170 |
11 |
|
T353 |
12 |
| auto[1] |
156 |
1 |
|
|
T38 |
8 |
|
T170 |
9 |
|
T353 |
8 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
165 |
1 |
|
|
T38 |
16 |
|
T170 |
12 |
|
T353 |
9 |
| auto[1] |
135 |
1 |
|
|
T38 |
4 |
|
T170 |
8 |
|
T353 |
11 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
163 |
1 |
|
|
T38 |
11 |
|
T170 |
9 |
|
T353 |
14 |
| auto[1] |
137 |
1 |
|
|
T38 |
9 |
|
T170 |
11 |
|
T353 |
6 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
154 |
1 |
|
|
T38 |
7 |
|
T170 |
8 |
|
T353 |
11 |
| auto[1] |
146 |
1 |
|
|
T38 |
13 |
|
T170 |
12 |
|
T353 |
9 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
133 |
1 |
|
|
T38 |
14 |
|
T170 |
9 |
|
T353 |
10 |
| auto[1] |
167 |
1 |
|
|
T38 |
6 |
|
T170 |
11 |
|
T353 |
10 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
162 |
1 |
|
|
T38 |
15 |
|
T170 |
15 |
|
T353 |
9 |
| auto[1] |
138 |
1 |
|
|
T38 |
5 |
|
T170 |
5 |
|
T353 |
11 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
169 |
1 |
|
|
T38 |
12 |
|
T170 |
11 |
|
T353 |
16 |
| auto[1] |
131 |
1 |
|
|
T38 |
8 |
|
T170 |
9 |
|
T353 |
4 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
147 |
1 |
|
|
T38 |
13 |
|
T170 |
7 |
|
T353 |
8 |
| auto[1] |
153 |
1 |
|
|
T38 |
7 |
|
T170 |
13 |
|
T353 |
12 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
138 |
1 |
|
|
T38 |
7 |
|
T170 |
10 |
|
T353 |
9 |
| auto[1] |
162 |
1 |
|
|
T38 |
13 |
|
T170 |
10 |
|
T353 |
11 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
72 |
1 |
|
|
T38 |
5 |
|
T170 |
8 |
|
T353 |
2 |
| auto[0] |
auto[1] |
86 |
1 |
|
|
T38 |
5 |
|
T170 |
4 |
|
T353 |
8 |
| auto[1] |
auto[0] |
71 |
1 |
|
|
T38 |
4 |
|
T170 |
5 |
|
T353 |
5 |
| auto[1] |
auto[1] |
71 |
1 |
|
|
T38 |
6 |
|
T170 |
3 |
|
T353 |
5 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
70 |
1 |
|
|
T38 |
8 |
|
T170 |
7 |
|
T353 |
5 |
| auto[0] |
auto[1] |
74 |
1 |
|
|
T38 |
4 |
|
T170 |
4 |
|
T353 |
7 |
| auto[1] |
auto[0] |
83 |
1 |
|
|
T38 |
5 |
|
T170 |
5 |
|
T353 |
6 |
| auto[1] |
auto[1] |
73 |
1 |
|
|
T38 |
3 |
|
T170 |
4 |
|
T353 |
2 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
75 |
1 |
|
|
T38 |
10 |
|
T170 |
6 |
|
T353 |
3 |
| auto[0] |
auto[1] |
90 |
1 |
|
|
T38 |
6 |
|
T170 |
6 |
|
T353 |
6 |
| auto[1] |
auto[0] |
66 |
1 |
|
|
T170 |
5 |
|
T353 |
7 |
|
T349 |
4 |
| auto[1] |
auto[1] |
69 |
1 |
|
|
T38 |
4 |
|
T170 |
3 |
|
T353 |
4 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
84 |
1 |
|
|
T38 |
8 |
|
T170 |
4 |
|
T353 |
6 |
| auto[0] |
auto[1] |
79 |
1 |
|
|
T38 |
3 |
|
T170 |
5 |
|
T353 |
8 |
| auto[1] |
auto[0] |
77 |
1 |
|
|
T38 |
3 |
|
T170 |
6 |
|
T353 |
5 |
| auto[1] |
auto[1] |
60 |
1 |
|
|
T38 |
6 |
|
T170 |
5 |
|
T353 |
1 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
80 |
1 |
|
|
T38 |
3 |
|
T170 |
4 |
|
T353 |
5 |
| auto[0] |
auto[1] |
74 |
1 |
|
|
T38 |
4 |
|
T170 |
4 |
|
T353 |
6 |
| auto[1] |
auto[0] |
79 |
1 |
|
|
T38 |
7 |
|
T170 |
8 |
|
T353 |
4 |
| auto[1] |
auto[1] |
67 |
1 |
|
|
T38 |
6 |
|
T170 |
4 |
|
T353 |
5 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
61 |
1 |
|
|
T38 |
6 |
|
T170 |
3 |
|
T353 |
3 |
| auto[0] |
auto[1] |
72 |
1 |
|
|
T38 |
8 |
|
T170 |
6 |
|
T353 |
7 |
| auto[1] |
auto[0] |
81 |
1 |
|
|
T38 |
3 |
|
T170 |
6 |
|
T353 |
3 |
| auto[1] |
auto[1] |
86 |
1 |
|
|
T38 |
3 |
|
T170 |
5 |
|
T353 |
7 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
77 |
1 |
|
|
T38 |
5 |
|
T170 |
6 |
|
T353 |
5 |
| auto[0] |
auto[1] |
92 |
1 |
|
|
T38 |
7 |
|
T170 |
5 |
|
T353 |
11 |
| auto[1] |
auto[0] |
71 |
1 |
|
|
T38 |
2 |
|
T170 |
4 |
|
T353 |
4 |
| auto[1] |
auto[1] |
60 |
1 |
|
|
T38 |
6 |
|
T170 |
5 |
|
T349 |
4 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
74 |
1 |
|
|
T38 |
7 |
|
T170 |
4 |
|
T353 |
3 |
| auto[0] |
auto[1] |
73 |
1 |
|
|
T38 |
6 |
|
T170 |
3 |
|
T353 |
5 |
| auto[1] |
auto[0] |
90 |
1 |
|
|
T38 |
3 |
|
T170 |
6 |
|
T353 |
10 |
| auto[1] |
auto[1] |
63 |
1 |
|
|
T38 |
4 |
|
T170 |
7 |
|
T353 |
2 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
65 |
1 |
|
|
T38 |
3 |
|
T170 |
6 |
|
T353 |
8 |
| auto[0] |
auto[1] |
81 |
1 |
|
|
T38 |
5 |
|
T170 |
5 |
|
T353 |
2 |
| auto[1] |
auto[0] |
82 |
1 |
|
|
T38 |
5 |
|
T170 |
4 |
|
T353 |
8 |
| auto[1] |
auto[1] |
72 |
1 |
|
|
T38 |
7 |
|
T170 |
5 |
|
T353 |
2 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
149 |
1 |
|
|
T38 |
9 |
|
T170 |
6 |
|
T353 |
8 |
| auto[1] |
auto[1] |
151 |
1 |
|
|
T38 |
11 |
|
T170 |
14 |
|
T353 |
12 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
82 |
1 |
|
|
T38 |
10 |
|
T170 |
10 |
|
T353 |
6 |
| auto[0] |
auto[1] |
80 |
1 |
|
|
T38 |
5 |
|
T170 |
5 |
|
T353 |
3 |
| auto[1] |
auto[0] |
66 |
1 |
|
|
T38 |
2 |
|
T170 |
2 |
|
T353 |
5 |
| auto[1] |
auto[1] |
72 |
1 |
|
|
T38 |
3 |
|
T170 |
3 |
|
T353 |
6 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
138 |
1 |
|
|
T38 |
7 |
|
T170 |
10 |
|
T353 |
9 |
| auto[1] |
auto[1] |
162 |
1 |
|
|
T38 |
13 |
|
T170 |
10 |
|
T353 |
11 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
50 |
1 |
|
|
T38 |
10 |
|
T170 |
10 |
|
T354 |
10 |
| auto[1] |
50 |
1 |
|
|
T38 |
10 |
|
T170 |
10 |
|
T354 |
10 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
55 |
1 |
|
|
T38 |
10 |
|
T170 |
12 |
|
T354 |
10 |
| auto[1] |
45 |
1 |
|
|
T38 |
10 |
|
T170 |
8 |
|
T354 |
10 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
54 |
1 |
|
|
T38 |
12 |
|
T170 |
11 |
|
T354 |
11 |
| auto[1] |
46 |
1 |
|
|
T38 |
8 |
|
T170 |
9 |
|
T354 |
9 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
53 |
1 |
|
|
T38 |
9 |
|
T170 |
12 |
|
T354 |
13 |
| auto[1] |
47 |
1 |
|
|
T38 |
11 |
|
T170 |
8 |
|
T354 |
7 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
51 |
1 |
|
|
T38 |
11 |
|
T170 |
12 |
|
T354 |
6 |
| auto[1] |
49 |
1 |
|
|
T38 |
9 |
|
T170 |
8 |
|
T354 |
14 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
58 |
1 |
|
|
T38 |
12 |
|
T170 |
11 |
|
T354 |
12 |
| auto[1] |
42 |
1 |
|
|
T38 |
8 |
|
T170 |
9 |
|
T354 |
8 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
53 |
1 |
|
|
T38 |
13 |
|
T170 |
11 |
|
T354 |
9 |
| auto[1] |
47 |
1 |
|
|
T38 |
7 |
|
T170 |
9 |
|
T354 |
11 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
46 |
1 |
|
|
T38 |
4 |
|
T170 |
9 |
|
T354 |
7 |
| auto[1] |
54 |
1 |
|
|
T38 |
16 |
|
T170 |
11 |
|
T354 |
13 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
50 |
1 |
|
|
T38 |
12 |
|
T170 |
10 |
|
T354 |
8 |
| auto[1] |
50 |
1 |
|
|
T38 |
8 |
|
T170 |
10 |
|
T354 |
12 |