Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.46 99.29 96.36 100.00 95.51 98.78 99.33 92.96


Total tests in report: 912
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
57.29 57.29 79.25 79.25 65.85 65.85 65.64 65.64 21.79 21.79 79.78 79.78 69.36 69.36 19.35 19.35 /workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.197762338
74.68 17.39 89.55 10.30 77.98 12.13 67.01 1.37 62.18 40.38 89.61 9.83 88.82 19.46 47.57 28.22 /workspace/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.1310127652
80.83 6.16 91.04 1.49 80.69 2.70 92.12 25.11 71.15 8.97 90.98 1.37 91.81 2.99 48.02 0.46 /workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.1189620700
84.01 3.18 94.83 3.79 87.84 7.15 93.04 0.91 73.72 2.56 94.86 3.88 94.12 2.31 49.65 1.62 /workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.3541330273
85.95 1.95 94.89 0.06 88.07 0.23 93.49 0.46 73.72 0.00 94.94 0.07 94.41 0.29 62.16 12.51 /workspace/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.3591883479
87.88 1.93 95.97 1.08 89.74 1.67 93.49 0.00 83.33 9.62 96.08 1.15 94.41 0.00 62.16 0.00 /workspace/coverage/default/1.sysrst_ctrl_feature_disable.3498466419
89.50 1.62 97.48 1.51 91.71 1.97 96.92 3.42 83.97 0.64 97.41 1.33 95.86 1.45 63.17 1.01 /workspace/coverage/default/1.sysrst_ctrl_auto_blk_key_output.1686318984
90.63 1.13 97.70 0.22 92.06 0.35 96.92 0.00 86.54 2.56 97.60 0.18 96.72 0.87 66.87 3.70 /workspace/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.711301770
91.76 1.13 97.78 0.07 93.30 1.24 97.60 0.68 86.54 0.00 97.71 0.11 96.82 0.10 72.54 5.67 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.4098325279
92.59 0.84 98.00 0.22 93.43 0.13 98.17 0.57 86.54 0.00 97.74 0.04 97.01 0.19 77.25 4.71 /workspace/coverage/default/30.sysrst_ctrl_stress_all.3241888542
93.12 0.53 98.15 0.15 93.58 0.15 98.17 0.00 87.18 0.64 97.78 0.04 97.11 0.10 79.89 2.63 /workspace/coverage/default/12.sysrst_ctrl_combo_detect.744913743
93.62 0.50 98.36 0.21 93.68 0.10 98.17 0.00 89.74 2.56 97.93 0.15 97.50 0.39 79.99 0.10 /workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.2660284580
93.96 0.34 98.36 0.00 93.68 0.00 98.17 0.00 89.74 0.00 97.93 0.00 97.50 0.00 82.37 2.38 /workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.3216003373
94.29 0.32 98.56 0.21 94.11 0.43 98.17 0.00 89.74 0.00 97.93 0.00 97.50 0.00 83.99 1.62 /workspace/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.4081419910
94.58 0.30 98.68 0.11 94.26 0.15 98.17 0.00 90.38 0.64 98.11 0.18 97.88 0.39 84.60 0.61 /workspace/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.2193783379
94.87 0.28 98.69 0.02 94.29 0.03 98.17 0.00 91.03 0.64 98.15 0.04 97.88 0.00 85.87 1.27 /workspace/coverage/default/28.sysrst_ctrl_stress_all.981655672
95.15 0.28 98.69 0.00 94.31 0.03 99.77 1.60 91.03 0.00 98.15 0.00 97.98 0.10 86.12 0.25 /workspace/coverage/default/0.sysrst_ctrl_sec_cm.4105753187
95.40 0.25 98.77 0.07 94.36 0.05 99.77 0.00 92.31 1.28 98.23 0.07 98.17 0.19 86.17 0.05 /workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.1734222635
95.64 0.24 98.84 0.07 94.41 0.05 99.77 0.00 93.59 1.28 98.30 0.07 98.36 0.19 86.17 0.00 /workspace/coverage/default/46.sysrst_ctrl_edge_detect.2902660387
95.85 0.21 98.84 0.00 94.41 0.00 99.77 0.00 93.59 0.00 98.30 0.00 98.94 0.58 87.08 0.91 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.1785273633
96.03 0.18 98.88 0.04 94.44 0.03 99.77 0.00 94.23 0.64 98.34 0.04 99.04 0.10 87.54 0.46 /workspace/coverage/default/7.sysrst_ctrl_stress_all.836871865
96.21 0.17 98.94 0.06 94.49 0.05 99.77 0.00 94.23 0.00 98.34 0.00 99.04 0.00 88.65 1.11 /workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.3951943228
96.35 0.14 98.94 0.00 95.17 0.68 99.77 0.00 94.23 0.00 98.34 0.00 99.04 0.00 88.96 0.30 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.2270606610
96.47 0.12 98.96 0.02 95.17 0.00 99.77 0.00 94.87 0.64 98.37 0.04 99.04 0.00 89.11 0.15 /workspace/coverage/default/31.sysrst_ctrl_combo_detect.2475113364
96.59 0.12 98.99 0.04 95.20 0.03 99.77 0.00 95.51 0.64 98.41 0.04 99.13 0.10 89.11 0.00 /workspace/coverage/default/5.sysrst_ctrl_edge_detect.3567309323
96.67 0.08 99.03 0.04 95.20 0.00 99.77 0.00 95.51 0.00 98.41 0.00 99.13 0.00 89.67 0.56 /workspace/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.3171522996
96.76 0.08 99.07 0.04 95.48 0.28 99.77 0.00 95.51 0.00 98.48 0.07 99.33 0.19 89.67 0.00 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.3257546101
96.83 0.08 99.09 0.02 95.48 0.00 99.77 0.00 95.51 0.00 98.48 0.00 99.33 0.00 90.17 0.51 /workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.3083173693
96.89 0.06 99.14 0.06 95.58 0.10 100.00 0.23 95.51 0.00 98.52 0.04 99.33 0.00 90.17 0.00 /workspace/coverage/default/41.sysrst_ctrl_alert_test.4161744630
96.94 0.05 99.14 0.00 95.58 0.00 100.00 0.00 95.51 0.00 98.52 0.00 99.33 0.00 90.53 0.35 /workspace/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.1884398866
96.99 0.05 99.14 0.00 95.88 0.30 100.00 0.00 95.51 0.00 98.52 0.00 99.33 0.00 90.58 0.05 /workspace/coverage/default/12.sysrst_ctrl_ultra_low_pwr.9855397
97.04 0.05 99.14 0.00 95.90 0.03 100.00 0.00 95.51 0.00 98.52 0.00 99.33 0.00 90.88 0.30 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.4123562377
97.08 0.04 99.14 0.00 96.18 0.28 100.00 0.00 95.51 0.00 98.52 0.00 99.33 0.00 90.88 0.00 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.608673276
97.12 0.04 99.14 0.00 96.18 0.00 100.00 0.00 95.51 0.00 98.52 0.00 99.33 0.00 91.13 0.25 /workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.2573903070
97.14 0.02 99.14 0.00 96.18 0.00 100.00 0.00 95.51 0.00 98.52 0.00 99.33 0.00 91.29 0.15 /workspace/coverage/default/2.sysrst_ctrl_auto_blk_key_output.475723480
97.16 0.02 99.14 0.00 96.18 0.00 100.00 0.00 95.51 0.00 98.52 0.00 99.33 0.00 91.44 0.15 /workspace/coverage/default/26.sysrst_ctrl_combo_detect.1965843821
97.18 0.02 99.14 0.00 96.18 0.00 100.00 0.00 95.51 0.00 98.52 0.00 99.33 0.00 91.59 0.15 /workspace/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.3666663461
97.20 0.02 99.14 0.00 96.18 0.00 100.00 0.00 95.51 0.00 98.52 0.00 99.33 0.00 91.74 0.15 /workspace/coverage/default/40.sysrst_ctrl_combo_detect.2338196832
97.23 0.02 99.14 0.00 96.18 0.00 100.00 0.00 95.51 0.00 98.52 0.00 99.33 0.00 91.89 0.15 /workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.3802261230
97.24 0.02 99.18 0.04 96.18 0.00 100.00 0.00 95.51 0.00 98.60 0.07 99.33 0.00 91.89 0.00 /workspace/coverage/default/12.sysrst_ctrl_edge_detect.208147672
97.26 0.02 99.20 0.02 96.18 0.00 100.00 0.00 95.51 0.00 98.63 0.04 99.33 0.00 91.95 0.05 /workspace/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.266661739
97.27 0.01 99.20 0.00 96.18 0.00 100.00 0.00 95.51 0.00 98.63 0.00 99.33 0.00 92.05 0.10 /workspace/coverage/default/34.sysrst_ctrl_combo_detect.1197417230
97.29 0.01 99.20 0.00 96.18 0.00 100.00 0.00 95.51 0.00 98.63 0.00 99.33 0.00 92.15 0.10 /workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.494289736
97.30 0.01 99.20 0.00 96.18 0.00 100.00 0.00 95.51 0.00 98.63 0.00 99.33 0.00 92.25 0.10 /workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.726961826
97.31 0.01 99.20 0.00 96.21 0.03 100.00 0.00 95.51 0.00 98.63 0.00 99.33 0.00 92.30 0.05 /workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.1701813794
97.32 0.01 99.22 0.02 96.21 0.00 100.00 0.00 95.51 0.00 98.63 0.00 99.33 0.00 92.35 0.05 /workspace/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.854022616
97.33 0.01 99.23 0.02 96.21 0.00 100.00 0.00 95.51 0.00 98.67 0.04 99.33 0.00 92.35 0.00 /workspace/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.3127718678
97.34 0.01 99.25 0.02 96.21 0.00 100.00 0.00 95.51 0.00 98.71 0.04 99.33 0.00 92.35 0.00 /workspace/coverage/default/15.sysrst_ctrl_stress_all.62756474
97.34 0.01 99.27 0.02 96.21 0.00 100.00 0.00 95.51 0.00 98.74 0.04 99.33 0.00 92.35 0.00 /workspace/coverage/default/31.sysrst_ctrl_edge_detect.1701333458
97.35 0.01 99.29 0.02 96.21 0.00 100.00 0.00 95.51 0.00 98.78 0.04 99.33 0.00 92.35 0.00 /workspace/coverage/default/38.sysrst_ctrl_edge_detect.585093908
97.36 0.01 99.29 0.00 96.21 0.00 100.00 0.00 95.51 0.00 98.78 0.00 99.33 0.00 92.40 0.05 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.3921255836
97.37 0.01 99.29 0.00 96.21 0.00 100.00 0.00 95.51 0.00 98.78 0.00 99.33 0.00 92.45 0.05 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.1036613589
97.37 0.01 99.29 0.00 96.21 0.00 100.00 0.00 95.51 0.00 98.78 0.00 99.33 0.00 92.50 0.05 /workspace/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.4088860239
97.38 0.01 99.29 0.00 96.21 0.00 100.00 0.00 95.51 0.00 98.78 0.00 99.33 0.00 92.55 0.05 /workspace/coverage/default/0.sysrst_ctrl_pin_override_test.1442054213
97.39 0.01 99.29 0.00 96.21 0.00 100.00 0.00 95.51 0.00 98.78 0.00 99.33 0.00 92.60 0.05 /workspace/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.687537606
97.40 0.01 99.29 0.00 96.21 0.00 100.00 0.00 95.51 0.00 98.78 0.00 99.33 0.00 92.65 0.05 /workspace/coverage/default/28.sysrst_ctrl_combo_detect.3786983659
97.40 0.01 99.29 0.00 96.21 0.00 100.00 0.00 95.51 0.00 98.78 0.00 99.33 0.00 92.71 0.05 /workspace/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.1455497208
97.41 0.01 99.29 0.00 96.21 0.00 100.00 0.00 95.51 0.00 98.78 0.00 99.33 0.00 92.76 0.05 /workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.1490591652
97.42 0.01 99.29 0.00 96.21 0.00 100.00 0.00 95.51 0.00 98.78 0.00 99.33 0.00 92.81 0.05 /workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.1510307358
97.42 0.01 99.29 0.00 96.21 0.00 100.00 0.00 95.51 0.00 98.78 0.00 99.33 0.00 92.86 0.05 /workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.1708414440
97.43 0.01 99.29 0.00 96.21 0.00 100.00 0.00 95.51 0.00 98.78 0.00 99.33 0.00 92.91 0.05 /workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.1930009271
97.44 0.01 99.29 0.00 96.21 0.00 100.00 0.00 95.51 0.00 98.78 0.00 99.33 0.00 92.96 0.05 /workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.3517607118
97.45 0.01 99.29 0.00 96.26 0.05 100.00 0.00 95.51 0.00 98.78 0.00 99.33 0.00 92.96 0.00 /workspace/coverage/default/0.sysrst_ctrl_feature_disable.4285760303
97.45 0.01 99.29 0.00 96.28 0.03 100.00 0.00 95.51 0.00 98.78 0.00 99.33 0.00 92.96 0.00 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.22124959
97.45 0.01 99.29 0.00 96.31 0.03 100.00 0.00 95.51 0.00 98.78 0.00 99.33 0.00 92.96 0.00 /workspace/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.4103192424
97.46 0.01 99.29 0.00 96.33 0.03 100.00 0.00 95.51 0.00 98.78 0.00 99.33 0.00 92.96 0.00 /workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.2169484223

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.3893922044
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.2140015145
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.2980692626
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.2182077880
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.2066844090
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.3057363213
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.3042589791
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.468816600
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.1546116361
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.152051207
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.388168665
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.1253488720
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.2758634282
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.3991241629
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.15170768
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.1708204422
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.3736692506
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.3746852487
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.1410113108
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.2096078526
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.3621326294
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.2945751055
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.918315110
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.653975029
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.4208933946
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.4189560573
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.3129129393
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.1497491250
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.1160467097
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.1128658564
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.3432486423
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.1965012107
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.1652630806
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.4163540858
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.2820094676
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.1725195745
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.2231449597
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.2708425806
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.73279559
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.2386985072
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.1700372475
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.1130872912
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.210140874
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.2309802993
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.78321517
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.63334260
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.776916380
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.2613360966
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.44262996
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.3351777802
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.2461615533
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.3797356721
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.2171143102
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.4287722040
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.203868283
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.1907181477
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.3020822866
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.3577881471
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.2143847151
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.3923264766
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.2514767718
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.1421544644
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.2251378599
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.2052831597
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.1869397342
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.3500349736
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.1067035107
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.1862972913
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.970722235
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.3519309342
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.2035239200
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.1831100015
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.3427573732
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.1721238466
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.3541122587
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.3835258113
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.405175060
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.1631155840
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.4046071366
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.208190143
/workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.1101056726
/workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.4073023415
/workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.1234106335
/workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.1845130944
/workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.95749916
/workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.2895168612
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/workspace/coverage/default/42.sysrst_ctrl_alert_test.3373103035
/workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.3277532562
/workspace/coverage/default/42.sysrst_ctrl_combo_detect.3702483693
/workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.3936098410
/workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.2119967267
/workspace/coverage/default/42.sysrst_ctrl_edge_detect.2563280977
/workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.1724814894
/workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.2979304627
/workspace/coverage/default/42.sysrst_ctrl_pin_access_test.3698799263
/workspace/coverage/default/42.sysrst_ctrl_pin_override_test.2393969044
/workspace/coverage/default/42.sysrst_ctrl_smoke.707754962
/workspace/coverage/default/42.sysrst_ctrl_stress_all.431020625
/workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.995457582
/workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.13841362
/workspace/coverage/default/43.sysrst_ctrl_alert_test.1593215136
/workspace/coverage/default/43.sysrst_ctrl_combo_detect.3147076605
/workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.50093002
/workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.3480137273
/workspace/coverage/default/43.sysrst_ctrl_edge_detect.2695091337
/workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.3615279642
/workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.1970252693
/workspace/coverage/default/43.sysrst_ctrl_pin_access_test.1202948903
/workspace/coverage/default/43.sysrst_ctrl_pin_override_test.4115063273
/workspace/coverage/default/43.sysrst_ctrl_smoke.1973209507
/workspace/coverage/default/43.sysrst_ctrl_stress_all.4001353823
/workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.3428390747
/workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.939758031
/workspace/coverage/default/44.sysrst_ctrl_alert_test.2123814960
/workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.2437585891
/workspace/coverage/default/44.sysrst_ctrl_combo_detect.1841338432
/workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.2039250454
/workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.4025160783
/workspace/coverage/default/44.sysrst_ctrl_edge_detect.784107779
/workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.4253074701
/workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.587700680
/workspace/coverage/default/44.sysrst_ctrl_pin_access_test.3590414060
/workspace/coverage/default/44.sysrst_ctrl_pin_override_test.1526032543
/workspace/coverage/default/44.sysrst_ctrl_smoke.2700260143
/workspace/coverage/default/44.sysrst_ctrl_stress_all.356491884
/workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.2488098816
/workspace/coverage/default/45.sysrst_ctrl_alert_test.1560747422
/workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.4257753299
/workspace/coverage/default/45.sysrst_ctrl_combo_detect.1962654159
/workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.805272074
/workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.2020919775
/workspace/coverage/default/45.sysrst_ctrl_edge_detect.2067908185
/workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.1709901370
/workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.3370260423
/workspace/coverage/default/45.sysrst_ctrl_pin_access_test.568020043
/workspace/coverage/default/45.sysrst_ctrl_pin_override_test.1940929179
/workspace/coverage/default/45.sysrst_ctrl_smoke.1040444053
/workspace/coverage/default/45.sysrst_ctrl_stress_all.2328017807
/workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.3413703331
/workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.1813078851
/workspace/coverage/default/46.sysrst_ctrl_alert_test.4022824294
/workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.1281414
/workspace/coverage/default/46.sysrst_ctrl_combo_detect.3419900004
/workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.1321609333
/workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.140846825
/workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.678810220
/workspace/coverage/default/46.sysrst_ctrl_pin_access_test.2852589123
/workspace/coverage/default/46.sysrst_ctrl_pin_override_test.852300183
/workspace/coverage/default/46.sysrst_ctrl_smoke.2188368764
/workspace/coverage/default/46.sysrst_ctrl_stress_all.1334105061
/workspace/coverage/default/47.sysrst_ctrl_alert_test.1626353643
/workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.3957754988
/workspace/coverage/default/47.sysrst_ctrl_combo_detect.749686273
/workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.2501230331
/workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.3039092713
/workspace/coverage/default/47.sysrst_ctrl_edge_detect.2802753457
/workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.2404074106
/workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.468044118
/workspace/coverage/default/47.sysrst_ctrl_pin_access_test.82469674
/workspace/coverage/default/47.sysrst_ctrl_pin_override_test.2344078633
/workspace/coverage/default/47.sysrst_ctrl_smoke.4263367007
/workspace/coverage/default/47.sysrst_ctrl_stress_all.704713984
/workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.3921735527
/workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.191480502
/workspace/coverage/default/48.sysrst_ctrl_alert_test.964842385
/workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.2296280377
/workspace/coverage/default/48.sysrst_ctrl_combo_detect.2700336607
/workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.1256217860
/workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.763557306
/workspace/coverage/default/48.sysrst_ctrl_edge_detect.1571380006
/workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.1376495410
/workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.140888715
/workspace/coverage/default/48.sysrst_ctrl_pin_access_test.3633970727
/workspace/coverage/default/48.sysrst_ctrl_pin_override_test.2103662605
/workspace/coverage/default/48.sysrst_ctrl_smoke.455088327
/workspace/coverage/default/48.sysrst_ctrl_stress_all.3266870044
/workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.2904763835
/workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.471370707
/workspace/coverage/default/49.sysrst_ctrl_alert_test.1825898890
/workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.1931666129
/workspace/coverage/default/49.sysrst_ctrl_combo_detect.3851829869
/workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.2265552963
/workspace/coverage/default/49.sysrst_ctrl_edge_detect.3394333331
/workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.4264137824
/workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.3361886416
/workspace/coverage/default/49.sysrst_ctrl_pin_access_test.1824702292
/workspace/coverage/default/49.sysrst_ctrl_pin_override_test.1695828036
/workspace/coverage/default/49.sysrst_ctrl_smoke.1322717017
/workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.869389570
/workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.881085652
/workspace/coverage/default/5.sysrst_ctrl_alert_test.524025014
/workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.2585953445
/workspace/coverage/default/5.sysrst_ctrl_combo_detect.2990265
/workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.2306617303
/workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.177769644
/workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.3873224732
/workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.2909901794
/workspace/coverage/default/5.sysrst_ctrl_pin_access_test.811818036
/workspace/coverage/default/5.sysrst_ctrl_pin_override_test.3398643602
/workspace/coverage/default/5.sysrst_ctrl_smoke.755200024
/workspace/coverage/default/5.sysrst_ctrl_stress_all.1552376409
/workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.2256145006
/workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.3731939956
/workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.3821397081
/workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.1678420557
/workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.2150590618
/workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.635200755
/workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.788193197
/workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.2454301249
/workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.2873294673
/workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.2856144774
/workspace/coverage/default/6.sysrst_ctrl_alert_test.1916132529
/workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.153627388
/workspace/coverage/default/6.sysrst_ctrl_combo_detect.2934258671
/workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.277262553
/workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.3755495208
/workspace/coverage/default/6.sysrst_ctrl_edge_detect.587102178
/workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.912567620
/workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.2829562874
/workspace/coverage/default/6.sysrst_ctrl_pin_access_test.2730413413
/workspace/coverage/default/6.sysrst_ctrl_pin_override_test.3333166489
/workspace/coverage/default/6.sysrst_ctrl_smoke.3550904195
/workspace/coverage/default/6.sysrst_ctrl_stress_all.1142802426
/workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.3603268927
/workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.3904441906
/workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.1654148302
/workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.2029208602
/workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.1956376854
/workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.1580117751
/workspace/coverage/default/7.sysrst_ctrl_alert_test.782337771
/workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.2020389321
/workspace/coverage/default/7.sysrst_ctrl_combo_detect.125155993
/workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.1742211172
/workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.2753350353
/workspace/coverage/default/7.sysrst_ctrl_edge_detect.2413243066
/workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.2290639388
/workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.2510904422
/workspace/coverage/default/7.sysrst_ctrl_pin_access_test.1338416774
/workspace/coverage/default/7.sysrst_ctrl_pin_override_test.4214028763
/workspace/coverage/default/7.sysrst_ctrl_smoke.1095622430
/workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.1119841864
/workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.1542231431
/workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.3133256187
/workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.4185367939
/workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.3296828225
/workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.1020045924
/workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.3216418552
/workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.1059664244
/workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.596358971
/workspace/coverage/default/8.sysrst_ctrl_alert_test.1811872349
/workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.921259027
/workspace/coverage/default/8.sysrst_ctrl_combo_detect.3028740260
/workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.1718735868
/workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.4176061032
/workspace/coverage/default/8.sysrst_ctrl_edge_detect.60373504
/workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.3984593018
/workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.779288953
/workspace/coverage/default/8.sysrst_ctrl_pin_access_test.3128408959
/workspace/coverage/default/8.sysrst_ctrl_pin_override_test.724267812
/workspace/coverage/default/8.sysrst_ctrl_smoke.2409462205
/workspace/coverage/default/8.sysrst_ctrl_stress_all.2774666082
/workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.1713324735
/workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.2748507581
/workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.3228289811
/workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.375004322
/workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.1080709180
/workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.2230689742
/workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.1415968453
/workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.2456147675
/workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.1260776672
/workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.1440406281
/workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.3399365731
/workspace/coverage/default/9.sysrst_ctrl_alert_test.268912953
/workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.3359809909
/workspace/coverage/default/9.sysrst_ctrl_combo_detect.667725840
/workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.2190791148
/workspace/coverage/default/9.sysrst_ctrl_edge_detect.2175583011
/workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.2348644544
/workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.3451710184
/workspace/coverage/default/9.sysrst_ctrl_pin_access_test.3896095401
/workspace/coverage/default/9.sysrst_ctrl_pin_override_test.2707573933
/workspace/coverage/default/9.sysrst_ctrl_smoke.2580389465
/workspace/coverage/default/9.sysrst_ctrl_stress_all.2373618326
/workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.2697920995
/workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.3005927074
/workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.1395196111
/workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.1083002884
/workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.2067310861
/workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.3577614500



Total test records in report: 912
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T4 /workspace/coverage/default/20.sysrst_ctrl_auto_blk_key_output.155223001 Mar 21 01:45:12 PM PDT 24 Mar 21 01:45:23 PM PDT 24 3638667949 ps
T5 /workspace/coverage/default/2.sysrst_ctrl_auto_blk_key_output.475723480 Mar 21 01:43:23 PM PDT 24 Mar 21 01:43:24 PM PDT 24 3517967198 ps
T6 /workspace/coverage/default/30.sysrst_ctrl_stress_all.3241888542 Mar 21 01:45:54 PM PDT 24 Mar 21 01:46:12 PM PDT 24 14512402192 ps
T20 /workspace/coverage/default/30.sysrst_ctrl_in_out_inverted.4131625504 Mar 21 01:45:52 PM PDT 24 Mar 21 01:45:57 PM PDT 24 2460667240 ps
T21 /workspace/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.844620889 Mar 21 01:46:04 PM PDT 24 Mar 21 01:46:59 PM PDT 24 23331775804 ps
T22 /workspace/coverage/default/41.sysrst_ctrl_alert_test.4161744630 Mar 21 01:46:43 PM PDT 24 Mar 21 01:46:45 PM PDT 24 2036730255 ps
T23 /workspace/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.2532357288 Mar 21 01:45:46 PM PDT 24 Mar 21 01:45:55 PM PDT 24 2676601325 ps
T1 /workspace/coverage/default/42.sysrst_ctrl_combo_detect.3702483693 Mar 21 01:46:54 PM PDT 24 Mar 21 01:52:03 PM PDT 24 123918517809 ps
T14 /workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.3277532562 Mar 21 01:46:43 PM PDT 24 Mar 21 01:48:32 PM PDT 24 40122805912 ps
T2 /workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.197762338 Mar 21 01:47:28 PM PDT 24 Mar 21 01:49:15 PM PDT 24 151837755283 ps
T15 /workspace/coverage/default/18.sysrst_ctrl_auto_blk_key_output.2830782985 Mar 21 01:45:08 PM PDT 24 Mar 21 01:45:18 PM PDT 24 3148077460 ps
T3 /workspace/coverage/default/12.sysrst_ctrl_edge_detect.208147672 Mar 21 01:44:33 PM PDT 24 Mar 21 01:44:40 PM PDT 24 5538300012 ps
T7 /workspace/coverage/default/22.sysrst_ctrl_edge_detect.678680678 Mar 21 01:45:19 PM PDT 24 Mar 21 01:45:27 PM PDT 24 3120778526 ps
T16 /workspace/coverage/default/9.sysrst_ctrl_pin_access_test.3896095401 Mar 21 01:44:08 PM PDT 24 Mar 21 01:44:12 PM PDT 24 2176236019 ps
T17 /workspace/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.968743306 Mar 21 01:45:43 PM PDT 24 Mar 21 01:45:52 PM PDT 24 3059147197 ps
T18 /workspace/coverage/default/28.sysrst_ctrl_pin_access_test.954374587 Mar 21 01:45:43 PM PDT 24 Mar 21 01:45:49 PM PDT 24 2079561202 ps
T19 /workspace/coverage/default/4.sysrst_ctrl_pin_override_test.3950880438 Mar 21 01:43:43 PM PDT 24 Mar 21 01:43:51 PM PDT 24 2513480722 ps
T40 /workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.153627388 Mar 21 01:43:55 PM PDT 24 Mar 21 01:44:04 PM PDT 24 3894453157 ps
T8 /workspace/coverage/default/14.sysrst_ctrl_combo_detect.2922753258 Mar 21 01:44:39 PM PDT 24 Mar 21 01:49:24 PM PDT 24 107590031190 ps
T48 /workspace/coverage/default/43.sysrst_ctrl_smoke.1973209507 Mar 21 01:46:56 PM PDT 24 Mar 21 01:46:59 PM PDT 24 2115063246 ps
T33 /workspace/coverage/default/10.sysrst_ctrl_ultra_low_pwr.381133123 Mar 21 01:44:26 PM PDT 24 Mar 21 01:44:29 PM PDT 24 4880774194 ps
T52 /workspace/coverage/default/5.sysrst_ctrl_pin_access_test.811818036 Mar 21 01:43:47 PM PDT 24 Mar 21 01:43:50 PM PDT 24 2285742860 ps
T9 /workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.1440406281 Mar 21 01:47:24 PM PDT 24 Mar 21 01:47:47 PM PDT 24 32868324215 ps
T41 /workspace/coverage/default/33.sysrst_ctrl_auto_blk_key_output.2260651457 Mar 21 01:46:02 PM PDT 24 Mar 21 01:46:11 PM PDT 24 3158552641 ps
T10 /workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.3541330273 Mar 21 01:44:18 PM PDT 24 Mar 21 01:45:21 PM PDT 24 22929028759 ps
T29 /workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.468044118 Mar 21 01:47:15 PM PDT 24 Mar 21 01:47:19 PM PDT 24 2462502197 ps
T53 /workspace/coverage/default/39.sysrst_ctrl_smoke.486182212 Mar 21 01:46:27 PM PDT 24 Mar 21 01:46:29 PM PDT 24 2140204164 ps
T11 /workspace/coverage/default/44.sysrst_ctrl_combo_detect.1841338432 Mar 21 01:46:55 PM PDT 24 Mar 21 01:47:16 PM PDT 24 32359742740 ps
T12 /workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.1189620700 Mar 21 01:43:57 PM PDT 24 Mar 21 01:43:59 PM PDT 24 4717925824 ps
T30 /workspace/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.2528245680 Mar 21 01:45:19 PM PDT 24 Mar 21 01:45:22 PM PDT 24 2635347816 ps
T13 /workspace/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.356220879 Mar 21 01:44:41 PM PDT 24 Mar 21 01:45:33 PM PDT 24 81624226495 ps
T59 /workspace/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.2630485687 Mar 21 01:44:31 PM PDT 24 Mar 21 01:44:34 PM PDT 24 2622785778 ps
T74 /workspace/coverage/default/43.sysrst_ctrl_alert_test.1593215136 Mar 21 01:46:57 PM PDT 24 Mar 21 01:46:59 PM PDT 24 2039964304 ps
T34 /workspace/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.4081419910 Mar 21 01:44:18 PM PDT 24 Mar 21 01:46:23 PM PDT 24 181416126283 ps
T60 /workspace/coverage/default/35.sysrst_ctrl_pin_override_test.1366178060 Mar 21 01:46:16 PM PDT 24 Mar 21 01:46:20 PM PDT 24 2514067350 ps
T54 /workspace/coverage/default/17.sysrst_ctrl_in_out_inverted.1989925803 Mar 21 01:45:03 PM PDT 24 Mar 21 01:45:10 PM PDT 24 2446134957 ps
T27 /workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.939758031 Mar 21 01:46:56 PM PDT 24 Mar 21 01:46:59 PM PDT 24 7486696436 ps
T42 /workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.1701813794 Mar 21 01:47:23 PM PDT 24 Mar 21 01:48:49 PM PDT 24 124263344164 ps
T132 /workspace/coverage/default/26.sysrst_ctrl_pin_access_test.2568491833 Mar 21 01:45:40 PM PDT 24 Mar 21 01:45:43 PM PDT 24 2073183184 ps
T55 /workspace/coverage/default/32.sysrst_ctrl_in_out_inverted.266367604 Mar 21 01:46:04 PM PDT 24 Mar 21 01:46:06 PM PDT 24 2466650712 ps
T36 /workspace/coverage/default/49.sysrst_ctrl_edge_detect.3394333331 Mar 21 01:47:13 PM PDT 24 Mar 21 01:47:25 PM PDT 24 4281720351 ps
T133 /workspace/coverage/default/37.sysrst_ctrl_pin_access_test.18770896 Mar 21 01:46:29 PM PDT 24 Mar 21 01:46:32 PM PDT 24 2080570638 ps
T43 /workspace/coverage/default/1.sysrst_ctrl_auto_blk_key_output.1686318984 Mar 21 01:43:22 PM PDT 24 Mar 21 01:43:31 PM PDT 24 2994817452 ps
T61 /workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.912567620 Mar 21 01:43:56 PM PDT 24 Mar 21 01:44:01 PM PDT 24 2619021006 ps
T62 /workspace/coverage/default/24.sysrst_ctrl_stress_all.443823869 Mar 21 01:45:30 PM PDT 24 Mar 21 01:45:34 PM PDT 24 9738023506 ps
T134 /workspace/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.1988726866 Mar 21 01:44:43 PM PDT 24 Mar 21 01:44:52 PM PDT 24 3149523694 ps
T63 /workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.1724814894 Mar 21 01:46:42 PM PDT 24 Mar 21 01:46:49 PM PDT 24 2610359169 ps
T44 /workspace/coverage/default/12.sysrst_ctrl_combo_detect.744913743 Mar 21 01:44:29 PM PDT 24 Mar 21 01:47:51 PM PDT 24 153394705771 ps
T181 /workspace/coverage/default/46.sysrst_ctrl_pin_access_test.2852589123 Mar 21 01:47:14 PM PDT 24 Mar 21 01:47:16 PM PDT 24 2159997155 ps
T82 /workspace/coverage/default/31.sysrst_ctrl_combo_detect.2475113364 Mar 21 01:46:09 PM PDT 24 Mar 21 01:47:26 PM PDT 24 56791276823 ps
T64 /workspace/coverage/default/35.sysrst_ctrl_stress_all.1464570766 Mar 21 01:46:40 PM PDT 24 Mar 21 01:47:19 PM PDT 24 14579478354 ps
T68 /workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.1395196111 Mar 21 01:47:22 PM PDT 24 Mar 21 01:48:52 PM PDT 24 67927640839 ps
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T65 /workspace/coverage/default/39.sysrst_ctrl_stress_all.151938212 Mar 21 01:46:27 PM PDT 24 Mar 21 01:46:57 PM PDT 24 10623076355 ps
T45 /workspace/coverage/default/23.sysrst_ctrl_auto_blk_key_output.4198042265 Mar 21 01:45:21 PM PDT 24 Mar 21 01:45:32 PM PDT 24 3822116485 ps
T121 /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.1266375708 Mar 21 01:43:10 PM PDT 24 Mar 21 01:43:16 PM PDT 24 2164443062 ps
T49 /workspace/coverage/default/28.sysrst_ctrl_ultra_low_pwr.1781444605 Mar 21 01:45:44 PM PDT 24 Mar 21 01:45:46 PM PDT 24 3738212685 ps
T69 /workspace/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.1324492802 Mar 21 01:44:20 PM PDT 24 Mar 21 01:46:01 PM PDT 24 147834099241 ps
T37 /workspace/coverage/default/45.sysrst_ctrl_stress_all.2328017807 Mar 21 01:46:53 PM PDT 24 Mar 21 01:47:05 PM PDT 24 14191985489 ps
T122 /workspace/coverage/default/39.sysrst_ctrl_pin_access_test.3354815349 Mar 21 01:46:28 PM PDT 24 Mar 21 01:46:31 PM PDT 24 2027635800 ps
T39 /workspace/coverage/default/7.sysrst_ctrl_stress_all.836871865 Mar 21 01:44:08 PM PDT 24 Mar 21 02:11:37 PM PDT 24 631022496360 ps
T123 /workspace/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.168829232 Mar 21 01:44:57 PM PDT 24 Mar 21 02:43:42 PM PDT 24 1722073611321 ps
T127 /workspace/coverage/default/3.sysrst_ctrl_pin_override_test.4047929098 Mar 21 01:43:34 PM PDT 24 Mar 21 01:43:38 PM PDT 24 2513690962 ps
T50 /workspace/coverage/default/1.sysrst_ctrl_ultra_low_pwr.3946795394 Mar 21 01:43:20 PM PDT 24 Mar 21 01:43:27 PM PDT 24 3682715970 ps
T128 /workspace/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.166795148 Mar 21 01:45:10 PM PDT 24 Mar 21 01:45:13 PM PDT 24 3076119729 ps
T51 /workspace/coverage/default/22.sysrst_ctrl_ultra_low_pwr.3051956268 Mar 21 01:45:20 PM PDT 24 Mar 21 01:45:21 PM PDT 24 6595538173 ps
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T70 /workspace/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.1602377742 Mar 21 01:44:34 PM PDT 24 Mar 21 01:44:59 PM PDT 24 34972813012 ps
T46 /workspace/coverage/default/27.sysrst_ctrl_auto_blk_key_output.2868761954 Mar 21 01:45:43 PM PDT 24 Mar 21 01:45:44 PM PDT 24 3617575202 ps
T56 /workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.2743871383 Mar 21 01:46:41 PM PDT 24 Mar 21 01:47:02 PM PDT 24 34379220300 ps
T57 /workspace/coverage/default/4.sysrst_ctrl_in_out_inverted.1027089070 Mar 21 01:43:46 PM PDT 24 Mar 21 01:43:48 PM PDT 24 2550047741 ps
T47 /workspace/coverage/default/35.sysrst_ctrl_auto_blk_key_output.3770525688 Mar 21 01:46:17 PM PDT 24 Mar 21 01:46:21 PM PDT 24 3355543685 ps
T223 /workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.3873224732 Mar 21 01:43:57 PM PDT 24 Mar 21 01:43:58 PM PDT 24 2681628369 ps
T224 /workspace/coverage/default/3.sysrst_ctrl_sec_cm.2067921770 Mar 21 01:43:44 PM PDT 24 Mar 21 01:43:55 PM PDT 24 22097763813 ps
T215 /workspace/coverage/default/3.sysrst_ctrl_combo_detect.302026632 Mar 21 01:43:35 PM PDT 24 Mar 21 01:44:34 PM PDT 24 21090289698 ps
T83 /workspace/coverage/default/29.sysrst_ctrl_auto_blk_key_output.790186257 Mar 21 01:45:53 PM PDT 24 Mar 21 01:56:35 PM PDT 24 242509256032 ps
T38 /workspace/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.1310127652 Mar 21 01:44:31 PM PDT 24 Mar 21 01:45:53 PM PDT 24 140132237382 ps
T184 /workspace/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.2251134977 Mar 21 01:46:05 PM PDT 24 Mar 21 01:46:08 PM PDT 24 2633827802 ps
T58 /workspace/coverage/default/24.sysrst_ctrl_in_out_inverted.3240088326 Mar 21 01:45:36 PM PDT 24 Mar 21 01:45:44 PM PDT 24 2456957322 ps
T185 /workspace/coverage/default/17.sysrst_ctrl_alert_test.2805412120 Mar 21 01:45:09 PM PDT 24 Mar 21 01:45:12 PM PDT 24 2031809578 ps
T186 /workspace/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.1741580268 Mar 21 01:45:21 PM PDT 24 Mar 21 01:45:24 PM PDT 24 2964120844 ps
T187 /workspace/coverage/default/7.sysrst_ctrl_smoke.1095622430 Mar 21 01:43:57 PM PDT 24 Mar 21 01:44:02 PM PDT 24 2111567711 ps
T188 /workspace/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.1794527104 Mar 21 01:46:31 PM PDT 24 Mar 21 01:46:33 PM PDT 24 2639500283 ps
T189 /workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.2348644544 Mar 21 01:44:08 PM PDT 24 Mar 21 01:44:10 PM PDT 24 2650250967 ps
T190 /workspace/coverage/default/36.sysrst_ctrl_alert_test.2694732130 Mar 21 01:46:17 PM PDT 24 Mar 21 01:46:19 PM PDT 24 2033406778 ps
T191 /workspace/coverage/default/25.sysrst_ctrl_in_out_inverted.2249560820 Mar 21 01:45:33 PM PDT 24 Mar 21 01:45:37 PM PDT 24 2459325958 ps
T359 /workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.2296280377 Mar 21 01:47:11 PM PDT 24 Mar 21 01:48:03 PM PDT 24 261175758492 ps
T360 /workspace/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.3605639553 Mar 21 01:44:18 PM PDT 24 Mar 21 01:44:28 PM PDT 24 3395273017 ps
T361 /workspace/coverage/default/47.sysrst_ctrl_stress_all.704713984 Mar 21 01:47:11 PM PDT 24 Mar 21 01:47:16 PM PDT 24 6576360888 ps
T250 /workspace/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.2040218813 Mar 21 01:45:18 PM PDT 24 Mar 21 01:46:02 PM PDT 24 15618416149 ps
T84 /workspace/coverage/default/39.sysrst_ctrl_combo_detect.1517303544 Mar 21 01:46:31 PM PDT 24 Mar 21 01:47:41 PM PDT 24 107302516785 ps
T102 /workspace/coverage/default/0.sysrst_ctrl_pin_override_test.1442054213 Mar 21 01:43:10 PM PDT 24 Mar 21 01:43:18 PM PDT 24 2511068559 ps
T66 /workspace/coverage/default/44.sysrst_ctrl_edge_detect.784107779 Mar 21 01:46:55 PM PDT 24 Mar 21 01:46:58 PM PDT 24 4154334659 ps
T103 /workspace/coverage/default/5.sysrst_ctrl_smoke.755200024 Mar 21 01:43:44 PM PDT 24 Mar 21 01:43:50 PM PDT 24 2115763861 ps
T104 /workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.4176061032 Mar 21 01:44:09 PM PDT 24 Mar 21 01:44:11 PM PDT 24 2911215095 ps
T105 /workspace/coverage/default/33.sysrst_ctrl_pin_override_test.3236806556 Mar 21 01:46:04 PM PDT 24 Mar 21 01:46:06 PM PDT 24 2526170888 ps
T106 /workspace/coverage/default/30.sysrst_ctrl_smoke.95927687 Mar 21 01:45:52 PM PDT 24 Mar 21 01:45:59 PM PDT 24 2110060623 ps
T67 /workspace/coverage/default/3.sysrst_ctrl_stress_all.2730356390 Mar 21 01:43:42 PM PDT 24 Mar 21 01:49:41 PM PDT 24 801856544607 ps
T107 /workspace/coverage/default/13.sysrst_ctrl_auto_blk_key_output.3503225925 Mar 21 01:44:29 PM PDT 24 Mar 21 01:44:32 PM PDT 24 3624088161 ps
T108 /workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.3615279642 Mar 21 01:46:54 PM PDT 24 Mar 21 01:46:58 PM PDT 24 2620593766 ps
T35 /workspace/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.4091759126 Mar 21 01:45:44 PM PDT 24 Mar 21 01:46:28 PM PDT 24 33689333141 ps
T109 /workspace/coverage/default/34.sysrst_ctrl_edge_detect.384117015 Mar 21 01:46:16 PM PDT 24 Mar 21 01:46:25 PM PDT 24 2805172479 ps
T110 /workspace/coverage/default/0.sysrst_ctrl_auto_blk_key_output.3048525446 Mar 21 01:43:11 PM PDT 24 Mar 21 01:43:21 PM PDT 24 3441374460 ps
T85 /workspace/coverage/default/49.sysrst_ctrl_combo_detect.3851829869 Mar 21 01:47:12 PM PDT 24 Mar 21 01:49:22 PM PDT 24 101420786678 ps
T111 /workspace/coverage/default/34.sysrst_ctrl_ultra_low_pwr.1723656155 Mar 21 01:46:17 PM PDT 24 Mar 21 01:46:19 PM PDT 24 2895414707 ps
T112 /workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.3755495208 Mar 21 01:43:56 PM PDT 24 Mar 21 01:44:00 PM PDT 24 4857503474 ps
T113 /workspace/coverage/default/27.sysrst_ctrl_pin_access_test.3882752510 Mar 21 01:45:46 PM PDT 24 Mar 21 01:45:49 PM PDT 24 2145422792 ps
T114 /workspace/coverage/default/23.sysrst_ctrl_smoke.1302906804 Mar 21 01:45:21 PM PDT 24 Mar 21 01:45:24 PM PDT 24 2139749959 ps
T115 /workspace/coverage/default/38.sysrst_ctrl_combo_detect.572735095 Mar 21 01:46:32 PM PDT 24 Mar 21 01:47:29 PM PDT 24 87467113433 ps
T116 /workspace/coverage/default/14.sysrst_ctrl_auto_blk_key_output.3282832829 Mar 21 01:44:41 PM PDT 24 Mar 21 01:44:47 PM PDT 24 3841605841 ps
T362 /workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.2979304627 Mar 21 01:46:43 PM PDT 24 Mar 21 01:46:51 PM PDT 24 2462627544 ps
T363 /workspace/coverage/default/42.sysrst_ctrl_alert_test.3373103035 Mar 21 01:46:53 PM PDT 24 Mar 21 01:46:59 PM PDT 24 2013594944 ps
T364 /workspace/coverage/default/26.sysrst_ctrl_smoke.393864898 Mar 21 01:45:33 PM PDT 24 Mar 21 01:45:39 PM PDT 24 2111857534 ps
T356 /workspace/coverage/default/48.sysrst_ctrl_pin_override_test.2103662605 Mar 21 01:47:12 PM PDT 24 Mar 21 01:47:16 PM PDT 24 2518402493 ps
T208 /workspace/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.854022616 Mar 21 01:44:56 PM PDT 24 Mar 21 01:49:01 PM PDT 24 88319918246 ps
T365 /workspace/coverage/default/11.sysrst_ctrl_ultra_low_pwr.3567406264 Mar 21 01:44:20 PM PDT 24 Mar 21 01:44:25 PM PDT 24 3739073748 ps
T257 /workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.2508296671 Mar 21 01:46:40 PM PDT 24 Mar 21 01:46:42 PM PDT 24 2487973038 ps
T366 /workspace/coverage/default/44.sysrst_ctrl_pin_access_test.3590414060 Mar 21 01:46:52 PM PDT 24 Mar 21 01:46:55 PM PDT 24 2175734784 ps
T136 /workspace/coverage/default/0.sysrst_ctrl_stress_all.1220594569 Mar 21 01:43:13 PM PDT 24 Mar 21 01:43:58 PM PDT 24 17508285489 ps
T367 /workspace/coverage/default/12.sysrst_ctrl_pin_access_test.516526992 Mar 21 01:44:30 PM PDT 24 Mar 21 01:44:32 PM PDT 24 2050585914 ps
T137 /workspace/coverage/default/32.sysrst_ctrl_edge_detect.3768295222 Mar 21 01:46:03 PM PDT 24 Mar 21 01:46:07 PM PDT 24 3780825874 ps
T211 /workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.2029208602 Mar 21 01:47:27 PM PDT 24 Mar 21 01:48:35 PM PDT 24 95278728590 ps
T368 /workspace/coverage/default/3.sysrst_ctrl_in_out_inverted.3040751360 Mar 21 01:43:33 PM PDT 24 Mar 21 01:43:36 PM PDT 24 2477489522 ps
T355 /workspace/coverage/default/38.sysrst_ctrl_pin_override_test.3137402096 Mar 21 01:46:31 PM PDT 24 Mar 21 01:46:38 PM PDT 24 2513638484 ps
T138 /workspace/coverage/default/48.sysrst_ctrl_stress_all.3266870044 Mar 21 01:47:12 PM PDT 24 Mar 21 01:47:19 PM PDT 24 12319241852 ps
T369 /workspace/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.956529117 Mar 21 01:45:53 PM PDT 24 Mar 21 01:45:58 PM PDT 24 3548108970 ps
T370 /workspace/coverage/default/45.sysrst_ctrl_pin_access_test.568020043 Mar 21 01:46:53 PM PDT 24 Mar 21 01:46:55 PM PDT 24 2094125420 ps
T177 /workspace/coverage/default/18.sysrst_ctrl_edge_detect.185029631 Mar 21 01:45:09 PM PDT 24 Mar 21 01:45:12 PM PDT 24 2645449566 ps
T212 /workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.3517607118 Mar 21 01:47:25 PM PDT 24 Mar 21 01:49:41 PM PDT 24 111726007752 ps
T161 /workspace/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.646104684 Mar 21 01:45:20 PM PDT 24 Mar 21 01:45:54 PM PDT 24 47486694392 ps
T251 /workspace/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.3653423131 Mar 21 01:44:29 PM PDT 24 Mar 21 01:45:12 PM PDT 24 15514292339 ps
T264 /workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.1697174354 Mar 21 01:46:43 PM PDT 24 Mar 21 01:46:45 PM PDT 24 2716871277 ps
T265 /workspace/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.3351409332 Mar 21 01:46:10 PM PDT 24 Mar 21 01:46:21 PM PDT 24 4332450528 ps
T266 /workspace/coverage/default/30.sysrst_ctrl_auto_blk_key_output.2507374336 Mar 21 01:45:53 PM PDT 24 Mar 21 01:46:03 PM PDT 24 3393530176 ps
T259 /workspace/coverage/default/42.sysrst_ctrl_pin_override_test.2393969044 Mar 21 01:46:43 PM PDT 24 Mar 21 01:46:50 PM PDT 24 2510629979 ps
T267 /workspace/coverage/default/18.sysrst_ctrl_smoke.4214646530 Mar 21 01:45:10 PM PDT 24 Mar 21 01:45:12 PM PDT 24 2180696890 ps
T71 /workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.191480502 Mar 21 01:47:11 PM PDT 24 Mar 21 01:47:12 PM PDT 24 12668612319 ps
T252 /workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.869389570 Mar 21 01:47:25 PM PDT 24 Mar 21 01:48:43 PM PDT 24 31613481396 ps
T268 /workspace/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.1772382488 Mar 21 01:44:58 PM PDT 24 Mar 21 01:45:05 PM PDT 24 2609668859 ps
T227 /workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.805272074 Mar 21 01:46:56 PM PDT 24 Mar 21 01:47:36 PM PDT 24 30163731824 ps
T144 /workspace/coverage/default/0.sysrst_ctrl_edge_detect.100052619 Mar 21 01:43:13 PM PDT 24 Mar 21 01:43:17 PM PDT 24 2550811076 ps
T371 /workspace/coverage/default/19.sysrst_ctrl_pin_access_test.3818525251 Mar 21 01:45:09 PM PDT 24 Mar 21 01:45:13 PM PDT 24 2034762467 ps
T226 /workspace/coverage/default/8.sysrst_ctrl_combo_detect.3028740260 Mar 21 01:44:10 PM PDT 24 Mar 21 01:45:01 PM PDT 24 112346772748 ps
T72 /workspace/coverage/default/27.sysrst_ctrl_ultra_low_pwr.1338637215 Mar 21 01:45:45 PM PDT 24 Mar 21 01:45:56 PM PDT 24 10273478184 ps
T213 /workspace/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.2371827125 Mar 21 01:46:42 PM PDT 24 Mar 21 01:51:35 PM PDT 24 104982540160 ps
T372 /workspace/coverage/default/27.sysrst_ctrl_alert_test.3935426199 Mar 21 01:45:43 PM PDT 24 Mar 21 01:45:46 PM PDT 24 2022400142 ps
T139 /workspace/coverage/default/19.sysrst_ctrl_edge_detect.2984892353 Mar 21 01:45:10 PM PDT 24 Mar 21 01:45:20 PM PDT 24 3100789635 ps
T373 /workspace/coverage/default/43.sysrst_ctrl_pin_access_test.1202948903 Mar 21 01:46:53 PM PDT 24 Mar 21 01:47:00 PM PDT 24 2195180207 ps
T214 /workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.3904441906 Mar 21 01:47:27 PM PDT 24 Mar 21 01:47:56 PM PDT 24 42572466186 ps
T357 /workspace/coverage/default/44.sysrst_ctrl_pin_override_test.1526032543 Mar 21 01:46:54 PM PDT 24 Mar 21 01:46:57 PM PDT 24 2524122299 ps
T374 /workspace/coverage/default/29.sysrst_ctrl_smoke.238939455 Mar 21 01:45:54 PM PDT 24 Mar 21 01:46:00 PM PDT 24 2109564615 ps
T375 /workspace/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.3501308923 Mar 21 01:46:18 PM PDT 24 Mar 21 01:46:22 PM PDT 24 2622559899 ps
T376 /workspace/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.2211645301 Mar 21 01:46:18 PM PDT 24 Mar 21 01:46:20 PM PDT 24 2625000783 ps
T377 /workspace/coverage/default/2.sysrst_ctrl_smoke.4090123627 Mar 21 01:43:21 PM PDT 24 Mar 21 01:43:24 PM PDT 24 2118905045 ps
T358 /workspace/coverage/default/16.sysrst_ctrl_pin_override_test.2779772315 Mar 21 01:45:02 PM PDT 24 Mar 21 01:45:09 PM PDT 24 2507378704 ps
T293 /workspace/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.4027978790 Mar 21 01:45:41 PM PDT 24 Mar 21 01:46:45 PM PDT 24 44771952829 ps
T378 /workspace/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.2218948116 Mar 21 01:46:03 PM PDT 24 Mar 21 01:46:06 PM PDT 24 4242653461 ps
T379 /workspace/coverage/default/48.sysrst_ctrl_alert_test.964842385 Mar 21 01:47:09 PM PDT 24 Mar 21 01:47:15 PM PDT 24 2012962477 ps
T348 /workspace/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.3555326399 Mar 21 01:43:44 PM PDT 24 Mar 21 01:49:38 PM PDT 24 784402638352 ps
T258 /workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.3361886416 Mar 21 01:47:11 PM PDT 24 Mar 21 01:47:18 PM PDT 24 2457084645 ps
T380 /workspace/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.3849452387 Mar 21 01:45:10 PM PDT 24 Mar 21 01:45:17 PM PDT 24 2542622306 ps
T77 /workspace/coverage/default/36.sysrst_ctrl_stress_all.1572144942 Mar 21 01:46:19 PM PDT 24 Mar 21 01:48:32 PM PDT 24 1523369323616 ps
T73 /workspace/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.687537606 Mar 21 01:45:02 PM PDT 24 Mar 21 01:47:51 PM PDT 24 458989781649 ps
T80 /workspace/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.711301770 Mar 21 01:43:44 PM PDT 24 Mar 21 01:45:25 PM PDT 24 1163286418551 ps
T145 /workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.13841362 Mar 21 01:46:54 PM PDT 24 Mar 21 01:46:57 PM PDT 24 2794266380 ps
T146 /workspace/coverage/default/1.sysrst_ctrl_pin_override_test.1330897835 Mar 21 01:43:20 PM PDT 24 Mar 21 01:43:27 PM PDT 24 2513301045 ps
T147 /workspace/coverage/default/30.sysrst_ctrl_combo_detect.734672656 Mar 21 01:45:50 PM PDT 24 Mar 21 01:51:23 PM PDT 24 132981613908 ps
T148 /workspace/coverage/default/24.sysrst_ctrl_pin_override_test.3196786593 Mar 21 01:45:32 PM PDT 24 Mar 21 01:45:39 PM PDT 24 2515137716 ps
T149 /workspace/coverage/default/0.sysrst_ctrl_sec_cm.4105753187 Mar 21 01:43:13 PM PDT 24 Mar 21 01:44:11 PM PDT 24 22011421615 ps
T150 /workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.3951943228 Mar 21 01:47:25 PM PDT 24 Mar 21 01:48:36 PM PDT 24 112854505000 ps
T151 /workspace/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.1922430320 Mar 21 01:45:33 PM PDT 24 Mar 21 01:45:40 PM PDT 24 2611208352 ps
T291 /workspace/coverage/default/18.sysrst_ctrl_combo_detect.1353243514 Mar 21 01:45:09 PM PDT 24 Mar 21 01:45:37 PM PDT 24 20710945838 ps
T86 /workspace/coverage/default/41.sysrst_ctrl_combo_detect.788480120 Mar 21 01:46:39 PM PDT 24 Mar 21 01:47:40 PM PDT 24 50538222884 ps
T381 /workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.3480137273 Mar 21 01:46:56 PM PDT 24 Mar 21 01:47:04 PM PDT 24 2800818418 ps
T87 /workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.2660284580 Mar 21 01:47:24 PM PDT 24 Mar 21 01:47:41 PM PDT 24 25612546316 ps
T312 /workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.1654148302 Mar 21 01:47:24 PM PDT 24 Mar 21 01:48:11 PM PDT 24 84855388106 ps
T117 /workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.2748507581 Mar 21 01:44:09 PM PDT 24 Mar 21 01:44:12 PM PDT 24 4500148837 ps
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T423 /workspace/coverage/default/31.sysrst_ctrl_auto_blk_key_output.1983661111 Mar 21 01:46:05 PM PDT 24 Mar 21 01:46:15 PM PDT 24 3611460879 ps
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