Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.90	93.90	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	93.90	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.90	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	5	57	91.94

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	5	26	83.87	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2111

1

T1

4

T6

7

T28

10

auto[1]

583

1

T1

2

T3

13

T6

1

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2065

1

T1

4

T3

7

T28

12

auto[1]

629

1

T1

2

T3

6

T6

8

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2082

1

T1

1

T3

8

T6

6

auto[1]

612

1

T1

5

T3

5

T6

2

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2089

1

T1

1

T3

2

T6

7

auto[1]

605

1

T1

5

T3

11

T6

1

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2439

1

T1

6

T3

13

T6

8

auto[1]

255

1

T10

4

T12

32

T32

3

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2492

1

T1

6

T3

13

T6

8

auto[1]

202

1

T28

4

T12

4

T78

3

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2428

1

T1

6

T3

13

T6

8

auto[1]

266

1

T12

4

T32

10

T77

4

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2480

1

T1

6

T3

13

T6

8

auto[1]

214

1

T28

4

T12

10

T33

1

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2469

1

T1

6

T3

13

T6

8

auto[1]

225

1

T28

10

T10

4

T12

6

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2002

1

T1

1

T3

11

T28

16

auto[1]

692

1

T1

5

T3

2

T6

8

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	5	26	83.87	5
Automatically Generated Cross Bins	31	5	26	83.87	5
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	839	1			T1	6		T3	13		T6	8
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	114	1			T12	32		T32	3		T77	9
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	43	1			T28	2		T77	1		T85	1
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	16	1			T10	4		T357	8		T358	4
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	86	1			T33	1		T32	7		T73	6
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	1	1			T73	1		-	-		-	-
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	46	1			T28	2		T12	6		T342	4
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	91	1			T32	10		T125	3		T229	6
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	53	1			T238	2		T224	4		T359	12
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	20	1			T360	3		T361	1		T362	4
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	12	1			T342	1		T359	2		T363	2
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	9	1			T125	3		T364	6		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	4	1			T77	4		-	-		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	61	1			T28	2		T240	3		T365	5
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	9	1			T78	2		T366	1		T367	6
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	39	1			T28	2		T224	2		T368	5
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	8	1			T331	4		T363	4		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	18	1			T242	2		T238	4		T229	5
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	1	1			T369	1		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	3	1			T345	1		T362	2		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[1]	2	1			T347	2		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	19	1			T370	3		T357	2		T331	6
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	3	1			T371	3		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	5	1			T361	1		T349	4		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	12	1			T12	4		T229	3		T372	5
auto[1]	auto[1]	auto[1]	auto[0]	auto[1]	2	1			T373	2		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

126

1

T28

2

T77

1

T248

9

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

110

1

T12

4

T31

6

T77

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

88

1

T3

2

T240

3

T370

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

130

1

T115

9

T365

5

T333

10

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

34

1

T248

5

T88

4

T257

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

52

1

T32

5

T78

2

T238

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

22

1

T244

2

T330

4

T146

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

128

1

T28

2

T108

10

T90

10

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

27

1

T33

1

T374

2

T309

7

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

89

1

T12

16

T31

4

T32

7

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

32

1

T251

6

T333

3

T375

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

58

1

T115

4

T370

9

T376

5

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

30

1

T3

5

T28

2

T8

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

30

1

T1

4

T78

6

T333

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

6

1

T115

1

T146

1

T136

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

102

1

T73

6

T77

9

T242

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

26

1

T12

6

T44

1

T256

5

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

97

1

T6

5

T73

1

T166

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

34

1

T125

3

T233

4

T334

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

84

1

T12

16

T21

1

T32

5

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

30

1

T1

1

T3

6

T184

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

14

1

T90

3

T377

3

T378

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

9

1

T6

1

T253

3

T94

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

44

1

T10

4

T251

9

T198

8

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

16

1

T344

3

T122

1

T93

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

21

1

T6

2

T32

3

T141

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

22

1

T1

1

T90

2

T252

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

25

1

T28

2

T8

2

T31

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

13

1

T31

2

T115

1

T330

4

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

13

1

T243

1

T161

1

T253

4

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

4

1

T244

1

T152

1

T136

1

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded