Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1181

1

T13

13

T14

10

T16

11

auto[1]

1175

1

T13

7

T14

10

T16

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

560

1

T13

4

T14

5

T16

6

from_0to1

563

1

T13

4

T14

6

T16

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1170

1

T13

12

T14

10

T16

13

auto[1]

1186

1

T13

8

T14

10

T16

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1178

1

T13

11

T14

9

T16

10

auto[1]

1178

1

T13

9

T14

11

T16

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

76

1

T13

1

T16

1

T71

1

auto[0]

from_1to0

auto[0]

auto[1]

76

1

T16

1

T17

1

T71

1

auto[0]

from_1to0

auto[1]

auto[0]

52

1

T13

1

T391

1

T27

1

auto[0]

from_1to0

auto[1]

auto[1]

72

1

T13

1

T14

3

T17

1

auto[0]

from_0to1

auto[0]

auto[0]

69

1

T14

1

T71

1

T27

1

auto[0]

from_0to1

auto[0]

auto[1]

66

1

T13

1

T14

2

T17

2

auto[0]

from_0to1

auto[1]

auto[0]

65

1

T13

2

T14

1

T16

2

auto[0]

from_0to1

auto[1]

auto[1]

85

1

T16

1

T71

1

T391

1

auto[1]

from_1to0

auto[0]

auto[0]

68

1

T14

1

T16

1

T17

2

auto[1]

from_1to0

auto[0]

auto[1]

65

1

T13

1

T16

2

T21

2

auto[1]

from_1to0

auto[1]

auto[0]

71

1

T16

1

T391

2

T291

1

auto[1]

from_1to0

auto[1]

auto[1]

80

1

T14

1

T17

1

T71

1

auto[1]

from_0to1

auto[0]

auto[0]

76

1

T13

1

T16

1

T17

1

auto[1]

from_0to1

auto[0]

auto[1]

60

1

T14

1

T16

1

T21

1

auto[1]

from_0to1

auto[1]

auto[0]

71

1

T391

2

T27

3

T291

1

auto[1]

from_0to1

auto[1]

auto[1]

71

1

T14

1

T17

1

T71

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1139

1

T13

9

T14

9

T16

9

auto[1]

1217

1

T13

11

T14

11

T16

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

569

1

T13

6

T14

3

T16

4

from_0to1

570

1

T13

6

T14

3

T16

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1155

1

T13

8

T14

7

T16

10

auto[1]

1201

1

T13

12

T14

13

T16

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1195

1

T13

12

T14

11

T16

8

auto[1]

1161

1

T13

8

T14

9

T16

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

81

1

T13

1

T17

1

T71

1

auto[0]

from_1to0

auto[0]

auto[1]

53

1

T13

1

T71

1

T391

1

auto[0]

from_1to0

auto[1]

auto[0]

69

1

T13

2

T14

1

T21

1

auto[0]

from_1to0

auto[1]

auto[1]

72

1

T16

2

T17

1

T71

1

auto[0]

from_0to1

auto[0]

auto[0]

71

1

T16

1

T48

1

T392

1

auto[0]

from_0to1

auto[0]

auto[1]

59

1

T13

1

T17

1

T21

2

auto[0]

from_0to1

auto[1]

auto[0]

74

1

T13

1

T21

1

T71

1

auto[0]

from_0to1

auto[1]

auto[1]

77

1

T16

1

T17

3

T21

1

auto[1]

from_1to0

auto[0]

auto[0]

73

1

T13

1

T71

1

T201

2

auto[1]

from_1to0

auto[0]

auto[1]

81

1

T14

1

T17

1

T391

1

auto[1]

from_1to0

auto[1]

auto[0]

71

1

T14

1

T17

1

T27

1

auto[1]

from_1to0

auto[1]

auto[1]

69

1

T13

1

T16

2

T21

2

auto[1]

from_0to1

auto[0]

auto[0]

73

1

T13

1

T14

1

T16

1

auto[1]

from_0to1

auto[0]

auto[1]

65

1

T14

1

T16

1

T71

1

auto[1]

from_0to1

auto[1]

auto[0]

70

1

T13

2

T16

1

T71

1

auto[1]

from_0to1

auto[1]

auto[1]

81

1

T13

1

T14

1

T201

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1196

1

T13

12

T14

11

T16

9

auto[1]

1160

1

T13

8

T14

9

T16

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

560

1

T13

5

T14

5

T16

4

from_0to1

555

1

T13

5

T14

5

T16

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1199

1

T13

12

T14

8

T16

7

auto[1]

1157

1

T13

8

T14

12

T16

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1190

1

T13

8

T14

12

T16

10

auto[1]

1166

1

T13

12

T14

8

T16

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

79

1

T13

1

T14

1

T17

2

auto[0]

from_1to0

auto[0]

auto[1]

80

1

T13

1

T17

2

T21

1

auto[0]

from_1to0

auto[1]

auto[0]

69

1

T13

1

T17

1

T21

1

auto[0]

from_1to0

auto[1]

auto[1]

67

1

T13

1

T14

1

T391

1

auto[0]

from_0to1

auto[0]

auto[0]

69

1

T13

1

T201

1

T44

2

auto[0]

from_0to1

auto[0]

auto[1]

64

1

T13

2

T16

1

T71

1

auto[0]

from_0to1

auto[1]

auto[0]

76

1

T13

1

T14

2

T17

2

auto[0]

from_0to1

auto[1]

auto[1]

70

1

T14

1

T16

1

T17

1

auto[1]

from_1to0

auto[0]

auto[0]

69

1

T14

1

T71

1

T391

1

auto[1]

from_1to0

auto[0]

auto[1]

71

1

T13

1

T16

1

T71

1

auto[1]

from_1to0

auto[1]

auto[0]

58

1

T16

1

T21

1

T71

1

auto[1]

from_1to0

auto[1]

auto[1]

67

1

T14

2

T16

2

T27

1

auto[1]

from_0to1

auto[0]

auto[0]

67

1

T14

1

T17

1

T21

2

auto[1]

from_0to1

auto[0]

auto[1]

82

1

T14

1

T17

1

T21

1

auto[1]

from_0to1

auto[1]

auto[0]

60

1

T16

1

T391

1

T201

2

auto[1]

from_0to1

auto[1]

auto[1]

67

1

T13

1

T16

1

T21

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1161

1

T13

9

T14

7

T16

13

auto[1]

1195

1

T13

11

T14

13

T16

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

559

1

T13

3

T14

8

T16

3

from_0to1

564

1

T13

4

T14

8

T16

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1166

1

T13

11

T14

8

T16

11

auto[1]

1190

1

T13

9

T14

12

T16

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1177

1

T13

7

T14

11

T16

9

auto[1]

1179

1

T13

13

T14

9

T16

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

70

1

T13

1

T14

1

T16

1

auto[0]

from_1to0

auto[0]

auto[1]

60

1

T14

1

T17

2

T27

1

auto[0]

from_1to0

auto[1]

auto[0]

68

1

T14

1

T21

1

T201

1

auto[0]

from_1to0

auto[1]

auto[1]

72

1

T13

1

T71

1

T391

1

auto[0]

from_0to1

auto[0]

auto[0]

67

1

T13

1

T391

3

T44

1

auto[0]

from_0to1

auto[0]

auto[1]

72

1

T16

3

T71

1

T27

1

auto[0]

from_0to1

auto[1]

auto[0]

65

1

T13

1

T14

1

T17

1

auto[0]

from_0to1

auto[1]

auto[1]

71

1

T14

2

T16

1

T201

1

auto[1]

from_1to0

auto[0]

auto[0]

83

1

T16

1

T17

2

T21

1

auto[1]

from_1to0

auto[0]

auto[1]

68

1

T14

2

T16

1

T17

1

auto[1]

from_1to0

auto[1]

auto[0]

69

1

T14

2

T391

1

T201

1

auto[1]

from_1to0

auto[1]

auto[1]

69

1

T13

1

T14

1

T21

1

auto[1]

from_0to1

auto[0]

auto[0]

70

1

T14

2

T21

1

T391

1

auto[1]

from_0to1

auto[0]

auto[1]

68

1

T13

2

T14

1

T17

2

auto[1]

from_0to1

auto[1]

auto[0]

84

1

T14

2

T21

1

T391

2

auto[1]

from_0to1

auto[1]

auto[1]

67

1

T17

1

T21

1

T27

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1171

1

T13

8

T14

14

T16

6

auto[1]

1185

1

T13

12

T14

6

T16

14

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

571

1

T13

5

T14

4

T16

6

from_0to1

581

1

T13

5

T14

4

T16

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1161

1

T13

9

T14

9

T16

11

auto[1]

1195

1

T13

11

T14

11

T16

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1174

1

T13

9

T14

12

T16

12

auto[1]

1182

1

T13

11

T14

8

T16

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

60

1

T17

1

T21

1

T27

1

auto[0]

from_1to0

auto[0]

auto[1]

67

1

T13

1

T14

1

T48

2

auto[0]

from_1to0

auto[1]

auto[0]

74

1

T14

1

T16

2

T17

2

auto[0]

from_1to0

auto[1]

auto[1]

70

1

T13

1

T14

1

T17

2

auto[0]

from_0to1

auto[0]

auto[0]

68

1

T13

1

T17

1

T21

2

auto[0]

from_0to1

auto[0]

auto[1]

83

1

T16

1

T21

1

T71

1

auto[0]

from_0to1

auto[1]

auto[0]

78

1

T13

1

T14

1

T16

1

auto[0]

from_0to1

auto[1]

auto[1]

75

1

T14

1

T17

2

T71

1

auto[1]

from_1to0

auto[0]

auto[0]

70

1

T16

1

T71

1

T391

1

auto[1]

from_1to0

auto[0]

auto[1]

78

1

T13

1

T16

2

T71

1

auto[1]

from_1to0

auto[1]

auto[0]

75

1

T13

1

T14

1

T16

1

auto[1]

from_1to0

auto[1]

auto[1]

77

1

T13

1

T391

1

T27

1

auto[1]

from_0to1

auto[0]

auto[0]

67

1

T13

1

T14

1

T16

1

auto[1]

from_0to1

auto[0]

auto[1]

71

1

T13

1

T14

1

T27

1

auto[1]

from_0to1

auto[1]

auto[0]

59

1

T16

1

T71

2

T27

1

auto[1]

from_0to1

auto[1]

auto[1]

80

1

T13

1

T16

1

T291

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1166

1

T13

13

T14

10

T16

11

auto[1]

1190

1

T13

7

T14

10

T16

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

561

1

T13

4

T14

4

T16

5

from_0to1

566

1

T13

3

T14

5

T16

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1170

1

T13

9

T14

10

T16

7

auto[1]

1186

1

T13

11

T14

10

T16

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1186

1

T13

13

T14

12

T16

11

auto[1]

1170

1

T13

7

T14

8

T16

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

80

1

T13

1

T17

3

T391

2

auto[0]

from_1to0

auto[0]

auto[1]

75

1

T14

1

T16

1

T17

1

auto[0]

from_1to0

auto[1]

auto[0]

47

1

T13

1

T71

1

T291

1

auto[0]

from_1to0

auto[1]

auto[1]

75

1

T14

2

T16

2

T21

1

auto[0]

from_0to1

auto[0]

auto[0]

60

1

T13

1

T14

2

T21

1

auto[0]

from_0to1

auto[0]

auto[1]

68

1

T16

1

T17

1

T71

1

auto[0]

from_0to1

auto[1]

auto[0]

76

1

T16

2

T71

1

T391

1

auto[0]

from_0to1

auto[1]

auto[1]

71

1

T13

1

T17

1

T21

2

auto[1]

from_1to0

auto[0]

auto[0]

59

1

T17

1

T21

1

T27

1

auto[1]

from_1to0

auto[0]

auto[1]

74

1

T71

1

T391

1

T201

1

auto[1]

from_1to0

auto[1]

auto[0]

78

1

T13

2

T14

1

T16

1

auto[1]

from_1to0

auto[1]

auto[1]

73

1

T16

1

T71

2

T391

1

auto[1]

from_0to1

auto[0]

auto[0]

99

1

T14

3

T16

2

T21

1

auto[1]

from_0to1

auto[0]

auto[1]

60

1

T17

1

T21

2

T391

1

auto[1]

from_0to1

auto[1]

auto[0]

72

1

T13

1

T17

2

T71

1

auto[1]

from_0to1

auto[1]

auto[1]

60

1

T71

1

T48

1

T291

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1187

1

T13

11

T14

8

T16

7

auto[1]

1169

1

T13

9

T14

12

T16

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

568

1

T13

3

T14

5

T16

4

from_0to1

564

1

T13

4

T14

6

T16

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1193

1

T13

9

T14

7

T16

10

auto[1]

1163

1

T13

11

T14

13

T16

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1193

1

T13

13

T14

10

T16

9

auto[1]

1163

1

T13

7

T14

10

T16

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

72

1

T16

2

T17

1

T21

1

auto[0]

from_1to0

auto[0]

auto[1]

83

1

T14

2

T17

1

T21

1

auto[0]

from_1to0

auto[1]

auto[0]

65

1

T13

1

T14

1

T17

1

auto[0]

from_1to0

auto[1]

auto[1]

69

1

T13

1

T391

1

T48

1

auto[0]

from_0to1

auto[0]

auto[0]

76

1

T13

2

T17

2

T21

1

auto[0]

from_0to1

auto[0]

auto[1]

72

1

T14

1

T391

1

T44

2

auto[0]

from_0to1

auto[1]

auto[0]

57

1

T14

1

T17

1

T71

1

auto[0]

from_0to1

auto[1]

auto[1]

77

1

T14

1

T16

1

T21

1

auto[1]

from_1to0

auto[0]

auto[0]

70

1

T14

1

T16

1

T391

2

auto[1]

from_1to0

auto[0]

auto[1]

67

1

T13

1

T14

1

T71

1

auto[1]

from_1to0

auto[1]

auto[0]

79

1

T17

1

T21

1

T391

1

auto[1]

from_1to0

auto[1]

auto[1]

63

1

T16

1

T21

1

T27

1

auto[1]

from_0to1

auto[0]

auto[0]

84

1

T16

1

T71

1

T201

2

auto[1]

from_0to1

auto[0]

auto[1]

65

1

T16

1

T71

1

T391

1

auto[1]

from_0to1

auto[1]

auto[0]

72

1

T13

2

T14

1

T16

1

auto[1]

from_0to1

auto[1]

auto[1]

61

1

T14

2

T17

1

T21

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1172

1

T13

12

T14

14

T16

4

auto[1]

1184

1

T13

8

T14

6

T16

16

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

572

1

T13

6

T14

4

T16

5

from_0to1

575

1

T13

6

T14

4

T16

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1171

1

T13

14

T14

8

T16

8

auto[1]

1185

1

T13

6

T14

12

T16

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1191

1

T13

7

T14

14

T16

11

auto[1]

1165

1

T13

13

T14

6

T16

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

61

1

T201

1

T116

1

T295

1

auto[0]

from_1to0

auto[0]

auto[1]

71

1

T13

1

T14

1

T17

1

auto[0]

from_1to0

auto[1]

auto[0]

79

1

T13

1

T14

1

T17

2

auto[0]

from_1to0

auto[1]

auto[1]

71

1

T13

1

T14

1

T17

1

auto[0]

from_0to1

auto[0]

auto[0]

63

1

T13

2

T14

1

T16

1

auto[0]

from_0to1

auto[0]

auto[1]

65

1

T13

2

T14

1

T21

1

auto[0]

from_0to1

auto[1]

auto[0]

75

1

T21

1

T27

2

T48

1

auto[0]

from_0to1

auto[1]

auto[1]

75

1

T391

1

T27

1

T201

2

auto[1]

from_1to0

auto[0]

auto[0]

73

1

T13

1

T14

1

T21

2

auto[1]

from_1to0

auto[0]

auto[1]

81

1

T13

1

T16

2

T17

1

auto[1]

from_1to0

auto[1]

auto[0]

69

1

T13

1

T16

2

T21

2

auto[1]

from_1to0

auto[1]

auto[1]

67

1

T16

1

T71

1

T27

2

auto[1]

from_0to1

auto[0]

auto[0]

73

1

T16

1

T21

3

T71

1

auto[1]

from_0to1

auto[0]

auto[1]

79

1

T13

1

T21

1

T71

1

auto[1]

from_0to1

auto[1]

auto[0]

74

1

T14

2

T16

2

T17

2

auto[1]

from_0to1

auto[1]

auto[1]

71

1

T13

1

T16

1

T391

1