Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	153203	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

118863

1

T4

37

T5

1

T1

263

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	137069	1			T4	24		T5	2		T1	390
values[0x0]	66938	1			T4	36		T1	52		T2	38
values[0x1]	68059	1			T4	32		T5	1		T1	41

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	124529	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

147537

1

T4

43

T5

1

T1

304

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	819	1			T1	1		T13	4		T3	5
valid_sources[0x01]	1132	1			T13	1		T3	2		T15	1
valid_sources[0x02]	911	1			T3	2		T15	4		T16	1
valid_sources[0x03]	1151	1			T13	1		T3	3		T29	6
valid_sources[0x04]	1064	1			T2	1		T13	1		T3	1
valid_sources[0x05]	908	1			T3	5		T15	1		T6	5
valid_sources[0x06]	810	1			T2	1		T3	5		T15	2
valid_sources[0x07]	1522	1			T1	1		T2	1		T3	4
valid_sources[0x08]	912	1			T13	3		T3	1		T15	3
valid_sources[0x09]	1046	1			T1	2		T13	3		T3	6
valid_sources[0x0a]	2025	1			T1	20		T13	1		T3	1
valid_sources[0x0b]	885	1			T1	8		T2	2		T3	3
valid_sources[0x0c]	1037	1			T3	2		T6	1		T17	1
valid_sources[0x0d]	1305	1			T3	6		T6	5		T8	1
valid_sources[0x0e]	982	1			T3	5		T15	5		T6	1
valid_sources[0x0f]	2038	1			T1	12		T15	3		T6	1
valid_sources[0x10]	1273	1			T2	6		T13	2		T3	5
valid_sources[0x11]	884	1			T13	3		T3	10		T15	1
valid_sources[0x12]	1409	1			T2	1		T3	3		T15	7
valid_sources[0x13]	849	1			T3	3		T6	2		T28	1
valid_sources[0x14]	912	1			T3	2		T15	1		T16	1
valid_sources[0x15]	774	1			T1	2		T2	1		T13	1
valid_sources[0x16]	878	1			T1	23		T13	2		T3	2
valid_sources[0x17]	1050	1			T3	6		T15	1		T6	2
valid_sources[0x18]	940	1			T13	1		T3	6		T15	2
valid_sources[0x19]	868	1			T1	3		T3	4		T15	7
valid_sources[0x1a]	1955	1			T1	2		T2	1		T13	2
valid_sources[0x1b]	856	1			T2	8		T13	1		T3	3
valid_sources[0x1c]	1016	1			T1	5		T13	1		T3	3
valid_sources[0x1d]	963	1			T13	1		T3	4		T6	2
valid_sources[0x1e]	1065	1			T3	4		T15	4		T16	3
valid_sources[0x1f]	955	1			T3	2		T15	3		T6	3
valid_sources[0x20]	789	1			T3	5		T6	2		T28	28
valid_sources[0x21]	1148	1			T2	5		T13	1		T3	1
valid_sources[0x22]	969	1			T13	1		T3	3		T6	2
valid_sources[0x23]	1042	1			T13	4		T3	5		T6	3
valid_sources[0x24]	877	1			T13	1		T3	4		T15	2
valid_sources[0x25]	798	1			T1	6		T3	2		T8	3
valid_sources[0x26]	1203	1			T13	2		T3	2		T15	5
valid_sources[0x27]	1053	1			T1	1		T2	3		T3	7
valid_sources[0x28]	822	1			T1	10		T3	11		T8	2
valid_sources[0x29]	1167	1			T3	1		T6	1		T28	9
valid_sources[0x2a]	943	1			T3	4		T15	2		T6	1
valid_sources[0x2b]	894	1			T1	1		T3	4		T15	2
valid_sources[0x2c]	1038	1			T1	4		T3	2		T16	1
valid_sources[0x2d]	853	1			T1	15		T3	2		T15	1
valid_sources[0x2e]	823	1			T1	8		T13	1		T3	7
valid_sources[0x2f]	1697	1			T3	10		T15	4		T16	2
valid_sources[0x30]	2775	1			T1	9		T3	2		T15	4
valid_sources[0x31]	917	1			T3	6		T15	3		T16	1
valid_sources[0x32]	921	1			T6	5		T8	1		T188	5
valid_sources[0x33]	835	1			T13	2		T3	2		T6	2
valid_sources[0x34]	903	1			T1	25		T2	2		T3	4
valid_sources[0x35]	846	1			T3	2		T15	5		T16	1
valid_sources[0x36]	1432	1			T1	4		T13	3		T3	3
valid_sources[0x37]	854	1			T1	2		T2	3		T13	1
valid_sources[0x38]	1068	1			T3	1		T15	2		T6	4
valid_sources[0x39]	807	1			T1	2		T2	4		T16	1
valid_sources[0x3a]	867	1			T3	5		T15	4		T6	2
valid_sources[0x3b]	967	1			T2	5		T3	4		T15	4
valid_sources[0x3c]	867	1			T1	9		T13	1		T3	7
valid_sources[0x3d]	1067	1			T1	1		T3	4		T6	1
valid_sources[0x3e]	879	1			T3	9		T6	4		T28	27
valid_sources[0x3f]	755	1			T1	14		T13	1		T3	6
valid_sources[0x40]	1009	1			T1	11		T13	4		T3	3
valid_sources[0x41]	780	1			T6	3		T9	2		T10	4
valid_sources[0x42]	911	1			T13	2		T3	5		T16	1
valid_sources[0x43]	988	1			T1	11		T3	2		T6	1
valid_sources[0x44]	1058	1			T13	1		T3	2		T16	2
valid_sources[0x45]	1048	1			T13	1		T3	6		T6	3
valid_sources[0x46]	1819	1			T3	6		T6	3		T17	1
valid_sources[0x47]	1014	1			T13	2		T3	3		T15	3
valid_sources[0x48]	1060	1			T2	5		T13	1		T3	8
valid_sources[0x49]	793	1			T3	2		T15	1		T6	2
valid_sources[0x4a]	803	1			T1	3		T13	1		T3	1
valid_sources[0x4b]	1145	1			T3	3		T6	1		T28	6
valid_sources[0x4c]	1949	1			T3	4		T15	8		T6	2
valid_sources[0x4d]	677	1			T3	4		T17	1		T8	3
valid_sources[0x4e]	851	1			T13	1		T3	3		T15	3
valid_sources[0x4f]	913	1			T3	2		T15	3		T16	3
valid_sources[0x50]	737	1			T2	1		T3	6		T15	2
valid_sources[0x51]	1102	1			T2	2		T13	1		T3	7
valid_sources[0x52]	1604	1			T2	4		T3	5		T28	5
valid_sources[0x53]	1219	1			T3	4		T15	6		T6	4
valid_sources[0x54]	1982	1			T1	6		T13	1		T15	1
valid_sources[0x55]	1065	1			T3	1		T15	4		T6	6
valid_sources[0x56]	1027	1			T13	1		T3	4		T15	1
valid_sources[0x57]	1448	1			T1	3		T13	1		T3	4
valid_sources[0x58]	869	1			T3	4		T15	3		T16	1
valid_sources[0x59]	1762	1			T13	1		T3	1		T15	6
valid_sources[0x5a]	1186	1			T13	1		T3	3		T15	7
valid_sources[0x5b]	786	1			T13	1		T3	3		T15	1
valid_sources[0x5c]	994	1			T1	10		T3	4		T6	1
valid_sources[0x5d]	798	1			T1	2		T2	1		T3	4
valid_sources[0x5e]	878	1			T13	1		T3	3		T15	1
valid_sources[0x5f]	1265	1			T13	2		T3	1		T15	1
valid_sources[0x60]	1175	1			T1	3		T3	5		T15	7
valid_sources[0x61]	817	1			T3	2		T15	1		T6	1
valid_sources[0x62]	843	1			T13	1		T3	5		T15	3
valid_sources[0x63]	1091	1			T3	5		T16	2		T6	1
valid_sources[0x64]	936	1			T13	1		T3	6		T6	1
valid_sources[0x65]	1311	1			T1	7		T3	2		T15	4
valid_sources[0x66]	1288	1			T1	1		T13	4		T3	2
valid_sources[0x67]	979	1			T1	3		T3	4		T15	6
valid_sources[0x68]	939	1			T13	1		T3	6		T15	6
valid_sources[0x69]	783	1			T1	9		T3	5		T15	1
valid_sources[0x6a]	908	1			T13	2		T3	1		T15	4
valid_sources[0x6b]	895	1			T3	7		T15	2		T6	2
valid_sources[0x6c]	814	1			T2	1		T13	1		T3	1
valid_sources[0x6d]	857	1			T1	9		T13	1		T3	2
valid_sources[0x6e]	1759	1			T3	8		T15	1		T6	6
valid_sources[0x6f]	879	1			T3	6		T6	2		T10	3
valid_sources[0x70]	842	1			T2	1		T3	2		T15	1
valid_sources[0x71]	820	1			T1	4		T3	1		T15	4
valid_sources[0x72]	1068	1			T1	28		T3	1		T15	7
valid_sources[0x73]	743	1			T2	1		T13	1		T3	2
valid_sources[0x74]	1372	1			T2	1		T3	3		T16	1
valid_sources[0x75]	1190	1			T3	1		T15	2		T16	2
valid_sources[0x76]	799	1			T13	3		T3	3		T15	1
valid_sources[0x77]	1269	1			T1	2		T3	2		T6	1
valid_sources[0x78]	1095	1			T3	4		T16	1		T8	13
valid_sources[0x79]	784	1			T1	6		T13	1		T3	6
valid_sources[0x7a]	955	1			T1	4		T13	1		T3	4
valid_sources[0x7b]	1107	1			T2	2		T3	4		T6	2
valid_sources[0x7c]	822	1			T13	1		T3	1		T15	2
valid_sources[0x7d]	1137	1			T3	5		T46	33		T28	2
valid_sources[0x7e]	1148	1			T3	1		T6	3		T29	1
valid_sources[0x7f]	893	1			T3	5		T15	1		T6	1
valid_sources[0x80]	1256	1			T1	2		T3	4		T15	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

62687

1

T4

12

T5

1

T1

208

values[0x0]

all_enables

biggest_size

32678

1

T4

17

T1

29

T2

16

values[0x1]

all_enables

biggest_size

23498

1

T4

8

T1

26

T2

12