Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1230830570	11567	0	0
auto_block_debounce_ctl_rd_A	1230830570	1594	0	0
auto_block_out_ctl_rd_A	1230830570	2021	0	0
com_det_ctl_0_rd_A	1230830570	4321	0	0
com_det_ctl_1_rd_A	1230830570	4292	0	0
com_det_ctl_2_rd_A	1230830570	4460	0	0
com_det_ctl_3_rd_A	1230830570	4204	0	0
com_out_ctl_0_rd_A	1230830570	4718	0	0
com_out_ctl_1_rd_A	1230830570	4885	0	0
com_out_ctl_2_rd_A	1230830570	4527	0	0
com_out_ctl_3_rd_A	1230830570	4845	0	0
com_pre_det_ctl_0_rd_A	1230830570	1283	0	0
com_pre_det_ctl_1_rd_A	1230830570	1361	0	0
com_pre_det_ctl_2_rd_A	1230830570	1356	0	0
com_pre_det_ctl_3_rd_A	1230830570	1335	0	0
com_pre_sel_ctl_0_rd_A	1230830570	5005	0	0
com_pre_sel_ctl_1_rd_A	1230830570	5054	0	0
com_pre_sel_ctl_2_rd_A	1230830570	4712	0	0
com_pre_sel_ctl_3_rd_A	1230830570	4838	0	0
com_sel_ctl_0_rd_A	1230830570	4924	0	0
com_sel_ctl_1_rd_A	1230830570	4790	0	0
com_sel_ctl_2_rd_A	1230830570	4887	0	0
com_sel_ctl_3_rd_A	1230830570	4868	0	0
ec_rst_ctl_rd_A	1230830570	2505	0	0
intr_enable_rd_A	1230830570	1745	0	0
key_intr_ctl_rd_A	1230830570	3775	0	0
key_intr_debounce_ctl_rd_A	1230830570	1305	0	0
key_invert_ctl_rd_A	1230830570	4875	0	0
pin_allowed_ctl_rd_A	1230830570	5283	0	0
pin_out_ctl_rd_A	1230830570	4381	0	0
pin_out_value_rd_A	1230830570	4535	0	0
regwen_rd_A	1230830570	1565	0	0
ulp_ac_debounce_ctl_rd_A	1230830570	1563	0	0
ulp_ctl_rd_A	1230830570	1262	0	0
ulp_lid_debounce_ctl_rd_A	1230830570	1373	0	0
ulp_pwrb_debounce_ctl_rd_A	1230830570	1592	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1230830570	11567	0	0
T21	123675	10	0	0
T22	55904	0	0	0
T26	23354	0	0	0
T27	0	22	0	0
T31	418662	0	0	0
T34	622249	0	0	0
T35	13969	0	0	0
T36	55421	0	0	0
T44	0	28	0	0
T48	0	2	0	0
T72	138849	0	0	0
T82	0	21	0	0
T112	48829	0	0	0
T113	111117	0	0	0
T116	0	22	0	0
T118	0	8	0	0
T141	0	8	0	0
T196	0	14	0	0
T276	0	2	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1230830570	1594	0	0
T50	68502	12	0	0
T51	35720	0	0	0
T75	317543	0	0	0
T78	150967	0	0	0
T85	482547	0	0	0
T111	0	6	0	0
T115	272255	0	0	0
T141	0	19	0	0
T183	0	17	0	0
T231	0	7	0	0
T242	895874	0	0	0
T244	0	16	0	0
T276	0	22	0	0
T277	0	6	0	0
T278	0	5	0	0
T279	0	7	0	0
T280	198544	0	0	0
T281	242676	0	0	0
T282	194574	0	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1230830570	2021	0	0
T50	68502	10	0	0
T51	35720	0	0	0
T75	317543	0	0	0
T78	150967	0	0	0
T85	482547	0	0	0
T115	272255	0	0	0
T141	0	9	0	0
T183	0	3	0	0
T184	0	2	0	0
T231	0	5	0	0
T242	895874	0	0	0
T244	0	29	0	0
T276	0	22	0	0
T277	0	11	0	0
T278	0	5	0	0
T279	0	3	0	0
T280	198544	0	0	0
T281	242676	0	0	0
T282	194574	0	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1230830570	4321	0	0
T8	636707	87	0	0
T12	0	107	0	0
T23	235051	0	0	0
T28	588208	21	0	0
T29	137636	0	0	0
T47	22146	0	0	0
T53	27607	0	0	0
T54	18796	0	0	0
T55	193019	0	0	0
T56	62956	0	0	0
T73	0	57	0	0
T85	0	67	0	0
T88	0	95	0	0
T90	0	54	0	0
T188	47884	0	0	0
T240	0	43	0	0
T242	0	55	0	0
T251	0	84	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1230830570	4292	0	0
T8	636707	61	0	0
T12	0	98	0	0
T23	235051	0	0	0
T28	588208	22	0	0
T29	137636	0	0	0
T47	22146	0	0	0
T53	27607	0	0	0
T54	18796	0	0	0
T55	193019	0	0	0
T56	62956	0	0	0
T73	0	81	0	0
T85	0	58	0	0
T88	0	78	0	0
T90	0	46	0	0
T188	47884	0	0	0
T240	0	62	0	0
T242	0	46	0	0
T251	0	49	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1230830570	4460	0	0
T8	636707	58	0	0
T12	0	89	0	0
T23	235051	0	0	0
T28	588208	37	0	0
T29	137636	0	0	0
T47	22146	0	0	0
T53	27607	0	0	0
T54	18796	0	0	0
T55	193019	0	0	0
T56	62956	0	0	0
T73	0	51	0	0
T85	0	55	0	0
T88	0	94	0	0
T90	0	54	0	0
T188	47884	0	0	0
T240	0	42	0	0
T242	0	28	0	0
T251	0	47	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1230830570	4204	0	0
T8	636707	69	0	0
T12	0	80	0	0
T23	235051	0	0	0
T28	588208	26	0	0
T29	137636	0	0	0
T47	22146	0	0	0
T53	27607	0	0	0
T54	18796	0	0	0
T55	193019	0	0	0
T56	62956	0	0	0
T73	0	72	0	0
T85	0	47	0	0
T88	0	69	0	0
T90	0	34	0	0
T188	47884	0	0	0
T240	0	46	0	0
T242	0	33	0	0
T251	0	86	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1230830570	4718	0	0
T8	636707	63	0	0
T12	0	95	0	0
T23	235051	0	0	0
T28	588208	44	0	0
T29	137636	0	0	0
T47	22146	0	0	0
T53	27607	0	0	0
T54	18796	0	0	0
T55	193019	0	0	0
T56	62956	0	0	0
T73	0	49	0	0
T85	0	83	0	0
T88	0	70	0	0
T90	0	34	0	0
T188	47884	0	0	0
T240	0	42	0	0
T242	0	43	0	0
T251	0	77	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1230830570	4885	0	0
T8	636707	84	0	0
T12	0	77	0	0
T23	235051	0	0	0
T28	588208	30	0	0
T29	137636	0	0	0
T47	22146	0	0	0
T53	27607	0	0	0
T54	18796	0	0	0
T55	193019	0	0	0
T56	62956	0	0	0
T73	0	57	0	0
T85	0	64	0	0
T88	0	67	0	0
T90	0	52	0	0
T188	47884	0	0	0
T240	0	55	0	0
T242	0	48	0	0
T251	0	59	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1230830570	4527	0	0
T8	636707	73	0	0
T12	0	104	0	0
T23	235051	0	0	0
T28	588208	11	0	0
T29	137636	0	0	0
T47	22146	0	0	0
T53	27607	0	0	0
T54	18796	0	0	0
T55	193019	0	0	0
T56	62956	0	0	0
T73	0	54	0	0
T85	0	42	0	0
T88	0	64	0	0
T90	0	32	0	0
T188	47884	0	0	0
T240	0	54	0	0
T242	0	46	0	0
T251	0	67	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1230830570	4845	0	0
T8	636707	61	0	0
T12	0	93	0	0
T23	235051	0	0	0
T28	588208	25	0	0
T29	137636	0	0	0
T47	22146	0	0	0
T53	27607	0	0	0
T54	18796	0	0	0
T55	193019	0	0	0
T56	62956	0	0	0
T73	0	66	0	0
T85	0	48	0	0
T88	0	82	0	0
T90	0	33	0	0
T188	47884	0	0	0
T240	0	57	0	0
T242	0	60	0	0
T251	0	72	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1230830570	1283	0	0
T81	57873	0	0	0
T91	0	3	0	0
T121	0	9	0	0
T122	0	16	0	0
T125	168682	0	0	0
T126	260185	0	0	0
T127	195325	0	0	0
T141	0	16	0	0
T146	0	19	0	0
T149	0	5	0	0
T151	0	22	0	0
T198	288204	0	0	0
T244	0	14	0	0
T254	0	42	0	0
T276	734462	21	0	0
T283	127837	0	0	0
T284	51022	0	0	0
T285	50256	0	0	0
T286	30330	0	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1230830570	1361	0	0
T81	57873	0	0	0
T91	0	1	0	0
T121	0	9	0	0
T122	0	13	0	0
T125	168682	0	0	0
T126	260185	0	0	0
T127	195325	0	0	0
T141	0	5	0	0
T146	0	16	0	0
T149	0	30	0	0
T184	0	6	0	0
T198	288204	0	0	0
T244	0	16	0	0
T254	0	33	0	0
T276	734462	12	0	0
T283	127837	0	0	0
T284	51022	0	0	0
T285	50256	0	0	0
T286	30330	0	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1230830570	1356	0	0
T81	57873	0	0	0
T91	0	2	0	0
T121	0	10	0	0
T122	0	15	0	0
T125	168682	0	0	0
T126	260185	0	0	0
T127	195325	0	0	0
T141	0	14	0	0
T146	0	5	0	0
T149	0	20	0	0
T184	0	3	0	0
T198	288204	0	0	0
T244	0	13	0	0
T254	0	14	0	0
T276	734462	23	0	0
T283	127837	0	0	0
T284	51022	0	0	0
T285	50256	0	0	0
T286	30330	0	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1230830570	1335	0	0
T81	57873	0	0	0
T91	0	2	0	0
T121	0	16	0	0
T122	0	14	0	0
T125	168682	0	0	0
T126	260185	0	0	0
T127	195325	0	0	0
T141	0	16	0	0
T146	0	9	0	0
T149	0	23	0	0
T184	0	9	0	0
T198	288204	0	0	0
T244	0	10	0	0
T254	0	28	0	0
T276	734462	19	0	0
T283	127837	0	0	0
T284	51022	0	0	0
T285	50256	0	0	0
T286	30330	0	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1230830570	5005	0	0
T8	636707	75	0	0
T12	0	92	0	0
T23	235051	0	0	0
T28	588208	15	0	0
T29	137636	0	0	0
T47	22146	0	0	0
T53	27607	0	0	0
T54	18796	0	0	0
T55	193019	0	0	0
T56	62956	0	0	0
T73	0	55	0	0
T85	0	47	0	0
T88	0	54	0	0
T90	0	41	0	0
T188	47884	0	0	0
T240	0	60	0	0
T242	0	64	0	0
T251	0	86	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1230830570	5054	0	0
T8	636707	54	0	0
T12	0	98	0	0
T23	235051	0	0	0
T28	588208	20	0	0
T29	137636	0	0	0
T47	22146	0	0	0
T53	27607	0	0	0
T54	18796	0	0	0
T55	193019	0	0	0
T56	62956	0	0	0
T73	0	50	0	0
T85	0	54	0	0
T88	0	55	0	0
T90	0	51	0	0
T188	47884	0	0	0
T240	0	48	0	0
T242	0	46	0	0
T251	0	75	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1230830570	4712	0	0
T8	636707	58	0	0
T12	0	95	0	0
T23	235051	0	0	0
T28	588208	20	0	0
T29	137636	0	0	0
T47	22146	0	0	0
T53	27607	0	0	0
T54	18796	0	0	0
T55	193019	0	0	0
T56	62956	0	0	0
T73	0	72	0	0
T85	0	45	0	0
T88	0	75	0	0
T90	0	32	0	0
T188	47884	0	0	0
T240	0	76	0	0
T242	0	40	0	0
T251	0	79	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1230830570	4838	0	0
T8	636707	79	0	0
T12	0	90	0	0
T23	235051	0	0	0
T28	588208	19	0	0
T29	137636	0	0	0
T47	22146	0	0	0
T53	27607	0	0	0
T54	18796	0	0	0
T55	193019	0	0	0
T56	62956	0	0	0
T73	0	46	0	0
T85	0	71	0	0
T88	0	66	0	0
T90	0	22	0	0
T188	47884	0	0	0
T240	0	42	0	0
T242	0	47	0	0
T251	0	76	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1230830570	4924	0	0
T8	636707	81	0	0
T12	0	105	0	0
T23	235051	0	0	0
T28	588208	24	0	0
T29	137636	0	0	0
T47	22146	0	0	0
T53	27607	0	0	0
T54	18796	0	0	0
T55	193019	0	0	0
T56	62956	0	0	0
T73	0	58	0	0
T85	0	50	0	0
T88	0	91	0	0
T90	0	48	0	0
T188	47884	0	0	0
T240	0	49	0	0
T242	0	46	0	0
T251	0	79	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1230830570	4790	0	0
T8	636707	71	0	0
T12	0	69	0	0
T23	235051	0	0	0
T28	588208	55	0	0
T29	137636	0	0	0
T47	22146	0	0	0
T53	27607	0	0	0
T54	18796	0	0	0
T55	193019	0	0	0
T56	62956	0	0	0
T73	0	39	0	0
T85	0	63	0	0
T88	0	87	0	0
T90	0	34	0	0
T188	47884	0	0	0
T240	0	44	0	0
T242	0	32	0	0
T251	0	54	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1230830570	4887	0	0
T8	636707	59	0	0
T12	0	77	0	0
T23	235051	0	0	0
T28	588208	22	0	0
T29	137636	0	0	0
T47	22146	0	0	0
T53	27607	0	0	0
T54	18796	0	0	0
T55	193019	0	0	0
T56	62956	0	0	0
T73	0	65	0	0
T85	0	51	0	0
T88	0	91	0	0
T90	0	23	0	0
T188	47884	0	0	0
T240	0	71	0	0
T242	0	48	0	0
T251	0	61	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1230830570	4868	0	0
T8	636707	58	0	0
T12	0	100	0	0
T23	235051	0	0	0
T28	588208	19	0	0
T29	137636	0	0	0
T47	22146	0	0	0
T53	27607	0	0	0
T54	18796	0	0	0
T55	193019	0	0	0
T56	62956	0	0	0
T73	0	72	0	0
T85	0	48	0	0
T88	0	94	0	0
T90	0	49	0	0
T188	47884	0	0	0
T240	0	56	0	0
T242	0	47	0	0
T251	0	62	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1230830570	2505	0	0
T8	636707	24	0	0
T12	0	52	0	0
T23	235051	0	0	0
T28	588208	6	0	0
T29	137636	0	0	0
T45	0	10	0	0
T47	22146	0	0	0
T53	27607	0	0	0
T54	18796	8	0	0
T55	193019	0	0	0
T56	62956	0	0	0
T69	0	3	0	0
T73	0	15	0	0
T85	0	12	0	0
T86	0	2	0	0
T188	47884	0	0	0
T242	0	7	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1230830570	1745	0	0
T81	57873	0	0	0
T121	0	26	0	0
T122	0	42	0	0
T125	168682	0	0	0
T126	260185	0	0	0
T127	195325	0	0	0
T141	0	12	0	0
T146	0	25	0	0
T149	0	17	0	0
T184	0	29	0	0
T198	288204	0	0	0
T244	0	44	0	0
T254	0	52	0	0
T276	734462	30	0	0
T283	127837	0	0	0
T284	51022	0	0	0
T285	50256	0	0	0
T286	30330	0	0	0
T287	0	9	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1230830570	3775	0	0
T39	31753	7	0	0
T66	237735	0	0	0
T89	527446	0	0	0
T90	335102	0	0	0
T91	0	4	0	0
T141	0	15	0	0
T177	0	1	0	0
T184	0	14	0	0
T189	0	1	0	0
T197	0	2	0	0
T244	0	17	0	0
T250	672174	0	0	0
T251	447511	0	0	0
T276	0	14	0	0
T288	0	6	0	0
T289	107310	0	0	0
T290	58821	0	0	0
T291	238561	0	0	0
T292	209039	0	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1230830570	1305	0	0
T81	57873	0	0	0
T121	0	5	0	0
T122	0	19	0	0
T125	168682	0	0	0
T126	260185	0	0	0
T127	195325	0	0	0
T141	0	10	0	0
T146	0	12	0	0
T149	0	5	0	0
T151	0	28	0	0
T184	0	3	0	0
T198	288204	0	0	0
T244	0	6	0	0
T254	0	22	0	0
T276	734462	26	0	0
T283	127837	0	0	0
T284	51022	0	0	0
T285	50256	0	0	0
T286	30330	0	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1230830570	4875	0	0
T9	346974	0	0	0
T10	374909	0	0	0
T11	97909	0	0	0
T12	405799	0	0	0
T23	235051	57	0	0
T24	59841	0	0	0
T25	0	52	0	0
T56	62956	0	0	0
T57	221684	0	0	0
T67	0	82	0	0
T68	0	65	0	0
T69	31401	0	0	0
T70	51451	0	0	0
T141	0	68	0	0
T208	0	87	0	0
T244	0	255	0	0
T276	0	23	0	0
T293	0	63	0	0
T294	0	30	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1230830570	5283	0	0
T3	576131	0	0	0
T6	560499	0	0	0
T7	17392	0	0	0
T14	250994	93	0	0
T15	132723	0	0	0
T16	60739	0	0	0
T17	123092	0	0	0
T28	588208	0	0	0
T46	334365	0	0	0
T53	27607	0	0	0
T91	0	2	0	0
T141	0	126	0	0
T184	0	81	0	0
T276	0	16	0	0
T291	0	71	0	0
T295	0	52	0	0
T296	0	39	0	0
T297	0	41	0	0
T298	0	94	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1230830570	4381	0	0
T3	576131	0	0	0
T6	560499	0	0	0
T7	17392	0	0	0
T14	250994	57	0	0
T15	132723	0	0	0
T16	60739	0	0	0
T17	123092	0	0	0
T28	588208	0	0	0
T46	334365	0	0	0
T53	27607	0	0	0
T141	0	154	0	0
T184	0	123	0	0
T244	0	13	0	0
T276	0	21	0	0
T291	0	93	0	0
T295	0	33	0	0
T296	0	26	0	0
T297	0	34	0	0
T298	0	63	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1230830570	4535	0	0
T3	576131	0	0	0
T6	560499	0	0	0
T7	17392	0	0	0
T14	250994	63	0	0
T15	132723	0	0	0
T16	60739	0	0	0
T17	123092	0	0	0
T28	588208	0	0	0
T46	334365	0	0	0
T53	27607	0	0	0
T141	0	164	0	0
T184	0	97	0	0
T244	0	10	0	0
T276	0	20	0	0
T291	0	80	0	0
T295	0	35	0	0
T296	0	35	0	0
T297	0	53	0	0
T298	0	85	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1230830570	1565	0	0
T81	57873	0	0	0
T91	0	6	0	0
T121	0	13	0	0
T122	0	15	0	0
T125	168682	0	0	0
T126	260185	0	0	0
T127	195325	0	0	0
T141	0	19	0	0
T146	0	10	0	0
T149	0	7	0	0
T184	0	12	0	0
T198	288204	0	0	0
T244	0	12	0	0
T254	0	24	0	0
T276	734462	9	0	0
T283	127837	0	0	0
T284	51022	0	0	0
T285	50256	0	0	0
T286	30330	0	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1230830570	1563	0	0
T81	57873	12	0	0
T83	0	11	0	0
T91	0	2	0	0
T125	168682	0	0	0
T126	260185	0	0	0
T127	195325	0	0	0
T141	0	13	0	0
T184	0	31	0	0
T189	0	3	0	0
T198	288204	0	0	0
T244	0	17	0	0
T254	0	24	0	0
T276	734462	21	0	0
T283	127837	0	0	0
T284	51022	0	0	0
T285	50256	0	0	0
T286	30330	0	0	0
T299	0	1	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1230830570	1262	0	0
T81	57873	7	0	0
T83	0	2	0	0
T91	0	7	0	0
T125	168682	0	0	0
T126	260185	0	0	0
T127	195325	0	0	0
T141	0	16	0	0
T184	0	24	0	0
T189	0	1	0	0
T198	288204	0	0	0
T244	0	5	0	0
T254	0	31	0	0
T276	734462	22	0	0
T283	127837	0	0	0
T284	51022	0	0	0
T285	50256	0	0	0
T286	30330	0	0	0
T300	0	2	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1230830570	1373	0	0
T81	57873	8	0	0
T83	0	11	0	0
T121	0	10	0	0
T122	0	9	0	0
T125	168682	0	0	0
T126	260185	0	0	0
T127	195325	0	0	0
T141	0	12	0	0
T184	0	21	0	0
T189	0	6	0	0
T198	288204	0	0	0
T244	0	3	0	0
T254	0	30	0	0
T276	734462	29	0	0
T283	127837	0	0	0
T284	51022	0	0	0
T285	50256	0	0	0
T286	30330	0	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1230830570	1592	0	0
T81	57873	11	0	0
T83	0	7	0	0
T91	0	20	0	0
T125	168682	0	0	0
T126	260185	0	0	0
T127	195325	0	0	0
T141	0	18	0	0
T184	0	11	0	0
T198	288204	0	0	0
T244	0	19	0	0
T254	0	39	0	0
T276	734462	19	0	0
T283	127837	0	0	0
T284	51022	0	0	0
T285	50256	0	0	0
T286	30330	0	0	0
T299	0	2	0	0
T300	0	1	0	0