SYSRST_CTRL Simulation Results

Sunday March 24 2024 19:02:40 UTC

GitHub Revision: `70ad420931`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 56687816123908180356912499273064417112757374299033127319246303583078997854118

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	6.500s	2.113ms	50	50	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	8.280s	2.477ms	50	50	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	3.500s	2.426ms	5	5	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	7.070s	2.538ms	5	5	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	11.570s	4.010ms	5	5	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	6.280s	2.038ms	20	20	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	4.912m	59.310ms	5	5	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	9.740s	2.933ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	7.000s	2.106ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	6.280s	2.038ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	9.740s	2.933ms	5	5	100.00
V1		TOTAL			165	165	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	8.173m	183.335ms	50	50	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	14.183m	328.522ms	95	100	95.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	3.321m	325.210ms	48	50	96.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	15.004m	336.629ms	50	50	100.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	7.590s	2.510ms	50	50	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	6.840s	2.257ms	50	50	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	25.798m	566.872ms	50	50	100.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	8.100s	2.611ms	50	50	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	9.575m	1.871s	44	50	88.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	54.150s	41.613ms	2	2	100.00
V2	stress_all	sysrst_ctrl_stress_all	14.258m	1.317s	49	50	98.00
V2	alert_test	sysrst_ctrl_alert_test	6.290s	2.014ms	50	50	100.00
V2	intr_test	sysrst_ctrl_intr_test	6.920s	2.012ms	50	50	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	8.540s	2.187ms	20	20	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	8.540s	2.187ms	20	20	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	11.570s	4.010ms	5	5	100.00
		sysrst_ctrl_csr_rw	6.280s	2.038ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	9.740s	2.933ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	27.870s	9.840ms	20	20	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	11.570s	4.010ms	5	5	100.00
		sysrst_ctrl_csr_rw	6.280s	2.038ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	9.740s	2.933ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	27.870s	9.840ms	20	20	100.00
V2		TOTAL			678	692	97.98
V2S	tl_intg_err	sysrst_ctrl_sec_cm	58.790s	42.014ms	5	5	100.00
		sysrst_ctrl_tl_intg_err	1.914m	42.436ms	20	20	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	1.914m	42.436ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	5.616m	1.151s	43	50	86.00
V3		TOTAL			43	50	86.00
		TOTAL			911	932	97.75

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	15	15	11	73.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.00	98.81	96.76	100.00	95.51	98.26	99.52	90.11

Failure Buckets

UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) has 9 failures:

Test sysrst_ctrl_ultra_low_pwr has 6 failures.

0.sysrst_ctrl_ultra_low_pwr.27283107230755113749913634299624276040574929583201988742196120417297882365975
Line 558, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 2480560935 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 254753060935 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i
  UVM_INFO @ 2142713060935 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i
  UVM_INFO @ 3022998060935 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
  UVM_INFO @ 3023014559447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

6.sysrst_ctrl_ultra_low_pwr.95110535180600095902268811859122335649622147727273558801670574506222538047997
Line 558, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 2382463646 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 2424963646 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:95) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a L2H transition on lid_open_i
  UVM_INFO @ 4594963646 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
  UVM_INFO @ 4614034861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test sysrst_ctrl_stress_all_with_rand_reset has 2 failures.

5.sysrst_ctrl_stress_all_with_rand_reset.55946255138795178446767533915755697834657799284596890526056230853613162138272
Line 572, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 13850271899 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 14022771899 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:95) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a L2H transition on lid_open_i
  UVM_INFO @ 15217771899 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
  UVM_INFO @ 15237374725 ps: (sysrst_ctrl_stress_all_vseq.sv:52) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_stress_all_vseq] body: executing sequence sysrst_ctrl_combo_detect_ec_rst_vseq
  UVM_INFO @ 17232849022 ps: (sysrst_ctrl_combo_detect_ec_rst_vseq.sv:44) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_ec_rst_vseq] Starting the body from combo detect ec_rst

17.sysrst_ctrl_stress_all_with_rand_reset.40980307043093251241397595697382441635538511845148066335896147608032979083347
Line 573, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 9459227612 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_ERROR @ 11306727612 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 11306727612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test sysrst_ctrl_stress_all has 1 failures.

49.sysrst_ctrl_stress_all.107222572719029710331436989636499393260326897064192825736563774755846812119229
Line 559, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 4329494510 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_ERROR @ 6671994510 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 6671994510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_flash_wr_prot_vseq.sv:55) [sysrst_ctrl_flash_wr_prot_vseq] Check failed cfg.vif.flash_wp_l == * (* [*] vs * [*]) has 3 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 3 failures.

12.sysrst_ctrl_stress_all_with_rand_reset.43624475862766997587853239375904710630721326627613538497201530874187607152345
Line 632, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 42225566346 ps: (sysrst_ctrl_flash_wr_prot_vseq.sv:55) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_flash_wr_prot_vseq] Check failed cfg.vif.flash_wp_l == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 42236604813 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
  Stress w/ reset is done for run 5/10
  UVM_INFO @ 42237528409 ps: (dv_base_reg.sv:325) [sysrst_ctrl_reg_block.regwen] lock_lockable_flds          1 val
  UVM_INFO @ 42238549226 ps: (cip_base_vseq.sv:717) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] running run_seq_with_rand_reset_vseq iteration 6/10

28.sysrst_ctrl_stress_all_with_rand_reset.36428488403510159977028088968872068507619482299760683671722640770535718680677
Line 583, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 11144474100 ps: (sysrst_ctrl_flash_wr_prot_vseq.sv:55) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_flash_wr_prot_vseq] Check failed cfg.vif.flash_wp_l == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 11151589021 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
  Stress w/ reset is done for run 2/10
  UVM_INFO @ 11154229397 ps: (dv_base_reg.sv:325) [sysrst_ctrl_reg_block.regwen] lock_lockable_flds          1 val
  UVM_INFO @ 11154229397 ps: (cip_base_vseq.sv:717) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] running run_seq_with_rand_reset_vseq iteration 3/10

... and 1 more failures.

UVM_ERROR (sysrst_ctrl_auto_blk_key_output_vseq.sv:122) [sysrst_ctrl_auto_blk_key_output_vseq] Check failed override_key2_out_value == cfg.vif.key2_out (* [*] vs * [*]) has 2 failures:

Test sysrst_ctrl_auto_blk_key_output has 2 failures.

2.sysrst_ctrl_auto_blk_key_output.48639077594910754016694892503850537424761343186531468561283625355025906681737
Line 560, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_auto_blk_key_output/latest/run.log

  UVM_ERROR @ 2313335730 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Check failed override_key2_out_value == cfg.vif.key2_out (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 2413432318 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:88) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Debounce timer set for: 59
  UVM_INFO @ 2933335730 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:100) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Value of cycles:90
  UVM_INFO @ 3038428568 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:88) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Debounce timer set for: 2d
  UVM_INFO @ 3378335730 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:100) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Value of cycles:54

28.sysrst_ctrl_auto_blk_key_output.35764124590697166806760937940169670068055618733395727664592764791583297397052
Line 560, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_auto_blk_key_output/latest/run.log

  UVM_ERROR @ 2327049298 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Check failed override_key2_out_value == cfg.vif.key2_out (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 2427272403 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:88) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Debounce timer set for: 49
  UVM_INFO @ 2872049298 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:100) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Value of cycles:63
  UVM_INFO @ 2992165843 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:88) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Debounce timer set for: e
  UVM_INFO @ 3202049298 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:100) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Value of cycles:17

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [*] vs * [*]) has 2 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 2 failures.

15.sysrst_ctrl_combo_detect_with_pre_cond.36913612917327461993452263108971116838789647499325342772173082867568942281340
Line 639, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 83343051679 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 83343051679 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 83343051679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

83.sysrst_ctrl_combo_detect_with_pre_cond.15977148411103545558731405500060205570295557638046067505538067754088681991030
Line 586, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/83.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 25576307655 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 25681307655 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
  UVM_INFO @ 25701307655 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
  UVM_INFO @ 35915095242 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x30
  UVM_INFO @ 35915324405 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x1e

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*]) has 2 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 2 failures.

27.sysrst_ctrl_combo_detect_with_pre_cond.3028060581928181813035630223210395996870631238850385052816846425543001725995
Line 606, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 75716951815 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 75716951815 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 75716951815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

92.sysrst_ctrl_combo_detect_with_pre_cond.69401984448960470964316984527781214029748833377478000649422146368520058701281
Line 571, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/92.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 25860705093 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 25860705093 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 25860705093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(7) vs exp(2) +/-* has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

4.sysrst_ctrl_combo_detect_with_pre_cond.3385308309600854561088479829684112721003639143593044874868858683975175540084
Line 586, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 37584812872 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(7) vs exp(2) +/-4
  UVM_INFO @ 47740252532 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x15
  UVM_INFO @ 47740273366 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x1c
  UVM_INFO @ 49609864441 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 1
  UVM_INFO @ 49609906109 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 3

UVM_FATAL (cip_base_vseq.sv:104) [sysrst_ctrl_common_vseq] wait timeout occurred! has 1 failures:
- Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.
  - 26.sysrst_ctrl_stress_all_with_rand_reset.107785147967001094046808619696416341835391966032213192725309631696108739719899
    Line 582, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 21606452094 ps: (cip_base_vseq.sv:104) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] wait timeout occurred!
  UVM_INFO @ 21606452094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sysrst_ctrl_reg_block.combo_intr_status reset value: * has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

29.sysrst_ctrl_stress_all_with_rand_reset.46243416533219459834250993374085706976753396802611914882029830026968834126762
Line 583, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 13882421488 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sysrst_ctrl_reg_block.combo_intr_status reset value: 0x0
  UVM_INFO @ 14091827976 ps: (sysrst_ctrl_stress_all_vseq.sv:52) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_stress_all_vseq] body: executing sequence sysrst_ctrl_common_vseq
  UVM_INFO @ 16087403848 ps: (cip_base_vseq.sv:442) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Running intr test iteration 1/3
  UVM_INFO @ 16087648744 ps: (cip_base_vseq.sv:442) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Running intr test iteration 2/3
  UVM_INFO @ 16087893640 ps: (cip_base_vseq.sv:442) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Running intr test iteration 3/3