Unified Coverage Report :: Group Instance : sysrst_ctrl_combo_intr_status_cg

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1427

1

T1

12

T5

5

T2

6

auto[1]

1923

1

T1

10

T5

15

T2

17

---

Summary for Variable cp_combo0_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo0_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2820

1

T1

18

T5

20

T2

20

auto[1]

530

1

T1

4

T2

3

T4

15

---

Summary for Variable cp_combo1_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo1_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3186

1

T1

20

T5

20

T2

20

auto[1]

164

1

T1

2

T2

3

T4

3

---

Summary for Variable cp_combo2_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo2_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3134

1

T1

22

T5

20

T2

23

auto[1]

216

1

T4

5

T10

12

T32

2

---

Summary for Variable cp_combo3_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo3_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3161

1

T1

21

T5

20

T2

23

auto[1]

189

1

T1

1

T4

2

T10

1

---

Summary for Variable cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_interrupt

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2119

1

T1

1

T5

1

T2

23

auto[1]

1231

1

T1

21

T5

19

T4

18

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1371

1

T1

10

T5

11

T2

14

auto[1]

1979

1

T1

12

T5

9

T2

9

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1410

1

T1

9

T5

9

T2

6

auto[1]

1940

1

T1

13

T5

11

T2

17

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1287

1

T1

10

T5

7

T2

9

auto[1]

2063

1

T1

12

T5

13

T2

14

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1427

1

T1

11

T5

12

T2

11

auto[1]

1923

1

T1

11

T5

8

T2

12

---

Summary for Cross cross_combo0

Samples crossed: cp_combo0_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	0	96	100.00
Automatically Generated Cross Bins	96	0	96	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo0

Bins

cp_combo0_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

62

1

T2

1

T4

1

T12

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

16

1

T1

1

T5

1

T129

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

44

1

T10

1

T11

2

T32

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

10

1

T1

1

T5

1

T95

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

49

1

T11

1

T12

1

T117

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

8

1

T227

1

T339

1

T269

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

46

1

T285

1

T340

1

T260

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

25

1

T340

1

T341

1

T269

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

52

1

T2

1

T11

1

T41

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

24

1

T5

1

T4

1

T52

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

51

1

T7

1

T12

2

T39

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

18

1

T1

1

T5

1

T34

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

41

1

T2

1

T42

1

T12

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

13

1

T1

1

T4

1

T10

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

58

1

T7

8

T42

9

T40

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

20

1

T5

3

T95

1

T284

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

56

1

T10

1

T11

1

T12

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

8

1

T1

1

T10

1

T227

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

47

1

T2

1

T282

1

T261

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

21

1

T5

1

T52

2

T95

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

31

1

T11

2

T12

1

T118

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

16

1

T5

1

T52

1

T55

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

41

1

T2

2

T12

1

T32

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

31

1

T52

2

T342

9

T269

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

47

1

T2

1

T40

1

T117

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

13

1

T1

1

T10

1

T11

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

49

1

T2

2

T12

2

T39

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

40

1

T1

1

T5

1

T95

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

42

1

T12

1

T40

2

T32

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

44

1

T1

1

T10

1

T52

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

80

1

T2

2

T10

1

T41

9

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

61

1

T1

1

T5

1

T261

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

58

1

T7

2

T10

1

T11

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

20

1

T1

2

T10

1

T52

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

61

1

T7

4

T11

3

T39

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

23

1

T1

1

T11

3

T95

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

44

1

T11

2

T12

1

T39

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

21

1

T95

1

T34

1

T208

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

36

1

T12

1

T32

2

T282

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

22

1

T1

1

T34

2

T339

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

54

1

T10

2

T39

1

T32

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

20

1

T129

2

T145

1

T343

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

46

1

T2

1

T127

2

T130

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

42

1

T5

1

T52

1

T127

8

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

59

1

T39

2

T117

1

T55

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

30

1

T5

1

T95

1

T98

9

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

61

1

T55

1

T285

2

T130

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

61

1

T10

1

T227

2

T263

7

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

40

1

T2

1

T11

1

T118

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

20

1

T52

1

T95

1

T284

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

38

1

T2

1

T40

2

T282

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

19

1

T5

1

T10

1

T95

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

48

1

T1

1

T2

1

T10

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

28

1

T1

1

T4

1

T11

5

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

54

1

T10

1

T117

5

T267

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

39

1

T5

2

T267

9

T344

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

58

1

T5

1

T11

2

T39

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

24

1

T1

1

T339

1

T266

9

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

78

1

T2

1

T10

2

T12

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

61

1

T5

3

T10

1

T127

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

100

1

T10

1

T12

1

T39

6

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

58

1

T95

1

T55

1

T227

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

321

1

T2

4

T4

2

T10

12

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

12

1

T1

2

T284

1

T341

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

13

1

T4

1

T52

2

T284

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

8

1

T34

1

T340

1

T341

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

8

1

T10

1

T208

1

T227

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

7

1

T10

1

T284

1

T227

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

5

1

T284

1

T34

1

T208

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

4

1

T52

1

T344

1

T345

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

13

1

T4

1

T10

1

T268

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

8

1

T4

2

T52

1

T34

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

5

1

T4

1

T284

1

T273

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

5

1

T129

1

T340

1

T145

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

6

1

T284

1

T340

1

T344

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

8

1

T10

1

T52

1

T284

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

7

1

T1

1

T10

1

T208

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

9

1

T10

1

T344

1

T268

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

14

1

T4

1

T10

1

T52

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

4

1

T340

1

T346

1

T345

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

5

1

T208

1

T269

1

T347

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

5

1

T52

1

T95

1

T208

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

10

1

T1

1

T208

1

T344

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

6

1

T95

1

T284

1

T129

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

8

1

T10

1

T34

1

T341

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

18

1

T52

1

T284

1

T127

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

6

1

T284

1

T340

1

T348

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

10

1

T10

1

T340

1

T279

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

8

1

T208

1

T340

1

T349

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

5

1

T341

1

T349

1

T145

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

12

1

T4

1

T10

1

T11

4

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

14

1

T52

1

T284

1

T208

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

7

1

T284

1

T129

1

T208

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

7

1

T10

1

T261

1

T127

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

8

1

T284

1

T340

1

T268

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

110

1

T1

2

T4

8

T10

10

User Defined Cross Bins for cross_combo0

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo1

Samples crossed: cp_combo1_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	29	67	69.79	29
Automatically Generated Cross Bins	96	29	67	69.79	29
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo1

Element holes

cp_combo1_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	*	*	*	*	[auto[1]]	--	--	16
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_combo1_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_combo1_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

67

1

T2

1

T4

1

T10

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

29

1

T1

1

T5

1

T4

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

51

1

T2

1

T10

2

T11

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

18

1

T1

1

T5

1

T95

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

50

1

T11

1

T12

1

T117

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

16

1

T10

1

T208

1

T227

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

49

1

T285

1

T340

1

T260

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

32

1

T10

1

T284

1

T227

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

54

1

T2

1

T11

1

T41

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

29

1

T5

1

T4

1

T52

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

53

1

T7

1

T12

2

T39

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

22

1

T1

1

T5

1

T52

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

49

1

T2

1

T10

1

T42

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

26

1

T1

1

T4

2

T10

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

65

1

T2

1

T7

8

T42

9

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

28

1

T5

3

T4

2

T52

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

60

1

T10

1

T11

1

T12

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

13

1

T1

1

T4

1

T10

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

54

1

T2

1

T10

1

T282

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

26

1

T5

1

T52

2

T95

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

33

1

T10

1

T11

2

T12

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

22

1

T5

1

T52

1

T55

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

50

1

T2

3

T10

1

T12

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

39

1

T10

1

T52

3

T284

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

58

1

T2

1

T40

1

T117

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

20

1

T1

2

T10

2

T11

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

49

1

T2

2

T12

2

T39

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

49

1

T1

1

T5

1

T10

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

44

1

T12

1

T40

2

T32

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

58

1

T1

1

T4

1

T10

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

83

1

T2

2

T10

1

T41

9

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

65

1

T1

1

T5

1

T261

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

63

1

T7

2

T10

1

T11

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

25

1

T1

2

T10

1

T52

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

63

1

T7

2

T11

3

T39

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

27

1

T1

1

T11

3

T52

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

49

1

T10

1

T11

2

T12

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

31

1

T1

1

T95

1

T34

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

39

1

T12

1

T32

2

T282

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

28

1

T1

1

T95

1

T284

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

58

1

T10

2

T39

1

T32

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

28

1

T10

1

T129

2

T34

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

51

1

T2

1

T127

2

T130

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

60

1

T5

1

T52

2

T284

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

64

1

T10

1

T12

1

T39

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

36

1

T5

1

T95

1

T284

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

59

1

T32

1

T55

1

T285

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

71

1

T10

2

T227

2

T263

7

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

46

1

T2

1

T11

1

T118

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

27

1

T52

1

T95

1

T284

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

42

1

T2

1

T40

2

T282

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

24

1

T5

1

T10

1

T95

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

50

1

T1

1

T2

1

T10

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

40

1

T1

1

T4

2

T10

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

56

1

T10

1

T117

5

T285

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

53

1

T5

2

T52

1

T267

9

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

62

1

T5

1

T10

1

T11

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

31

1

T1

1

T284

1

T129

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

82

1

T2

1

T10

2

T12

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

68

1

T5

3

T10

2

T261

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

98

1

T10

1

T12

1

T39

6

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

66

1

T95

1

T55

1

T284

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

227

1

T2

1

T4

2

T10

9

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

101

1

T1

2

T4

5

T10

9

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

1

1

T350

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

1

1

T351

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

21

1

T1

2

T4

3

T10

1

User Defined Cross Bins for cross_combo1

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo2

Samples crossed: cp_combo2_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	28	68	70.83	28
Automatically Generated Cross Bins	96	28	68	70.83	28
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo2

Element holes

cp_combo2_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[1]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_combo2_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_combo2_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

67

1

T2

1

T4

1

T10

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

29

1

T1

1

T5

1

T4

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

51

1

T2

1

T10

2

T11

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

17

1

T1

1

T5

1

T95

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

50

1

T11

1

T12

1

T117

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

16

1

T10

1

T208

1

T227

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

43

1

T285

1

T340

1

T260

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

32

1

T10

1

T284

1

T227

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

54

1

T2

1

T11

1

T41

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

29

1

T5

1

T4

1

T52

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

53

1

T7

1

T12

2

T39

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

22

1

T1

1

T5

1

T52

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

46

1

T2

1

T10

1

T42

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

23

1

T1

1

T4

2

T10

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

62

1

T2

1

T7

8

T42

9

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

28

1

T5

3

T4

2

T52

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

60

1

T10

1

T11

1

T12

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

13

1

T1

1

T4

1

T10

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

54

1

T2

1

T10

1

T282

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

26

1

T5

1

T52

2

T95

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

33

1

T10

1

T11

2

T12

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

22

1

T5

1

T52

1

T55

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

47

1

T2

3

T10

1

T12

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

39

1

T10

1

T52

3

T284

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

57

1

T2

1

T40

1

T117

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

20

1

T1

2

T10

2

T11

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

53

1

T2

2

T12

2

T39

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

49

1

T1

1

T5

1

T10

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

48

1

T12

1

T40

2

T32

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

58

1

T1

1

T4

1

T10

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

75

1

T2

2

T10

1

T41

9

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

65

1

T1

1

T5

1

T261

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

63

1

T7

2

T10

1

T11

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

25

1

T1

2

T10

1

T52

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

58

1

T7

4

T11

3

T39

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

27

1

T1

1

T11

3

T52

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

52

1

T10

1

T11

2

T12

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

31

1

T1

1

T95

1

T34

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

40

1

T12

1

T32

2

T282

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

28

1

T1

1

T95

1

T284

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

57

1

T10

2

T39

1

T32

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

28

1

T10

1

T129

2

T34

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

51

1

T2

1

T127

2

T130

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

60

1

T5

1

T52

2

T284

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

64

1

T10

1

T12

1

T39

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

36

1

T5

1

T95

1

T284

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

62

1

T32

1

T55

1

T285

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

71

1

T10

2

T227

2

T263

7

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

47

1

T2

1

T11

1

T118

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

28

1

T52

1

T95

1

T284

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

41

1

T2

1

T40

2

T282

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

24

1

T5

1

T10

1

T95

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

51

1

T1

1

T2

1

T10

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

40

1

T1

1

T4

2

T10

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

50

1

T10

1

T117

5

T267

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

53

1

T5

2

T52

1

T267

9

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

65

1

T5

1

T10

1

T11

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

31

1

T1

1

T284

1

T129

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

79

1

T2

1

T10

2

T12

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

68

1

T5

3

T10

2

T261

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

101

1

T10

1

T12

1

T39

6

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

66

1

T95

1

T55

1

T284

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

199

1

T2

4

T10

1

T12

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

97

1

T1

4

T4

5

T10

9

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

1

1

T352

1

-

-

-

-

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

3

1

T353

3

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

1

1

T350

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

25

1

T4

3

T10

1

T284

2

User Defined Cross Bins for cross_combo2

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo3

Samples crossed: cp_combo3_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	28	68	70.83	28
Automatically Generated Cross Bins	96	28	68	70.83	28
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo3

Element holes

cp_combo3_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[0]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[0]]	[auto[1]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	*	[auto[0]]	[auto[1]]	--	--	2

Uncovered bins

cp_combo3_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1

Covered bins

cp_combo3_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

67

1

T2

1

T4

1

T10

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

29

1

T1

1

T5

1

T4

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

51

1

T2

1

T10

2

T11

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

18

1

T1

1

T5

1

T95

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

50

1

T11

1

T12

1

T117

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

16

1

T10

1

T208

1

T227

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

48

1

T285

1

T340

1

T260

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

31

1

T10

1

T284

1

T227

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

54

1

T2

1

T11

1

T41

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

29

1

T5

1

T4

1

T52

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

52

1

T7

1

T12

2

T39

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

22

1

T1

1

T5

1

T52

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

49

1

T2

1

T10

1

T42

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

26

1

T1

1

T4

2

T10

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

64

1

T2

1

T7

8

T42

9

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

28

1

T5

3

T4

2

T52

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

58

1

T10

1

T11

1

T12

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

13

1

T1

1

T4

1

T10

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

54

1

T2

1

T10

1

T282

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

26

1

T5

1

T52

2

T95

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

33

1

T10

1

T11

2

T12

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

22

1

T5

1

T52

1

T55

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

50

1

T2

3

T10

1

T12

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

39

1

T10

1

T52

3

T284

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

57

1

T2

1

T40

1

T117

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

20

1

T1

2

T10

2

T11

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

53

1

T2

2

T12

2

T39

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

49

1

T1

1

T5

1

T10

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

47

1

T12

1

T40

2

T32

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

58

1

T1

1

T4

1

T10

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

83

1

T2

2

T10

1

T41

9

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

65

1

T1

1

T5

1

T261

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

63

1

T7

2

T10

1

T11

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

24

1

T1

2

T10

1

T52

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

65

1

T7

4

T11

3

T39

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

28

1

T1

1

T11

3

T52

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

52

1

T10

1

T11

2

T12

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

31

1

T1

1

T95

1

T34

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

42

1

T12

1

T32

2

T282

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

28

1

T1

1

T95

1

T284

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

55

1

T10

2

T39

1

T32

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

28

1

T10

1

T129

2

T34

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

49

1

T2

1

T127

2

T130

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

60

1

T5

1

T52

2

T284

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

62

1

T10

1

T12

1

T39

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

36

1

T5

1

T95

1

T284

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

67

1

T32

1

T55

1

T285

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

71

1

T10

2

T227

2

T263

7

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

47

1

T2

1

T11

1

T118

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

28

1

T52

1

T95

1

T284

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

41

1

T2

1

T40

1

T282

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

24

1

T5

1

T10

1

T95

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

51

1

T1

1

T2

1

T10

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

40

1

T1

1

T4

2

T10

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

54

1

T10

1

T117

5

T267

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

53

1

T5

2

T52

1

T267

9

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

60

1

T5

1

T10

1

T11

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

31

1

T1

1

T284

1

T129

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

80

1

T2

1

T10

2

T12

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

66

1

T5

3

T10

2

T261

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

102

1

T10

1

T12

1

T39

6

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

66

1

T95

1

T55

1

T284

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

197

1

T2

4

T4

2

T10

11

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

99

1

T1

3

T4

6

T10

10

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1

1

T354

1

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

1

1

T347

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

2

1

T127

2

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

23

1

T1

1

T4

2

T52

2

User Defined Cross Bins for cross_combo3

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded