Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.10 99.44 96.81 100.00 98.08 98.93 99.71 93.70


Total tests in report: 915
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
60.87 60.87 78.11 78.11 67.80 67.80 93.84 93.84 13.46 13.46 79.41 79.41 67.73 67.73 25.78 25.78 /workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.3158762517
73.65 12.78 86.58 8.47 77.17 9.38 94.98 1.14 50.00 36.54 87.39 7.99 82.56 14.84 36.87 11.09 /workspace/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.74040015
81.00 7.35 93.41 6.83 86.22 9.05 96.80 1.83 60.26 10.26 92.87 5.47 91.14 8.57 46.29 9.42 /workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.549341260
83.85 2.85 94.96 1.55 87.89 1.67 97.26 0.46 70.51 10.26 94.31 1.44 94.32 3.18 47.69 1.40 /workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.2280406560
86.55 2.70 95.17 0.21 88.20 0.30 97.26 0.00 73.08 2.56 94.60 0.30 94.99 0.67 62.54 14.85 /workspace/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.460409416
88.67 2.12 96.25 1.08 89.84 1.64 97.26 0.00 83.97 10.90 95.75 1.15 95.09 0.10 62.54 0.00 /workspace/coverage/default/0.sysrst_ctrl_feature_disable.3738733993
90.38 1.71 97.82 1.57 92.24 2.40 97.49 0.23 83.97 0.00 97.26 1.52 95.66 0.58 68.19 5.65 /workspace/coverage/default/4.sysrst_ctrl_stress_all.4188006141
91.69 1.31 97.84 0.02 93.30 1.06 98.17 0.68 83.97 0.00 97.30 0.04 95.76 0.10 75.46 7.27 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.1873741604
92.62 0.94 98.19 0.35 93.58 0.28 98.17 0.00 87.18 3.21 97.60 0.30 97.01 1.25 76.64 1.18 /workspace/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.4214110890
93.39 0.77 98.28 0.09 93.58 0.00 98.17 0.00 89.10 1.92 97.71 0.11 97.01 0.00 79.87 3.23 /workspace/coverage/default/26.sysrst_ctrl_combo_detect.1192750299
93.93 0.54 98.53 0.24 93.68 0.10 98.17 0.00 91.67 2.56 97.86 0.15 97.69 0.67 79.92 0.05 /workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.3627476568
94.34 0.41 98.56 0.04 93.71 0.03 98.17 0.00 92.31 0.64 97.89 0.04 97.78 0.10 81.97 2.05 /workspace/coverage/default/34.sysrst_ctrl_combo_detect.590009697
94.63 0.28 98.56 0.00 93.73 0.03 99.77 1.60 92.31 0.00 97.89 0.00 97.88 0.10 82.24 0.27 /workspace/coverage/default/2.sysrst_ctrl_sec_cm.1601342235
94.90 0.27 98.62 0.06 93.76 0.03 99.77 0.00 92.31 0.00 97.89 0.00 97.88 0.00 84.07 1.83 /workspace/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.3167052995
95.17 0.27 98.69 0.07 93.81 0.05 99.77 0.00 93.59 1.28 97.97 0.07 98.07 0.19 84.28 0.22 /workspace/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.2827833807
95.43 0.26 98.71 0.02 93.83 0.03 99.77 0.00 93.59 0.00 98.00 0.04 98.17 0.10 85.90 1.61 /workspace/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.1445454542
95.68 0.25 98.81 0.09 93.88 0.05 99.77 0.00 94.87 1.28 98.11 0.11 98.36 0.19 85.95 0.05 /workspace/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.4290288785
95.92 0.24 98.88 0.07 93.93 0.05 99.77 0.00 96.15 1.28 98.19 0.07 98.55 0.19 85.95 0.00 /workspace/coverage/default/2.sysrst_ctrl_edge_detect.2896291179
96.11 0.19 98.97 0.09 94.24 0.30 99.77 0.00 96.15 0.00 98.34 0.15 99.33 0.77 85.95 0.00 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.207403055
96.28 0.18 98.99 0.02 94.24 0.00 99.77 0.00 96.15 0.00 98.37 0.04 99.33 0.00 87.14 1.18 /workspace/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.2170519506
96.46 0.18 99.01 0.02 94.51 0.28 99.77 0.00 96.15 0.00 98.45 0.07 99.33 0.00 88.00 0.86 /workspace/coverage/default/25.sysrst_ctrl_stress_all.630026977
96.63 0.17 99.01 0.00 95.50 0.99 99.77 0.00 96.15 0.00 98.45 0.00 99.33 0.00 88.21 0.22 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.2581398418
96.79 0.15 99.01 0.00 95.50 0.00 99.77 0.00 96.15 0.00 98.45 0.00 99.33 0.00 89.29 1.08 /workspace/coverage/default/10.sysrst_ctrl_stress_all.2893230567
96.92 0.13 99.05 0.04 95.53 0.03 99.77 0.00 96.79 0.64 98.48 0.04 99.42 0.10 89.40 0.11 /workspace/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.290250844
97.04 0.12 99.09 0.04 95.55 0.03 99.77 0.00 97.44 0.64 98.52 0.04 99.52 0.10 89.40 0.00 /workspace/coverage/default/10.sysrst_ctrl_edge_detect.1788343417
97.16 0.12 99.12 0.04 95.58 0.03 99.77 0.00 98.08 0.64 98.56 0.04 99.61 0.10 89.40 0.00 /workspace/coverage/default/15.sysrst_ctrl_edge_detect.3687557354
97.26 0.10 99.18 0.06 95.60 0.03 99.77 0.00 98.08 0.00 98.56 0.00 99.61 0.00 90.04 0.65 /workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.3828478286
97.34 0.07 99.18 0.00 95.63 0.03 99.77 0.00 98.08 0.00 98.56 0.00 99.61 0.00 90.53 0.48 /workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.689526031
97.41 0.07 99.23 0.06 96.01 0.38 99.77 0.00 98.08 0.00 98.63 0.07 99.61 0.00 90.53 0.00 /workspace/coverage/default/1.sysrst_ctrl_feature_disable.3135870688
97.47 0.06 99.23 0.00 96.01 0.00 99.77 0.00 98.08 0.00 98.63 0.00 99.61 0.00 90.96 0.43 /workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.2168635825
97.52 0.05 99.29 0.06 96.08 0.08 100.00 0.23 98.08 0.00 98.63 0.00 99.61 0.00 90.96 0.00 /workspace/coverage/default/14.sysrst_ctrl_alert_test.1825012181
97.57 0.05 99.29 0.00 96.39 0.30 100.00 0.00 98.08 0.00 98.63 0.00 99.61 0.00 91.01 0.05 /workspace/coverage/default/12.sysrst_ctrl_ultra_low_pwr.613316466
97.62 0.05 99.29 0.00 96.39 0.00 100.00 0.00 98.08 0.00 98.63 0.00 99.61 0.00 91.33 0.32 /workspace/coverage/default/19.sysrst_ctrl_combo_detect.422516085
97.66 0.04 99.29 0.00 96.44 0.05 100.00 0.00 98.08 0.00 98.63 0.00 99.61 0.00 91.55 0.22 /workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.2168474973
97.69 0.04 99.29 0.00 96.49 0.05 100.00 0.00 98.08 0.00 98.67 0.04 99.61 0.00 91.71 0.16 /workspace/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.688267141
97.72 0.03 99.29 0.00 96.49 0.00 100.00 0.00 98.08 0.00 98.67 0.00 99.61 0.00 91.93 0.22 /workspace/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.2788272004
97.75 0.03 99.29 0.00 96.49 0.00 100.00 0.00 98.08 0.00 98.67 0.00 99.61 0.00 92.14 0.22 /workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.3897538209
97.78 0.03 99.31 0.02 96.54 0.05 100.00 0.00 98.08 0.00 98.71 0.04 99.71 0.10 92.14 0.00 /workspace/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.1708003679
97.81 0.02 99.31 0.00 96.54 0.00 100.00 0.00 98.08 0.00 98.71 0.00 99.71 0.00 92.30 0.16 /workspace/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.1693586469
97.83 0.02 99.31 0.00 96.54 0.00 100.00 0.00 98.08 0.00 98.71 0.00 99.71 0.00 92.47 0.16 /workspace/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.1564720906
97.85 0.02 99.31 0.00 96.69 0.15 100.00 0.00 98.08 0.00 98.71 0.00 99.71 0.00 92.47 0.00 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.2852438499
97.87 0.02 99.31 0.00 96.69 0.00 100.00 0.00 98.08 0.00 98.71 0.00 99.71 0.00 92.57 0.11 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.2933827422
97.88 0.02 99.31 0.00 96.69 0.00 100.00 0.00 98.08 0.00 98.71 0.00 99.71 0.00 92.68 0.11 /workspace/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.1957030363
97.90 0.02 99.31 0.00 96.69 0.00 100.00 0.00 98.08 0.00 98.71 0.00 99.71 0.00 92.79 0.11 /workspace/coverage/default/12.sysrst_ctrl_stress_all.897039964
97.91 0.02 99.31 0.00 96.69 0.00 100.00 0.00 98.08 0.00 98.71 0.00 99.71 0.00 92.90 0.11 /workspace/coverage/default/15.sysrst_ctrl_pin_override_test.1276530656
97.93 0.02 99.31 0.00 96.69 0.00 100.00 0.00 98.08 0.00 98.71 0.00 99.71 0.00 93.00 0.11 /workspace/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.3084322602
97.94 0.02 99.31 0.00 96.69 0.00 100.00 0.00 98.08 0.00 98.71 0.00 99.71 0.00 93.11 0.11 /workspace/coverage/default/33.sysrst_ctrl_combo_detect.1059414990
97.96 0.02 99.31 0.00 96.69 0.00 100.00 0.00 98.08 0.00 98.71 0.00 99.71 0.00 93.22 0.11 /workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.2978118649
97.97 0.01 99.33 0.02 96.69 0.00 100.00 0.00 98.08 0.00 98.74 0.04 99.71 0.00 93.22 0.00 /workspace/coverage/default/13.sysrst_ctrl_edge_detect.4160789173
97.97 0.01 99.35 0.02 96.69 0.00 100.00 0.00 98.08 0.00 98.78 0.04 99.71 0.00 93.22 0.00 /workspace/coverage/default/27.sysrst_ctrl_stress_all.2097227054
97.98 0.01 99.37 0.02 96.69 0.00 100.00 0.00 98.08 0.00 98.82 0.04 99.71 0.00 93.22 0.00 /workspace/coverage/default/29.sysrst_ctrl_edge_detect.751460053
97.99 0.01 99.38 0.02 96.69 0.00 100.00 0.00 98.08 0.00 98.85 0.04 99.71 0.00 93.22 0.00 /workspace/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.3716925203
98.00 0.01 99.40 0.02 96.69 0.00 100.00 0.00 98.08 0.00 98.89 0.04 99.71 0.00 93.22 0.00 /workspace/coverage/default/40.sysrst_ctrl_edge_detect.3770944018
98.01 0.01 99.42 0.02 96.69 0.00 100.00 0.00 98.08 0.00 98.93 0.04 99.71 0.00 93.22 0.00 /workspace/coverage/default/9.sysrst_ctrl_edge_detect.3064510994
98.01 0.01 99.42 0.00 96.69 0.00 100.00 0.00 98.08 0.00 98.93 0.00 99.71 0.00 93.27 0.05 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.236717243
98.02 0.01 99.42 0.00 96.69 0.00 100.00 0.00 98.08 0.00 98.93 0.00 99.71 0.00 93.33 0.05 /workspace/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.445144655
98.03 0.01 99.42 0.00 96.69 0.00 100.00 0.00 98.08 0.00 98.93 0.00 99.71 0.00 93.38 0.05 /workspace/coverage/default/23.sysrst_ctrl_combo_detect.2142254144
98.04 0.01 99.42 0.00 96.69 0.00 100.00 0.00 98.08 0.00 98.93 0.00 99.71 0.00 93.43 0.05 /workspace/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.3900833802
98.04 0.01 99.42 0.00 96.69 0.00 100.00 0.00 98.08 0.00 98.93 0.00 99.71 0.00 93.49 0.05 /workspace/coverage/default/27.sysrst_ctrl_combo_detect.3670053730
98.05 0.01 99.42 0.00 96.69 0.00 100.00 0.00 98.08 0.00 98.93 0.00 99.71 0.00 93.54 0.05 /workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.1109797949
98.06 0.01 99.42 0.00 96.69 0.00 100.00 0.00 98.08 0.00 98.93 0.00 99.71 0.00 93.60 0.05 /workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.2833273720
98.07 0.01 99.42 0.00 96.69 0.00 100.00 0.00 98.08 0.00 98.93 0.00 99.71 0.00 93.65 0.05 /workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.3263560554
98.08 0.01 99.42 0.00 96.69 0.00 100.00 0.00 98.08 0.00 98.93 0.00 99.71 0.00 93.70 0.05 /workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.1620190037
98.08 0.01 99.42 0.00 96.74 0.05 100.00 0.00 98.08 0.00 98.93 0.00 99.71 0.00 93.70 0.00 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.819265096
98.09 0.01 99.42 0.00 96.76 0.03 100.00 0.00 98.08 0.00 98.93 0.00 99.71 0.00 93.70 0.00 /workspace/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.1338054743
98.09 0.01 99.42 0.00 96.79 0.03 100.00 0.00 98.08 0.00 98.93 0.00 99.71 0.00 93.70 0.00 /workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.3507602829
98.09 0.01 99.44 0.02 96.79 0.00 100.00 0.00 98.08 0.00 98.93 0.00 99.71 0.00 93.70 0.00 /workspace/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.3961181901

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.834898253
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.496713105
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.926315879
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.1566997715
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.1766661977
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.4190360307
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.3219034397
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.563704233
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.2936000102
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.1908602971
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.3703687121
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.2048772823
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.4085865765
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.238388228
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.3776732682
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.2143730393
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.64132522
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.3454548533
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.4018959156
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.2560625473
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.2640908377
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.1647543589
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.4261646885
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.3318506172
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.3122355664
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.1683524379
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.2533829399
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.3388332921
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.2811556367
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.2178355649
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.3550933428
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.933384127
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.3790429038
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.1197406555
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.2774575967
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.1047271052
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.1645157078
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.3049098250
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.3161532337
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.109717087
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.3847898387
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.4243156672
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.3064148518
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.3158612393
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.3810460383
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.528699904
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.3080281658
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.4120822999
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.1919251784
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.79968939
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.4210383891
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.4287689984
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.3056798483
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.1630940758
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.1476161327
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.3259619356
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.837897380
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.324579958
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.1455197176
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.308908327
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.1316450810
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.482329774
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.3682364210
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.2938470499
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.3474655633
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.2715473257
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.3589017074
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.2057260244
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.2249525554
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.1737829200
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.1258141441
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.897189969
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.2917565865
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.3564753711
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.880409433
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.1523940528
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.4108819138
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.1783301895
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.1195228336
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.2172737602
/workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.625259307
/workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.1007554404
/workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.3742354409
/workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.3871251365
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/workspace/coverage/default/42.sysrst_ctrl_combo_detect.355941009
/workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.370397271
/workspace/coverage/default/42.sysrst_ctrl_edge_detect.1126162399
/workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.174981190
/workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.3247732995
/workspace/coverage/default/42.sysrst_ctrl_pin_access_test.893134091
/workspace/coverage/default/42.sysrst_ctrl_pin_override_test.498085659
/workspace/coverage/default/42.sysrst_ctrl_smoke.839867078
/workspace/coverage/default/42.sysrst_ctrl_stress_all.3045313110
/workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.1613323448
/workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.4164731636
/workspace/coverage/default/43.sysrst_ctrl_alert_test.885399693
/workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.3041653392
/workspace/coverage/default/43.sysrst_ctrl_combo_detect.4141503702
/workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.2082513337
/workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.3082209095
/workspace/coverage/default/43.sysrst_ctrl_edge_detect.271141263
/workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.4154169954
/workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.3713497266
/workspace/coverage/default/43.sysrst_ctrl_pin_access_test.1082780556
/workspace/coverage/default/43.sysrst_ctrl_pin_override_test.1733182950
/workspace/coverage/default/43.sysrst_ctrl_smoke.923526124
/workspace/coverage/default/43.sysrst_ctrl_stress_all.2770805988
/workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.1641302356
/workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.3082466763
/workspace/coverage/default/44.sysrst_ctrl_alert_test.3211303113
/workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.3886083206
/workspace/coverage/default/44.sysrst_ctrl_combo_detect.1188263243
/workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.4040670674
/workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.114911853
/workspace/coverage/default/44.sysrst_ctrl_edge_detect.127061254
/workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.2956088886
/workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.3550534356
/workspace/coverage/default/44.sysrst_ctrl_pin_access_test.2055538757
/workspace/coverage/default/44.sysrst_ctrl_pin_override_test.266075551
/workspace/coverage/default/44.sysrst_ctrl_smoke.1609522545
/workspace/coverage/default/44.sysrst_ctrl_stress_all.435186098
/workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.3547143233
/workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.1672350081
/workspace/coverage/default/45.sysrst_ctrl_alert_test.2666764905
/workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.2370208957
/workspace/coverage/default/45.sysrst_ctrl_combo_detect.1811152281
/workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.3705811662
/workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.3693480475
/workspace/coverage/default/45.sysrst_ctrl_edge_detect.2088182826
/workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.2120928444
/workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.3705020872
/workspace/coverage/default/45.sysrst_ctrl_pin_access_test.1402088923
/workspace/coverage/default/45.sysrst_ctrl_pin_override_test.2123453775
/workspace/coverage/default/45.sysrst_ctrl_smoke.1367990560
/workspace/coverage/default/45.sysrst_ctrl_stress_all.82033628
/workspace/coverage/default/46.sysrst_ctrl_alert_test.2789143651
/workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.554811408
/workspace/coverage/default/46.sysrst_ctrl_combo_detect.3961324549
/workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.1138934697
/workspace/coverage/default/46.sysrst_ctrl_edge_detect.909752369
/workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.2013872968
/workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.1565000484
/workspace/coverage/default/46.sysrst_ctrl_pin_access_test.3535215229
/workspace/coverage/default/46.sysrst_ctrl_pin_override_test.2587596409
/workspace/coverage/default/46.sysrst_ctrl_smoke.2770048393
/workspace/coverage/default/46.sysrst_ctrl_stress_all.1387652512
/workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.1058165503
/workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.2763796448
/workspace/coverage/default/47.sysrst_ctrl_alert_test.1182979403
/workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.2248255937
/workspace/coverage/default/47.sysrst_ctrl_combo_detect.451715115
/workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.2669504051
/workspace/coverage/default/47.sysrst_ctrl_edge_detect.2639883140
/workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.1467340101
/workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.1088265232
/workspace/coverage/default/47.sysrst_ctrl_pin_access_test.2907660386
/workspace/coverage/default/47.sysrst_ctrl_pin_override_test.2285678097
/workspace/coverage/default/47.sysrst_ctrl_smoke.1796880428
/workspace/coverage/default/47.sysrst_ctrl_stress_all.1297118150
/workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.77113111
/workspace/coverage/default/48.sysrst_ctrl_alert_test.2497893312
/workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.792709985
/workspace/coverage/default/48.sysrst_ctrl_combo_detect.2003516614
/workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.1595508766
/workspace/coverage/default/48.sysrst_ctrl_edge_detect.2089828159
/workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.854671372
/workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.3094118651
/workspace/coverage/default/48.sysrst_ctrl_pin_access_test.3156629846
/workspace/coverage/default/48.sysrst_ctrl_pin_override_test.3450116531
/workspace/coverage/default/48.sysrst_ctrl_smoke.1881277848
/workspace/coverage/default/48.sysrst_ctrl_stress_all.3966310509
/workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.4006460050
/workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.838556526
/workspace/coverage/default/49.sysrst_ctrl_alert_test.608285314
/workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.1036719516
/workspace/coverage/default/49.sysrst_ctrl_combo_detect.76514369
/workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.1327032440
/workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.1979378195
/workspace/coverage/default/49.sysrst_ctrl_edge_detect.2771868493
/workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.1226929543
/workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.2829268361
/workspace/coverage/default/49.sysrst_ctrl_pin_access_test.1005609039
/workspace/coverage/default/49.sysrst_ctrl_pin_override_test.3349964038
/workspace/coverage/default/49.sysrst_ctrl_smoke.2876199888
/workspace/coverage/default/49.sysrst_ctrl_stress_all.2424746599
/workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.4054379327
/workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.3348463238
/workspace/coverage/default/5.sysrst_ctrl_alert_test.4293346956
/workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.4101793364
/workspace/coverage/default/5.sysrst_ctrl_combo_detect.121732332
/workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.1522867539
/workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.376945301
/workspace/coverage/default/5.sysrst_ctrl_edge_detect.1681150172
/workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.3393272580
/workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.1753572221
/workspace/coverage/default/5.sysrst_ctrl_pin_access_test.4190710143
/workspace/coverage/default/5.sysrst_ctrl_pin_override_test.503506066
/workspace/coverage/default/5.sysrst_ctrl_smoke.1099140089
/workspace/coverage/default/5.sysrst_ctrl_stress_all.1912806716
/workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.280006554
/workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.3384018937
/workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.3009049368
/workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.217957681
/workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.554528357
/workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.3845483769
/workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.3527053845
/workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.4038904074
/workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.989576661
/workspace/coverage/default/6.sysrst_ctrl_alert_test.823677400
/workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.1497064941
/workspace/coverage/default/6.sysrst_ctrl_combo_detect.3834047548
/workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.317904487
/workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.1261653759
/workspace/coverage/default/6.sysrst_ctrl_edge_detect.3585727057
/workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.4118810616
/workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.990958101
/workspace/coverage/default/6.sysrst_ctrl_pin_access_test.3852883299
/workspace/coverage/default/6.sysrst_ctrl_pin_override_test.1825239868
/workspace/coverage/default/6.sysrst_ctrl_smoke.3373287012
/workspace/coverage/default/6.sysrst_ctrl_stress_all.909611157
/workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.551644990
/workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.3453402590
/workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.1088024452
/workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.2896293647
/workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.4176593738
/workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.3747985906
/workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.1025731231
/workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.2141073948
/workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.930724524
/workspace/coverage/default/7.sysrst_ctrl_alert_test.1865979904
/workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.4063709994
/workspace/coverage/default/7.sysrst_ctrl_combo_detect.1507822873
/workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.3261056993
/workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.1647465038
/workspace/coverage/default/7.sysrst_ctrl_edge_detect.391912389
/workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.1986850900
/workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.4079458741
/workspace/coverage/default/7.sysrst_ctrl_pin_access_test.1363748457
/workspace/coverage/default/7.sysrst_ctrl_pin_override_test.563770404
/workspace/coverage/default/7.sysrst_ctrl_smoke.641108875
/workspace/coverage/default/7.sysrst_ctrl_stress_all.3097857925
/workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.3136720035
/workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.568311859
/workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.3216151243
/workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.3579899040
/workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.3741333228
/workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.1887820382
/workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.3723654815
/workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.1915028611
/workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.1808840577
/workspace/coverage/default/8.sysrst_ctrl_alert_test.2905160270
/workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.792134084
/workspace/coverage/default/8.sysrst_ctrl_combo_detect.1458409346
/workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.3888965820
/workspace/coverage/default/8.sysrst_ctrl_edge_detect.2369575461
/workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.43413535
/workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.1560421242
/workspace/coverage/default/8.sysrst_ctrl_pin_access_test.665063920
/workspace/coverage/default/8.sysrst_ctrl_pin_override_test.1802490250
/workspace/coverage/default/8.sysrst_ctrl_smoke.3485341550
/workspace/coverage/default/8.sysrst_ctrl_stress_all.779890617
/workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.2393479917
/workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.3413205276
/workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.3755346444
/workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.1873996786
/workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.4286870908
/workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.1283561188
/workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.2326207795
/workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.465211422
/workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.3182697571
/workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.3686084859
/workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.1859844031
/workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.3765754477
/workspace/coverage/default/9.sysrst_ctrl_alert_test.222071523
/workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.2565289298
/workspace/coverage/default/9.sysrst_ctrl_combo_detect.3330467186
/workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.3123240541
/workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.1483107974
/workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.565310642
/workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.1946785623
/workspace/coverage/default/9.sysrst_ctrl_pin_access_test.2875401755
/workspace/coverage/default/9.sysrst_ctrl_pin_override_test.2257633974
/workspace/coverage/default/9.sysrst_ctrl_smoke.2889440009
/workspace/coverage/default/9.sysrst_ctrl_stress_all.859999873
/workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.2238130928
/workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.907971779
/workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.3522463893
/workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.479792123
/workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.2055823276
/workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.488493568
/workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.3966897319
/workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.1507008069



Total test records in report: 915
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/1.sysrst_ctrl_combo_detect.2052977776 Mar 26 02:41:20 PM PDT 24 Mar 26 02:42:07 PM PDT 24 131803681849 ps
T5 /workspace/coverage/default/11.sysrst_ctrl_combo_detect.2600261329 Mar 26 02:41:50 PM PDT 24 Mar 26 02:42:19 PM PDT 24 42470876114 ps
T6 /workspace/coverage/default/16.sysrst_ctrl_smoke.3492031436 Mar 26 02:42:01 PM PDT 24 Mar 26 02:42:06 PM PDT 24 2111718127 ps
T2 /workspace/coverage/default/33.sysrst_ctrl_combo_detect.1059414990 Mar 26 02:42:38 PM PDT 24 Mar 26 02:43:26 PM PDT 24 68725783350 ps
T13 /workspace/coverage/default/36.sysrst_ctrl_pin_override_test.4198116822 Mar 26 02:42:49 PM PDT 24 Mar 26 02:42:51 PM PDT 24 2535973867 ps
T3 /workspace/coverage/default/12.sysrst_ctrl_ultra_low_pwr.613316466 Mar 26 02:41:53 PM PDT 24 Mar 26 02:42:03 PM PDT 24 10286674781 ps
T4 /workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.3158762517 Mar 26 02:41:34 PM PDT 24 Mar 26 02:44:15 PM PDT 24 123611907744 ps
T14 /workspace/coverage/default/41.sysrst_ctrl_pin_override_test.3122744159 Mar 26 02:43:05 PM PDT 24 Mar 26 02:43:07 PM PDT 24 2537013164 ps
T15 /workspace/coverage/default/37.sysrst_ctrl_pin_override_test.476591949 Mar 26 02:42:50 PM PDT 24 Mar 26 02:42:58 PM PDT 24 2510025144 ps
T7 /workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.2896293647 Mar 26 02:43:47 PM PDT 24 Mar 26 02:46:58 PM PDT 24 75703326351 ps
T27 /workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.3627476568 Mar 26 02:43:43 PM PDT 24 Mar 26 02:44:58 PM PDT 24 27579940668 ps
T47 /workspace/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.287672830 Mar 26 02:42:37 PM PDT 24 Mar 26 02:42:42 PM PDT 24 2613250111 ps
T25 /workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.2565289298 Mar 26 02:41:43 PM PDT 24 Mar 26 02:41:46 PM PDT 24 3433151690 ps
T48 /workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.3082209095 Mar 26 02:43:11 PM PDT 24 Mar 26 02:43:16 PM PDT 24 3804703030 ps
T26 /workspace/coverage/default/30.sysrst_ctrl_auto_blk_key_output.338489102 Mar 26 02:42:39 PM PDT 24 Mar 26 02:42:41 PM PDT 24 3093113537 ps
T8 /workspace/coverage/default/43.sysrst_ctrl_edge_detect.271141263 Mar 26 02:43:10 PM PDT 24 Mar 26 02:43:25 PM PDT 24 5216683094 ps
T43 /workspace/coverage/default/16.sysrst_ctrl_auto_blk_key_output.3394589476 Mar 26 02:41:51 PM PDT 24 Mar 26 02:41:56 PM PDT 24 3222753945 ps
T21 /workspace/coverage/default/0.sysrst_ctrl_in_out_inverted.2492692660 Mar 26 02:41:15 PM PDT 24 Mar 26 02:41:19 PM PDT 24 2463301303 ps
T9 /workspace/coverage/default/6.sysrst_ctrl_edge_detect.3585727057 Mar 26 02:41:31 PM PDT 24 Mar 26 02:41:43 PM PDT 24 4667839280 ps
T22 /workspace/coverage/default/39.sysrst_ctrl_in_out_inverted.3896896258 Mar 26 02:42:57 PM PDT 24 Mar 26 02:42:59 PM PDT 24 2476512101 ps
T49 /workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.3947461687 Mar 26 02:43:05 PM PDT 24 Mar 26 02:43:15 PM PDT 24 3760703552 ps
T65 /workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.174981190 Mar 26 02:43:07 PM PDT 24 Mar 26 02:43:14 PM PDT 24 2611925215 ps
T66 /workspace/coverage/default/14.sysrst_ctrl_pin_access_test.2397927632 Mar 26 02:41:45 PM PDT 24 Mar 26 02:41:48 PM PDT 24 2149820542 ps
T67 /workspace/coverage/default/46.sysrst_ctrl_smoke.2770048393 Mar 26 02:43:22 PM PDT 24 Mar 26 02:43:24 PM PDT 24 2132481482 ps
T10 /workspace/coverage/default/25.sysrst_ctrl_stress_all.630026977 Mar 26 02:42:23 PM PDT 24 Mar 26 02:47:51 PM PDT 24 238346523104 ps
T11 /workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.549341260 Mar 26 02:43:57 PM PDT 24 Mar 26 02:45:50 PM PDT 24 165457451685 ps
T68 /workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.565310642 Mar 26 02:41:43 PM PDT 24 Mar 26 02:41:46 PM PDT 24 2630573336 ps
T69 /workspace/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.2438577982 Mar 26 02:42:28 PM PDT 24 Mar 26 02:42:30 PM PDT 24 2645626031 ps
T42 /workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.1088024452 Mar 26 02:43:56 PM PDT 24 Mar 26 02:44:20 PM PDT 24 34061011801 ps
T119 /workspace/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.3023439530 Mar 26 02:41:49 PM PDT 24 Mar 26 02:42:00 PM PDT 24 3794268078 ps
T264 /workspace/coverage/default/23.sysrst_ctrl_alert_test.1856991274 Mar 26 02:42:24 PM PDT 24 Mar 26 02:42:27 PM PDT 24 2030463540 ps
T12 /workspace/coverage/default/39.sysrst_ctrl_combo_detect.2628803357 Mar 26 02:42:58 PM PDT 24 Mar 26 02:49:03 PM PDT 24 141074661604 ps
T70 /workspace/coverage/default/24.sysrst_ctrl_pin_override_test.3414315567 Mar 26 02:42:25 PM PDT 24 Mar 26 02:42:27 PM PDT 24 2526652411 ps
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T31 /workspace/coverage/default/21.sysrst_ctrl_ultra_low_pwr.287776793 Mar 26 02:42:07 PM PDT 24 Mar 26 02:42:09 PM PDT 24 3880027731 ps
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T23 /workspace/coverage/default/19.sysrst_ctrl_in_out_inverted.3801894465 Mar 26 02:42:08 PM PDT 24 Mar 26 02:42:13 PM PDT 24 2461814256 ps
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T19 /workspace/coverage/default/33.sysrst_ctrl_ultra_low_pwr.1261236703 Mar 26 02:42:42 PM PDT 24 Mar 26 02:42:47 PM PDT 24 8381227509 ps
T202 /workspace/coverage/default/21.sysrst_ctrl_alert_test.3874697586 Mar 26 02:42:09 PM PDT 24 Mar 26 02:42:11 PM PDT 24 2025562073 ps
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T315 /workspace/coverage/default/10.sysrst_ctrl_pin_override_test.294293396 Mar 26 02:41:44 PM PDT 24 Mar 26 02:41:52 PM PDT 24 2511008035 ps
T37 /workspace/coverage/default/8.sysrst_ctrl_edge_detect.2369575461 Mar 26 02:41:43 PM PDT 24 Mar 26 02:41:49 PM PDT 24 4649684348 ps
T316 /workspace/coverage/default/28.sysrst_ctrl_pin_override_test.4049316694 Mar 26 02:42:29 PM PDT 24 Mar 26 02:42:37 PM PDT 24 2514186677 ps
T58 /workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.3550534356 Mar 26 02:43:09 PM PDT 24 Mar 26 02:43:16 PM PDT 24 2458252691 ps
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T39 /workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.1808840577 Mar 26 02:43:56 PM PDT 24 Mar 26 02:51:50 PM PDT 24 170015061106 ps
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T73 /workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.3522463893 Mar 26 02:43:56 PM PDT 24 Mar 26 02:45:07 PM PDT 24 25833388275 ps
T40 /workspace/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.3167052995 Mar 26 02:42:08 PM PDT 24 Mar 26 02:43:46 PM PDT 24 64049479696 ps
T195 /workspace/coverage/default/31.sysrst_ctrl_pin_access_test.1048164072 Mar 26 02:42:33 PM PDT 24 Mar 26 02:42:36 PM PDT 24 2153234755 ps
T33 /workspace/coverage/default/48.sysrst_ctrl_edge_detect.2089828159 Mar 26 02:43:36 PM PDT 24 Mar 26 02:43:39 PM PDT 24 5518668949 ps
T196 /workspace/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.356999106 Mar 26 02:42:17 PM PDT 24 Mar 26 02:42:24 PM PDT 24 5238542906 ps
T197 /workspace/coverage/default/16.sysrst_ctrl_pin_override_test.423277204 Mar 26 02:41:49 PM PDT 24 Mar 26 02:41:57 PM PDT 24 2512685995 ps
T198 /workspace/coverage/default/39.sysrst_ctrl_alert_test.1702248626 Mar 26 02:42:56 PM PDT 24 Mar 26 02:43:02 PM PDT 24 2014384470 ps
T38 /workspace/coverage/default/16.sysrst_ctrl_edge_detect.2167043529 Mar 26 02:41:58 PM PDT 24 Mar 26 02:42:02 PM PDT 24 2948443601 ps
T199 /workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.2956088886 Mar 26 02:43:23 PM PDT 24 Mar 26 02:43:27 PM PDT 24 2610978502 ps
T248 /workspace/coverage/default/15.sysrst_ctrl_pin_override_test.1276530656 Mar 26 02:41:54 PM PDT 24 Mar 26 02:41:58 PM PDT 24 2515286432 ps
T249 /workspace/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.60435253 Mar 26 02:41:44 PM PDT 24 Mar 26 02:41:47 PM PDT 24 2625007563 ps
T59 /workspace/coverage/default/20.sysrst_ctrl_in_out_inverted.4104944755 Mar 26 02:42:03 PM PDT 24 Mar 26 02:42:06 PM PDT 24 2477785026 ps
T53 /workspace/coverage/default/38.sysrst_ctrl_ultra_low_pwr.3463240065 Mar 26 02:42:57 PM PDT 24 Mar 26 02:42:59 PM PDT 24 3928073436 ps
T32 /workspace/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.74040015 Mar 26 02:42:30 PM PDT 24 Mar 26 02:43:04 PM PDT 24 208241554174 ps
T71 /workspace/coverage/default/1.sysrst_ctrl_edge_detect.22223336 Mar 26 02:41:16 PM PDT 24 Mar 26 02:41:23 PM PDT 24 3588678057 ps
T220 /workspace/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.2786832817 Mar 26 02:41:52 PM PDT 24 Mar 26 02:41:57 PM PDT 24 2458329546 ps
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T222 /workspace/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.833365904 Mar 26 02:42:09 PM PDT 24 Mar 26 02:42:23 PM PDT 24 5087453255 ps
T72 /workspace/coverage/default/36.sysrst_ctrl_edge_detect.2704067909 Mar 26 02:42:45 PM PDT 24 Mar 26 02:42:48 PM PDT 24 3397824416 ps
T74 /workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.317904487 Mar 26 02:41:33 PM PDT 24 Mar 26 02:42:45 PM PDT 24 108356398069 ps
T60 /workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.1560421242 Mar 26 02:41:42 PM PDT 24 Mar 26 02:41:50 PM PDT 24 2483698904 ps
T46 /workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.1058165503 Mar 26 02:43:35 PM PDT 24 Mar 26 02:44:10 PM PDT 24 14863638620 ps
T223 /workspace/coverage/default/42.sysrst_ctrl_pin_access_test.893134091 Mar 26 02:43:08 PM PDT 24 Mar 26 02:43:12 PM PDT 24 2062597736 ps
T282 /workspace/coverage/default/26.sysrst_ctrl_stress_all.2921605871 Mar 26 02:42:27 PM PDT 24 Mar 26 02:43:30 PM PDT 24 81902498532 ps
T389 /workspace/coverage/default/18.sysrst_ctrl_edge_detect.1042418353 Mar 26 02:42:02 PM PDT 24 Mar 26 02:42:10 PM PDT 24 2497638639 ps
T61 /workspace/coverage/default/17.sysrst_ctrl_stress_all.3971871978 Mar 26 02:42:03 PM PDT 24 Mar 26 02:42:09 PM PDT 24 7115521651 ps
T75 /workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.1283561188 Mar 26 02:44:04 PM PDT 24 Mar 26 02:45:09 PM PDT 24 24332368616 ps
T390 /workspace/coverage/default/29.sysrst_ctrl_alert_test.3075630417 Mar 26 02:42:26 PM PDT 24 Mar 26 02:42:32 PM PDT 24 2014049379 ps
T117 /workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.1859844031 Mar 26 02:44:01 PM PDT 24 Mar 26 02:44:33 PM PDT 24 46158806281 ps
T118 /workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.930724524 Mar 26 02:43:59 PM PDT 24 Mar 26 02:48:21 PM PDT 24 99670420079 ps
T391 /workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.1647465038 Mar 26 02:41:42 PM PDT 24 Mar 26 02:41:54 PM PDT 24 4118891280 ps
T385 /workspace/coverage/default/34.sysrst_ctrl_pin_override_test.40106124 Mar 26 02:42:39 PM PDT 24 Mar 26 02:42:43 PM PDT 24 2518201671 ps
T261 /workspace/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.1248450264 Mar 26 02:42:49 PM PDT 24 Mar 26 02:43:11 PM PDT 24 35422459476 ps
T392 /workspace/coverage/default/37.sysrst_ctrl_smoke.1818720843 Mar 26 02:42:54 PM PDT 24 Mar 26 02:43:00 PM PDT 24 2112602451 ps
T54 /workspace/coverage/default/4.sysrst_ctrl_ultra_low_pwr.44766127 Mar 26 02:41:18 PM PDT 24 Mar 26 02:41:21 PM PDT 24 8913367553 ps
T267 /workspace/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.445144655 Mar 26 02:41:54 PM PDT 24 Mar 26 02:42:33 PM PDT 24 58559733014 ps
T20 /workspace/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.2580396962 Mar 26 02:41:18 PM PDT 24 Mar 26 02:42:32 PM PDT 24 54390751771 ps
T62 /workspace/coverage/default/17.sysrst_ctrl_in_out_inverted.2363762244 Mar 26 02:42:03 PM PDT 24 Mar 26 02:42:12 PM PDT 24 2475425877 ps
T97 /workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.1887820382 Mar 26 02:44:07 PM PDT 24 Mar 26 02:44:24 PM PDT 24 25613555268 ps
T63 /workspace/coverage/default/4.sysrst_ctrl_stress_all.4188006141 Mar 26 02:41:34 PM PDT 24 Mar 26 02:42:05 PM PDT 24 11226018585 ps
T55 /workspace/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.688267141 Mar 26 02:42:48 PM PDT 24 Mar 26 02:44:06 PM PDT 24 134303909956 ps
T64 /workspace/coverage/default/21.sysrst_ctrl_in_out_inverted.2172345824 Mar 26 02:42:08 PM PDT 24 Mar 26 02:42:11 PM PDT 24 2491088037 ps
T56 /workspace/coverage/default/22.sysrst_ctrl_ultra_low_pwr.3296838741 Mar 26 02:42:12 PM PDT 24 Mar 26 02:42:28 PM PDT 24 1192595123122 ps
T136 /workspace/coverage/default/27.sysrst_ctrl_pin_access_test.2625798830 Mar 26 02:42:28 PM PDT 24 Mar 26 02:42:30 PM PDT 24 2127027424 ps
T137 /workspace/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.412803219 Mar 26 02:42:37 PM PDT 24 Mar 26 02:42:45 PM PDT 24 2610790954 ps
T138 /workspace/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.2051125024 Mar 26 02:41:48 PM PDT 24 Mar 26 02:41:51 PM PDT 24 2636503534 ps
T393 /workspace/coverage/default/26.sysrst_ctrl_smoke.3300052286 Mar 26 02:42:23 PM PDT 24 Mar 26 02:42:24 PM PDT 24 2137870695 ps
T284 /workspace/coverage/default/26.sysrst_ctrl_combo_detect.1192750299 Mar 26 02:42:29 PM PDT 24 Mar 26 02:49:23 PM PDT 24 146422426260 ps
T285 /workspace/coverage/default/25.sysrst_ctrl_combo_detect.544244101 Mar 26 02:42:24 PM PDT 24 Mar 26 02:45:58 PM PDT 24 88419598568 ps
T394 /workspace/coverage/default/49.sysrst_ctrl_smoke.2876199888 Mar 26 02:43:48 PM PDT 24 Mar 26 02:43:50 PM PDT 24 2129383502 ps
T153 /workspace/coverage/default/33.sysrst_ctrl_edge_detect.74322931 Mar 26 02:42:34 PM PDT 24 Mar 26 02:42:37 PM PDT 24 2964474041 ps
T163 /workspace/coverage/default/41.sysrst_ctrl_alert_test.2294098568 Mar 26 02:43:10 PM PDT 24 Mar 26 02:43:12 PM PDT 24 2160866580 ps
T164 /workspace/coverage/default/3.sysrst_ctrl_in_out_inverted.805511099 Mar 26 02:41:18 PM PDT 24 Mar 26 02:41:20 PM PDT 24 2466347124 ps
T165 /workspace/coverage/default/2.sysrst_ctrl_sec_cm.1601342235 Mar 26 02:41:17 PM PDT 24 Mar 26 02:42:13 PM PDT 24 22008566615 ps
T166 /workspace/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.906050678 Mar 26 02:41:56 PM PDT 24 Mar 26 02:41:59 PM PDT 24 2490796360 ps
T57 /workspace/coverage/default/42.sysrst_ctrl_stress_all.3045313110 Mar 26 02:43:09 PM PDT 24 Mar 26 02:43:18 PM PDT 24 24964024994 ps
T98 /workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.3747985906 Mar 26 02:43:56 PM PDT 24 Mar 26 02:44:37 PM PDT 24 32314773979 ps
T76 /workspace/coverage/default/39.sysrst_ctrl_ultra_low_pwr.825832506 Mar 26 02:42:57 PM PDT 24 Mar 26 02:43:00 PM PDT 24 3740443828 ps
T125 /workspace/coverage/default/10.sysrst_ctrl_pin_access_test.3678265645 Mar 26 02:41:46 PM PDT 24 Mar 26 02:41:53 PM PDT 24 2187178701 ps
T96 /workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.792134084 Mar 26 02:41:49 PM PDT 24 Mar 26 02:41:59 PM PDT 24 3229210059 ps
T126 /workspace/coverage/default/31.sysrst_ctrl_alert_test.325589596 Mar 26 02:42:34 PM PDT 24 Mar 26 02:42:36 PM PDT 24 2087484209 ps
T127 /workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.689526031 Mar 26 02:43:59 PM PDT 24 Mar 26 02:49:04 PM PDT 24 119808097331 ps
T128 /workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.2120928444 Mar 26 02:43:22 PM PDT 24 Mar 26 02:43:23 PM PDT 24 2833997001 ps
T129 /workspace/coverage/default/29.sysrst_ctrl_combo_detect.3205075435 Mar 26 02:42:27 PM PDT 24 Mar 26 02:47:21 PM PDT 24 111858483612 ps
T130 /workspace/coverage/default/45.sysrst_ctrl_combo_detect.1811152281 Mar 26 02:43:22 PM PDT 24 Mar 26 02:44:18 PM PDT 24 80060199295 ps
T131 /workspace/coverage/default/0.sysrst_ctrl_pin_access_test.878567957 Mar 26 02:41:11 PM PDT 24 Mar 26 02:41:14 PM PDT 24 2205246762 ps
T132 /workspace/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.2720671607 Mar 26 02:42:54 PM PDT 24 Mar 26 02:43:01 PM PDT 24 2612201471 ps
T34 /workspace/coverage/default/19.sysrst_ctrl_stress_all.540485535 Mar 26 02:42:02 PM PDT 24 Mar 26 02:51:34 PM PDT 24 226149503661 ps
T274 /workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.3886083206 Mar 26 02:43:22 PM PDT 24 Mar 26 02:43:32 PM PDT 24 3592014840 ps
T275 /workspace/coverage/default/38.sysrst_ctrl_pin_access_test.2313670889 Mar 26 02:42:58 PM PDT 24 Mar 26 02:42:59 PM PDT 24 2310459480 ps
T262 /workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.3755346444 Mar 26 02:43:57 PM PDT 24 Mar 26 02:44:46 PM PDT 24 64669738596 ps
T276 /workspace/coverage/default/37.sysrst_ctrl_alert_test.2666825545 Mar 26 02:42:54 PM PDT 24 Mar 26 02:42:57 PM PDT 24 2030882558 ps
T85 /workspace/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.2827833807 Mar 26 02:41:48 PM PDT 24 Mar 26 02:42:25 PM PDT 24 56439844411 ps
T203 /workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.3713497266 Mar 26 02:43:10 PM PDT 24 Mar 26 02:43:13 PM PDT 24 2489503405 ps
T204 /workspace/coverage/default/39.sysrst_ctrl_auto_blk_key_output.1866804986 Mar 26 02:42:56 PM PDT 24 Mar 26 02:43:01 PM PDT 24 3177450585 ps
T205 /workspace/coverage/default/5.sysrst_ctrl_stress_all.1912806716 Mar 26 02:41:32 PM PDT 24 Mar 26 02:41:40 PM PDT 24 11101730565 ps
T77 /workspace/coverage/default/26.sysrst_ctrl_ultra_low_pwr.1623806911 Mar 26 02:42:30 PM PDT 24 Mar 26 02:43:30 PM PDT 24 453246586904 ps
T206 /workspace/coverage/default/40.sysrst_ctrl_pin_access_test.3913170668 Mar 26 02:42:57 PM PDT 24 Mar 26 02:43:02 PM PDT 24 2018937260 ps
T207 /workspace/coverage/default/48.sysrst_ctrl_combo_detect.2003516614 Mar 26 02:43:38 PM PDT 24 Mar 26 02:45:13 PM PDT 24 138811523337 ps
T208 /workspace/coverage/default/43.sysrst_ctrl_combo_detect.4141503702 Mar 26 02:43:11 PM PDT 24 Mar 26 02:47:09 PM PDT 24 173064474184 ps
T209 /workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.1497064941 Mar 26 02:41:30 PM PDT 24 Mar 26 02:41:32 PM PDT 24 3725826956 ps
T210 /workspace/coverage/default/24.sysrst_ctrl_in_out_inverted.2675805673 Mar 26 02:42:19 PM PDT 24 Mar 26 02:42:23 PM PDT 24 2486016348 ps
T308 /workspace/coverage/default/1.sysrst_ctrl_stress_all.4241093769 Mar 26 02:41:19 PM PDT 24 Mar 26 02:41:31 PM PDT 24 19217206847 ps
T395 /workspace/coverage/default/31.sysrst_ctrl_pin_override_test.2378377917 Mar 26 02:42:36 PM PDT 24 Mar 26 02:42:38 PM PDT 24 2531297815 ps
T35 /workspace/coverage/default/3.sysrst_ctrl_edge_detect.3111125116 Mar 26 02:41:19 PM PDT 24 Mar 26 02:41:22 PM PDT 24 6044687784 ps
T226 /workspace/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.1406689772 Mar 26 02:42:19 PM PDT 24 Mar 26 02:42:22 PM PDT 24 2630270703 ps
T227 /workspace/coverage/default/0.sysrst_ctrl_stress_all.2562392365 Mar 26 02:41:16 PM PDT 24 Mar 26 02:42:10 PM PDT 24 97081317851 ps
T228 /workspace/coverage/default/2.sysrst_ctrl_pin_access_test.1653379461 Mar 26 02:41:18 PM PDT 24 Mar 26 02:41:20 PM PDT 24 2095617041 ps
T229 /workspace/coverage/default/32.sysrst_ctrl_ultra_low_pwr.3475124576 Mar 26 02:42:34 PM PDT 24 Mar 26 02:42:36 PM PDT 24 6062100156 ps
T230 /workspace/coverage/default/36.sysrst_ctrl_stress_all.3194211122 Mar 26 02:42:46 PM PDT 24 Mar 26 02:43:02 PM PDT 24 11672178543 ps
T231 /workspace/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.3953280844 Mar 26 02:42:26 PM PDT 24 Mar 26 02:42:33 PM PDT 24 2434796618 ps
T232 /workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.1565000484 Mar 26 02:43:24 PM PDT 24 Mar 26 02:43:28 PM PDT 24 2469352983 ps
T233 /workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.1025731231 Mar 26 02:43:57 PM PDT 24 Mar 26 02:46:06 PM PDT 24 46331607548 ps
T234 /workspace/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.1439044890 Mar 26 02:41:48 PM PDT 24 Mar 26 02:41:50 PM PDT 24 2697289908 ps
T78 /workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.2280406560 Mar 26 02:43:21 PM PDT 24 Mar 26 02:45:47 PM PDT 24 77992463665 ps
T396 /workspace/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.4271928594 Mar 26 02:42:38 PM PDT 24 Mar 26 02:42:50 PM PDT 24 4245275530 ps
T397 /workspace/coverage/default/21.sysrst_ctrl_stress_all.3930632385 Mar 26 02:42:12 PM PDT 24 Mar 26 02:42:30 PM PDT 24 11966693864 ps
T398 /workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.1979378195 Mar 26 02:43:47 PM PDT 24 Mar 26 02:43:52 PM PDT 24 4210477609 ps
T399 /workspace/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.4183960102 Mar 26 02:42:55 PM PDT 24 Mar 26 02:43:03 PM PDT 24 2612053865 ps
T263 /workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.3741333228 Mar 26 02:43:58 PM PDT 24 Mar 26 02:44:46 PM PDT 24 44570848954 ps
T400 /workspace/coverage/default/0.sysrst_ctrl_smoke.299883798 Mar 26 02:41:18 PM PDT 24 Mar 26 02:41:24 PM PDT 24 2112536464 ps
T309 /workspace/coverage/default/26.sysrst_ctrl_auto_blk_key_output.2528322718 Mar 26 02:42:20 PM PDT 24 Mar 26 02:42:29 PM PDT 24 3260915914 ps
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T401 /workspace/coverage/default/14.sysrst_ctrl_alert_test.1825012181 Mar 26 02:41:47 PM PDT 24 Mar 26 02:41:53 PM PDT 24 2011476971 ps
T307 /workspace/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.3573863741 Mar 26 02:42:42 PM PDT 24 Mar 26 02:43:25 PM PDT 24 18560737439 ps
T156 /workspace/coverage/default/28.sysrst_ctrl_edge_detect.2386944073 Mar 26 02:42:29 PM PDT 24 Mar 26 02:42:35 PM PDT 24 3134840190 ps
T181 /workspace/coverage/default/42.sysrst_ctrl_edge_detect.1126162399 Mar 26 02:43:10 PM PDT 24 Mar 26 02:43:15 PM PDT 24 2763832776 ps
T402 /workspace/coverage/default/22.sysrst_ctrl_pin_access_test.3284926658 Mar 26 02:42:16 PM PDT 24 Mar 26 02:42:21 PM PDT 24 2117403536 ps
T342 /workspace/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.3961181901 Mar 26 02:42:22 PM PDT 24 Mar 26 02:45:04 PM PDT 24 62223588599 ps
T403 /workspace/coverage/default/15.sysrst_ctrl_pin_access_test.3282011542 Mar 26 02:41:50 PM PDT 24 Mar 26 02:41:56 PM PDT 24 2063315059 ps
T317 /workspace/coverage/default/1.sysrst_ctrl_pin_override_test.4046420870 Mar 26 02:41:15 PM PDT 24 Mar 26 02:41:19 PM PDT 24 2519708394 ps
T404 /workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.907971779 Mar 26 02:41:43 PM PDT 24 Mar 26 02:41:50 PM PDT 24 2650437236 ps
T405 /workspace/coverage/default/7.sysrst_ctrl_smoke.641108875 Mar 26 02:41:31 PM PDT 24 Mar 26 02:41:37 PM PDT 24 2108481684 ps
T283 /workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.3828478286 Mar 26 02:43:58 PM PDT 24 Mar 26 02:46:42 PM PDT 24 92532957245 ps
T406 /workspace/coverage/default/31.sysrst_ctrl_smoke.2782680523 Mar 26 02:42:38 PM PDT 24 Mar 26 02:42:44 PM PDT 24 2111337253 ps
T99 /workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.4176593738 Mar 26 02:44:04 PM PDT 24 Mar 26 02:46:30 PM PDT 24 56659359086 ps
T407 /workspace/coverage/default/2.sysrst_ctrl_in_out_inverted.3077370347 Mar 26 02:41:17 PM PDT 24 Mar 26 02:41:25 PM PDT 24 2453855996 ps
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T409 /workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.1036719516 Mar 26 02:43:52 PM PDT 24 Mar 26 02:44:00 PM PDT 24 3180014679 ps
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T265 /workspace/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.780816446 Mar 26 02:42:12 PM PDT 24 Mar 26 02:42:44 PM PDT 24 25841317501 ps
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T433 /workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.376945301 Mar 26 02:41:31 PM PDT 24 Mar 26 02:41:38 PM PDT 24 2682768473 ps
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T435 /workspace/coverage/default/23.sysrst_ctrl_auto_blk_key_output.3399560609 Mar 26 02:42:09 PM PDT 24 Mar 26 02:42:18 PM PDT 24 3137434376 ps
T266 /workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.1507008069 Mar 26 02:44:09 PM PDT 24 Mar 26 02:44:46 PM PDT 24 49363198291 ps
T436 /workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.4079458741 Mar 26 02:41:29 PM PDT 24 Mar 26 02:41:33 PM PDT 24 2477067543 ps
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