Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
794 |
1 |
|
|
T21 |
7 |
|
T22 |
9 |
|
T23 |
8 |
| auto[1] |
886 |
1 |
|
|
T21 |
13 |
|
T22 |
11 |
|
T23 |
12 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
887 |
1 |
|
|
T21 |
11 |
|
T22 |
12 |
|
T23 |
12 |
| auto[1] |
793 |
1 |
|
|
T21 |
9 |
|
T22 |
8 |
|
T23 |
8 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
889 |
1 |
|
|
T21 |
13 |
|
T22 |
8 |
|
T23 |
11 |
| auto[1] |
791 |
1 |
|
|
T21 |
7 |
|
T22 |
12 |
|
T23 |
9 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
893 |
1 |
|
|
T21 |
12 |
|
T22 |
10 |
|
T23 |
11 |
| auto[1] |
787 |
1 |
|
|
T21 |
8 |
|
T22 |
10 |
|
T23 |
9 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
820 |
1 |
|
|
T21 |
8 |
|
T22 |
9 |
|
T23 |
8 |
| auto[1] |
860 |
1 |
|
|
T21 |
12 |
|
T22 |
11 |
|
T23 |
12 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
805 |
1 |
|
|
T21 |
12 |
|
T22 |
8 |
|
T23 |
11 |
| auto[1] |
875 |
1 |
|
|
T21 |
8 |
|
T22 |
12 |
|
T23 |
9 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
831 |
1 |
|
|
T21 |
5 |
|
T22 |
9 |
|
T23 |
11 |
| auto[1] |
849 |
1 |
|
|
T21 |
15 |
|
T22 |
11 |
|
T23 |
9 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
876 |
1 |
|
|
T21 |
11 |
|
T22 |
12 |
|
T23 |
10 |
| auto[1] |
804 |
1 |
|
|
T21 |
9 |
|
T22 |
8 |
|
T23 |
10 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
799 |
1 |
|
|
T21 |
8 |
|
T22 |
13 |
|
T23 |
12 |
| auto[1] |
881 |
1 |
|
|
T21 |
12 |
|
T22 |
7 |
|
T23 |
8 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
839 |
1 |
|
|
T21 |
12 |
|
T22 |
11 |
|
T23 |
10 |
| auto[1] |
841 |
1 |
|
|
T21 |
8 |
|
T22 |
9 |
|
T23 |
10 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
869 |
1 |
|
|
T21 |
6 |
|
T22 |
11 |
|
T23 |
8 |
| auto[1] |
811 |
1 |
|
|
T21 |
14 |
|
T22 |
9 |
|
T23 |
12 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
831 |
1 |
|
|
T21 |
15 |
|
T22 |
12 |
|
T23 |
7 |
| auto[1] |
849 |
1 |
|
|
T21 |
5 |
|
T22 |
8 |
|
T23 |
13 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
797 |
1 |
|
|
T21 |
10 |
|
T22 |
9 |
|
T23 |
8 |
| auto[1] |
883 |
1 |
|
|
T21 |
10 |
|
T22 |
11 |
|
T23 |
12 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
887 |
1 |
|
|
T21 |
11 |
|
T22 |
12 |
|
T23 |
12 |
| auto[1] |
793 |
1 |
|
|
T21 |
9 |
|
T22 |
8 |
|
T23 |
8 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
844 |
1 |
|
|
T21 |
8 |
|
T22 |
9 |
|
T23 |
6 |
| auto[1] |
836 |
1 |
|
|
T21 |
12 |
|
T22 |
11 |
|
T23 |
14 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
818 |
1 |
|
|
T21 |
11 |
|
T22 |
9 |
|
T23 |
10 |
| auto[1] |
862 |
1 |
|
|
T21 |
9 |
|
T22 |
11 |
|
T23 |
10 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
841 |
1 |
|
|
T21 |
9 |
|
T22 |
8 |
|
T23 |
13 |
| auto[1] |
839 |
1 |
|
|
T21 |
11 |
|
T22 |
12 |
|
T23 |
7 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
872 |
1 |
|
|
T21 |
7 |
|
T22 |
5 |
|
T23 |
8 |
| auto[1] |
808 |
1 |
|
|
T21 |
13 |
|
T22 |
15 |
|
T23 |
12 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
836 |
1 |
|
|
T21 |
11 |
|
T22 |
7 |
|
T23 |
10 |
| auto[1] |
844 |
1 |
|
|
T21 |
9 |
|
T22 |
13 |
|
T23 |
10 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
829 |
1 |
|
|
T21 |
9 |
|
T22 |
12 |
|
T23 |
9 |
| auto[1] |
851 |
1 |
|
|
T21 |
11 |
|
T22 |
8 |
|
T23 |
11 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
845 |
1 |
|
|
T21 |
8 |
|
T22 |
10 |
|
T23 |
13 |
| auto[1] |
835 |
1 |
|
|
T21 |
12 |
|
T22 |
10 |
|
T23 |
7 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
808 |
1 |
|
|
T21 |
10 |
|
T22 |
11 |
|
T23 |
14 |
| auto[1] |
872 |
1 |
|
|
T21 |
10 |
|
T22 |
9 |
|
T23 |
6 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
844 |
1 |
|
|
T21 |
12 |
|
T22 |
9 |
|
T23 |
12 |
| auto[1] |
836 |
1 |
|
|
T21 |
8 |
|
T22 |
11 |
|
T23 |
8 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
831 |
1 |
|
|
T21 |
15 |
|
T22 |
12 |
|
T23 |
7 |
| auto[1] |
849 |
1 |
|
|
T21 |
5 |
|
T22 |
8 |
|
T23 |
13 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
459 |
1 |
|
|
T21 |
6 |
|
T22 |
3 |
|
T23 |
3 |
| auto[0] |
auto[1] |
385 |
1 |
|
|
T21 |
2 |
|
T22 |
6 |
|
T23 |
3 |
| auto[1] |
auto[0] |
430 |
1 |
|
|
T21 |
7 |
|
T22 |
5 |
|
T23 |
8 |
| auto[1] |
auto[1] |
406 |
1 |
|
|
T21 |
5 |
|
T22 |
6 |
|
T23 |
6 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
448 |
1 |
|
|
T21 |
7 |
|
T22 |
4 |
|
T23 |
5 |
| auto[0] |
auto[1] |
370 |
1 |
|
|
T21 |
4 |
|
T22 |
5 |
|
T23 |
5 |
| auto[1] |
auto[0] |
445 |
1 |
|
|
T21 |
5 |
|
T22 |
6 |
|
T23 |
6 |
| auto[1] |
auto[1] |
417 |
1 |
|
|
T21 |
4 |
|
T22 |
5 |
|
T23 |
4 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
395 |
1 |
|
|
T21 |
3 |
|
T22 |
4 |
|
T23 |
7 |
| auto[0] |
auto[1] |
446 |
1 |
|
|
T21 |
6 |
|
T22 |
4 |
|
T23 |
6 |
| auto[1] |
auto[0] |
425 |
1 |
|
|
T21 |
5 |
|
T22 |
5 |
|
T23 |
1 |
| auto[1] |
auto[1] |
414 |
1 |
|
|
T21 |
6 |
|
T22 |
7 |
|
T23 |
6 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
403 |
1 |
|
|
T21 |
4 |
|
T22 |
2 |
|
T23 |
6 |
| auto[0] |
auto[1] |
469 |
1 |
|
|
T21 |
3 |
|
T22 |
3 |
|
T23 |
2 |
| auto[1] |
auto[0] |
402 |
1 |
|
|
T21 |
8 |
|
T22 |
6 |
|
T23 |
5 |
| auto[1] |
auto[1] |
406 |
1 |
|
|
T21 |
5 |
|
T22 |
9 |
|
T23 |
7 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
408 |
1 |
|
|
T21 |
2 |
|
T22 |
2 |
|
T23 |
5 |
| auto[0] |
auto[1] |
428 |
1 |
|
|
T21 |
9 |
|
T22 |
5 |
|
T23 |
5 |
| auto[1] |
auto[0] |
423 |
1 |
|
|
T21 |
3 |
|
T22 |
7 |
|
T23 |
6 |
| auto[1] |
auto[1] |
421 |
1 |
|
|
T21 |
6 |
|
T22 |
6 |
|
T23 |
4 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
427 |
1 |
|
|
T21 |
4 |
|
T22 |
6 |
|
T23 |
4 |
| auto[0] |
auto[1] |
402 |
1 |
|
|
T21 |
5 |
|
T22 |
6 |
|
T23 |
5 |
| auto[1] |
auto[0] |
449 |
1 |
|
|
T21 |
7 |
|
T22 |
6 |
|
T23 |
6 |
| auto[1] |
auto[1] |
402 |
1 |
|
|
T21 |
4 |
|
T22 |
2 |
|
T23 |
5 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
405 |
1 |
|
|
T21 |
6 |
|
T22 |
7 |
|
T23 |
5 |
| auto[0] |
auto[1] |
403 |
1 |
|
|
T21 |
4 |
|
T22 |
4 |
|
T23 |
9 |
| auto[1] |
auto[0] |
434 |
1 |
|
|
T21 |
6 |
|
T22 |
4 |
|
T23 |
5 |
| auto[1] |
auto[1] |
438 |
1 |
|
|
T21 |
4 |
|
T22 |
5 |
|
T23 |
1 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
438 |
1 |
|
|
T21 |
4 |
|
T22 |
6 |
|
T23 |
3 |
| auto[0] |
auto[1] |
406 |
1 |
|
|
T21 |
8 |
|
T22 |
3 |
|
T23 |
9 |
| auto[1] |
auto[0] |
431 |
1 |
|
|
T21 |
2 |
|
T22 |
5 |
|
T23 |
5 |
| auto[1] |
auto[1] |
405 |
1 |
|
|
T21 |
6 |
|
T22 |
6 |
|
T23 |
3 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
368 |
1 |
|
|
T21 |
1 |
|
T22 |
5 |
|
T23 |
3 |
| auto[0] |
auto[1] |
429 |
1 |
|
|
T21 |
9 |
|
T22 |
4 |
|
T23 |
5 |
| auto[1] |
auto[0] |
426 |
1 |
|
|
T21 |
6 |
|
T22 |
4 |
|
T23 |
5 |
| auto[1] |
auto[1] |
457 |
1 |
|
|
T21 |
4 |
|
T22 |
7 |
|
T23 |
7 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
887 |
1 |
|
|
T21 |
11 |
|
T22 |
12 |
|
T23 |
12 |
| auto[1] |
auto[1] |
793 |
1 |
|
|
T21 |
9 |
|
T22 |
8 |
|
T23 |
8 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
438 |
1 |
|
|
T21 |
3 |
|
T22 |
8 |
|
T23 |
7 |
| auto[0] |
auto[1] |
407 |
1 |
|
|
T21 |
5 |
|
T22 |
2 |
|
T23 |
6 |
| auto[1] |
auto[0] |
361 |
1 |
|
|
T21 |
5 |
|
T22 |
5 |
|
T23 |
5 |
| auto[1] |
auto[1] |
474 |
1 |
|
|
T21 |
7 |
|
T22 |
5 |
|
T23 |
2 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
831 |
1 |
|
|
T21 |
15 |
|
T22 |
12 |
|
T23 |
7 |
| auto[1] |
auto[1] |
849 |
1 |
|
|
T21 |
5 |
|
T22 |
8 |
|
T23 |
13 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
171 |
1 |
|
|
T57 |
9 |
|
T86 |
10 |
|
T154 |
10 |
| auto[1] |
149 |
1 |
|
|
T57 |
11 |
|
T86 |
10 |
|
T154 |
10 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
147 |
1 |
|
|
T57 |
13 |
|
T86 |
5 |
|
T154 |
8 |
| auto[1] |
173 |
1 |
|
|
T57 |
7 |
|
T86 |
15 |
|
T154 |
12 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
173 |
1 |
|
|
T57 |
7 |
|
T86 |
14 |
|
T154 |
8 |
| auto[1] |
147 |
1 |
|
|
T57 |
13 |
|
T86 |
6 |
|
T154 |
12 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
157 |
1 |
|
|
T57 |
13 |
|
T86 |
12 |
|
T154 |
8 |
| auto[1] |
163 |
1 |
|
|
T57 |
7 |
|
T86 |
8 |
|
T154 |
12 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
165 |
1 |
|
|
T57 |
13 |
|
T86 |
10 |
|
T154 |
10 |
| auto[1] |
155 |
1 |
|
|
T57 |
7 |
|
T86 |
10 |
|
T154 |
10 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
153 |
1 |
|
|
T57 |
13 |
|
T86 |
9 |
|
T154 |
9 |
| auto[1] |
167 |
1 |
|
|
T57 |
7 |
|
T86 |
11 |
|
T154 |
11 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
179 |
1 |
|
|
T57 |
14 |
|
T86 |
9 |
|
T154 |
14 |
| auto[1] |
141 |
1 |
|
|
T57 |
6 |
|
T86 |
11 |
|
T154 |
6 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
156 |
1 |
|
|
T57 |
10 |
|
T86 |
10 |
|
T154 |
14 |
| auto[1] |
164 |
1 |
|
|
T57 |
10 |
|
T86 |
10 |
|
T154 |
6 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
142 |
1 |
|
|
T57 |
10 |
|
T86 |
8 |
|
T154 |
9 |
| auto[1] |
178 |
1 |
|
|
T57 |
10 |
|
T86 |
12 |
|
T154 |
11 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
150 |
1 |
|
|
T57 |
10 |
|
T86 |
4 |
|
T154 |
8 |
| auto[1] |
170 |
1 |
|
|
T57 |
10 |
|
T86 |
16 |
|
T154 |
12 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
146 |
1 |
|
|
T57 |
9 |
|
T86 |
12 |
|
T154 |
12 |
| auto[1] |
174 |
1 |
|
|
T57 |
11 |
|
T86 |
8 |
|
T154 |
8 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
167 |
1 |
|
|
T57 |
11 |
|
T86 |
13 |
|
T154 |
10 |
| auto[1] |
153 |
1 |
|
|
T57 |
9 |
|
T86 |
7 |
|
T154 |
10 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
161 |
1 |
|
|
T57 |
13 |
|
T86 |
7 |
|
T154 |
11 |
| auto[1] |
159 |
1 |
|
|
T57 |
7 |
|
T86 |
13 |
|
T154 |
9 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
147 |
1 |
|
|
T57 |
13 |
|
T86 |
5 |
|
T154 |
8 |
| auto[1] |
173 |
1 |
|
|
T57 |
7 |
|
T86 |
15 |
|
T154 |
12 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
147 |
1 |
|
|
T57 |
9 |
|
T86 |
10 |
|
T154 |
11 |
| auto[1] |
173 |
1 |
|
|
T57 |
11 |
|
T86 |
10 |
|
T154 |
9 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
167 |
1 |
|
|
T57 |
11 |
|
T86 |
10 |
|
T154 |
7 |
| auto[1] |
153 |
1 |
|
|
T57 |
9 |
|
T86 |
10 |
|
T154 |
13 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
153 |
1 |
|
|
T57 |
9 |
|
T86 |
7 |
|
T154 |
7 |
| auto[1] |
167 |
1 |
|
|
T57 |
11 |
|
T86 |
13 |
|
T154 |
13 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
163 |
1 |
|
|
T57 |
11 |
|
T86 |
10 |
|
T154 |
10 |
| auto[1] |
157 |
1 |
|
|
T57 |
9 |
|
T86 |
10 |
|
T154 |
10 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
161 |
1 |
|
|
T57 |
6 |
|
T86 |
14 |
|
T154 |
11 |
| auto[1] |
159 |
1 |
|
|
T57 |
14 |
|
T86 |
6 |
|
T154 |
9 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
156 |
1 |
|
|
T57 |
8 |
|
T86 |
9 |
|
T154 |
13 |
| auto[1] |
164 |
1 |
|
|
T57 |
12 |
|
T86 |
11 |
|
T154 |
7 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
175 |
1 |
|
|
T57 |
10 |
|
T86 |
11 |
|
T154 |
10 |
| auto[1] |
145 |
1 |
|
|
T57 |
10 |
|
T86 |
9 |
|
T154 |
10 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
153 |
1 |
|
|
T57 |
8 |
|
T86 |
10 |
|
T154 |
8 |
| auto[1] |
167 |
1 |
|
|
T57 |
12 |
|
T86 |
10 |
|
T154 |
12 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
151 |
1 |
|
|
T57 |
9 |
|
T86 |
8 |
|
T154 |
12 |
| auto[1] |
169 |
1 |
|
|
T57 |
11 |
|
T86 |
12 |
|
T154 |
8 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
167 |
1 |
|
|
T57 |
11 |
|
T86 |
13 |
|
T154 |
10 |
| auto[1] |
153 |
1 |
|
|
T57 |
9 |
|
T86 |
7 |
|
T154 |
10 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
82 |
1 |
|
|
T57 |
4 |
|
T86 |
9 |
|
T154 |
6 |
| auto[0] |
auto[1] |
65 |
1 |
|
|
T57 |
5 |
|
T86 |
1 |
|
T154 |
5 |
| auto[1] |
auto[0] |
91 |
1 |
|
|
T57 |
3 |
|
T86 |
5 |
|
T154 |
2 |
| auto[1] |
auto[1] |
82 |
1 |
|
|
T57 |
8 |
|
T86 |
5 |
|
T154 |
7 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
84 |
1 |
|
|
T57 |
8 |
|
T86 |
8 |
|
T154 |
4 |
| auto[0] |
auto[1] |
83 |
1 |
|
|
T57 |
3 |
|
T86 |
2 |
|
T154 |
3 |
| auto[1] |
auto[0] |
73 |
1 |
|
|
T57 |
5 |
|
T86 |
4 |
|
T154 |
4 |
| auto[1] |
auto[1] |
80 |
1 |
|
|
T57 |
4 |
|
T86 |
6 |
|
T154 |
9 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
72 |
1 |
|
|
T57 |
5 |
|
T86 |
2 |
|
T154 |
3 |
| auto[0] |
auto[1] |
81 |
1 |
|
|
T57 |
4 |
|
T86 |
5 |
|
T154 |
4 |
| auto[1] |
auto[0] |
93 |
1 |
|
|
T57 |
8 |
|
T86 |
8 |
|
T154 |
7 |
| auto[1] |
auto[1] |
74 |
1 |
|
|
T57 |
3 |
|
T86 |
5 |
|
T154 |
6 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
71 |
1 |
|
|
T57 |
6 |
|
T86 |
3 |
|
T154 |
4 |
| auto[0] |
auto[1] |
92 |
1 |
|
|
T57 |
5 |
|
T86 |
7 |
|
T154 |
6 |
| auto[1] |
auto[0] |
82 |
1 |
|
|
T57 |
7 |
|
T86 |
6 |
|
T154 |
5 |
| auto[1] |
auto[1] |
75 |
1 |
|
|
T57 |
2 |
|
T86 |
4 |
|
T154 |
5 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
86 |
1 |
|
|
T57 |
4 |
|
T86 |
9 |
|
T154 |
8 |
| auto[0] |
auto[1] |
75 |
1 |
|
|
T57 |
2 |
|
T86 |
5 |
|
T154 |
3 |
| auto[1] |
auto[0] |
93 |
1 |
|
|
T57 |
10 |
|
T154 |
6 |
|
T179 |
3 |
| auto[1] |
auto[1] |
66 |
1 |
|
|
T57 |
4 |
|
T86 |
6 |
|
T154 |
3 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
72 |
1 |
|
|
T57 |
3 |
|
T86 |
7 |
|
T154 |
9 |
| auto[0] |
auto[1] |
84 |
1 |
|
|
T57 |
5 |
|
T86 |
2 |
|
T154 |
4 |
| auto[1] |
auto[0] |
84 |
1 |
|
|
T57 |
7 |
|
T86 |
3 |
|
T154 |
5 |
| auto[1] |
auto[1] |
80 |
1 |
|
|
T57 |
5 |
|
T86 |
8 |
|
T154 |
2 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
70 |
1 |
|
|
T57 |
5 |
|
T86 |
2 |
|
T154 |
3 |
| auto[0] |
auto[1] |
83 |
1 |
|
|
T57 |
3 |
|
T86 |
8 |
|
T154 |
5 |
| auto[1] |
auto[0] |
80 |
1 |
|
|
T57 |
5 |
|
T86 |
2 |
|
T154 |
5 |
| auto[1] |
auto[1] |
87 |
1 |
|
|
T57 |
7 |
|
T86 |
8 |
|
T154 |
7 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
67 |
1 |
|
|
T57 |
5 |
|
T86 |
5 |
|
T154 |
7 |
| auto[0] |
auto[1] |
84 |
1 |
|
|
T57 |
4 |
|
T86 |
3 |
|
T154 |
5 |
| auto[1] |
auto[0] |
79 |
1 |
|
|
T57 |
4 |
|
T86 |
7 |
|
T154 |
5 |
| auto[1] |
auto[1] |
90 |
1 |
|
|
T57 |
7 |
|
T86 |
5 |
|
T154 |
3 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
80 |
1 |
|
|
T57 |
6 |
|
T86 |
3 |
|
T154 |
3 |
| auto[0] |
auto[1] |
81 |
1 |
|
|
T57 |
7 |
|
T86 |
4 |
|
T154 |
8 |
| auto[1] |
auto[0] |
91 |
1 |
|
|
T57 |
3 |
|
T86 |
7 |
|
T154 |
7 |
| auto[1] |
auto[1] |
68 |
1 |
|
|
T57 |
4 |
|
T86 |
6 |
|
T154 |
2 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
147 |
1 |
|
|
T57 |
13 |
|
T86 |
5 |
|
T154 |
8 |
| auto[1] |
auto[1] |
173 |
1 |
|
|
T57 |
7 |
|
T86 |
15 |
|
T154 |
12 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
86 |
1 |
|
|
T57 |
5 |
|
T86 |
5 |
|
T154 |
4 |
| auto[0] |
auto[1] |
89 |
1 |
|
|
T57 |
5 |
|
T86 |
6 |
|
T154 |
6 |
| auto[1] |
auto[0] |
56 |
1 |
|
|
T57 |
5 |
|
T86 |
3 |
|
T154 |
5 |
| auto[1] |
auto[1] |
89 |
1 |
|
|
T57 |
5 |
|
T86 |
6 |
|
T154 |
5 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
167 |
1 |
|
|
T57 |
11 |
|
T86 |
13 |
|
T154 |
10 |
| auto[1] |
auto[1] |
153 |
1 |
|
|
T57 |
9 |
|
T86 |
7 |
|
T154 |
10 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
43 |
1 |
|
|
T154 |
9 |
|
T192 |
7 |
|
T273 |
9 |
| auto[1] |
57 |
1 |
|
|
T154 |
11 |
|
T192 |
13 |
|
T273 |
11 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
55 |
1 |
|
|
T154 |
10 |
|
T192 |
10 |
|
T273 |
9 |
| auto[1] |
45 |
1 |
|
|
T154 |
10 |
|
T192 |
10 |
|
T273 |
11 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
43 |
1 |
|
|
T154 |
11 |
|
T192 |
8 |
|
T273 |
8 |
| auto[1] |
57 |
1 |
|
|
T154 |
9 |
|
T192 |
12 |
|
T273 |
12 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
47 |
1 |
|
|
T154 |
11 |
|
T192 |
9 |
|
T273 |
13 |
| auto[1] |
53 |
1 |
|
|
T154 |
9 |
|
T192 |
11 |
|
T273 |
7 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
51 |
1 |
|
|
T154 |
12 |
|
T192 |
10 |
|
T273 |
7 |
| auto[1] |
49 |
1 |
|
|
T154 |
8 |
|
T192 |
10 |
|
T273 |
13 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
43 |
1 |
|
|
T154 |
6 |
|
T192 |
8 |
|
T273 |
13 |
| auto[1] |
57 |
1 |
|
|
T154 |
14 |
|
T192 |
12 |
|
T273 |
7 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
56 |
1 |
|
|
T154 |
12 |
|
T192 |
11 |
|
T273 |
8 |
| auto[1] |
44 |
1 |
|
|
T154 |
8 |
|
T192 |
9 |
|
T273 |
12 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
52 |
1 |
|
|
T154 |
11 |
|
T192 |
7 |
|
T273 |
11 |
| auto[1] |
48 |
1 |
|
|
T154 |
9 |
|
T192 |
13 |
|
T273 |
9 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
50 |
1 |
|
|
T154 |
7 |
|
T192 |
9 |
|
T273 |
13 |
| auto[1] |
50 |
1 |
|
|
T154 |
13 |
|
T192 |
11 |
|
T273 |
7 |