Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
821 |
1 |
|
|
T6 |
12 |
|
T3 |
13 |
|
T25 |
7 |
| auto[1] |
919 |
1 |
|
|
T6 |
8 |
|
T3 |
7 |
|
T25 |
13 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
861 |
1 |
|
|
T6 |
8 |
|
T3 |
11 |
|
T25 |
12 |
| auto[1] |
879 |
1 |
|
|
T6 |
12 |
|
T3 |
9 |
|
T25 |
8 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
899 |
1 |
|
|
T6 |
11 |
|
T3 |
10 |
|
T25 |
8 |
| auto[1] |
841 |
1 |
|
|
T6 |
9 |
|
T3 |
10 |
|
T25 |
12 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
860 |
1 |
|
|
T6 |
12 |
|
T3 |
8 |
|
T25 |
8 |
| auto[1] |
880 |
1 |
|
|
T6 |
8 |
|
T3 |
12 |
|
T25 |
12 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
860 |
1 |
|
|
T6 |
10 |
|
T3 |
12 |
|
T25 |
9 |
| auto[1] |
880 |
1 |
|
|
T6 |
10 |
|
T3 |
8 |
|
T25 |
11 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
837 |
1 |
|
|
T6 |
9 |
|
T3 |
10 |
|
T25 |
6 |
| auto[1] |
903 |
1 |
|
|
T6 |
11 |
|
T3 |
10 |
|
T25 |
14 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
882 |
1 |
|
|
T6 |
14 |
|
T3 |
6 |
|
T25 |
8 |
| auto[1] |
858 |
1 |
|
|
T6 |
6 |
|
T3 |
14 |
|
T25 |
12 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
872 |
1 |
|
|
T6 |
9 |
|
T3 |
10 |
|
T25 |
15 |
| auto[1] |
868 |
1 |
|
|
T6 |
11 |
|
T3 |
10 |
|
T25 |
5 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
873 |
1 |
|
|
T6 |
10 |
|
T3 |
8 |
|
T25 |
12 |
| auto[1] |
867 |
1 |
|
|
T6 |
10 |
|
T3 |
12 |
|
T25 |
8 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
878 |
1 |
|
|
T6 |
9 |
|
T3 |
10 |
|
T25 |
11 |
| auto[1] |
862 |
1 |
|
|
T6 |
11 |
|
T3 |
10 |
|
T25 |
9 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
870 |
1 |
|
|
T6 |
10 |
|
T3 |
14 |
|
T25 |
11 |
| auto[1] |
870 |
1 |
|
|
T6 |
10 |
|
T3 |
6 |
|
T25 |
9 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
898 |
1 |
|
|
T6 |
9 |
|
T3 |
12 |
|
T25 |
12 |
| auto[1] |
842 |
1 |
|
|
T6 |
11 |
|
T3 |
8 |
|
T25 |
8 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
891 |
1 |
|
|
T6 |
9 |
|
T3 |
14 |
|
T25 |
7 |
| auto[1] |
849 |
1 |
|
|
T6 |
11 |
|
T3 |
6 |
|
T25 |
13 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
861 |
1 |
|
|
T6 |
8 |
|
T3 |
11 |
|
T25 |
12 |
| auto[1] |
879 |
1 |
|
|
T6 |
12 |
|
T3 |
9 |
|
T25 |
8 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
862 |
1 |
|
|
T6 |
9 |
|
T3 |
11 |
|
T25 |
13 |
| auto[1] |
878 |
1 |
|
|
T6 |
11 |
|
T3 |
9 |
|
T25 |
7 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
883 |
1 |
|
|
T6 |
10 |
|
T3 |
9 |
|
T25 |
11 |
| auto[1] |
857 |
1 |
|
|
T6 |
10 |
|
T3 |
11 |
|
T25 |
9 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
875 |
1 |
|
|
T6 |
9 |
|
T3 |
9 |
|
T25 |
12 |
| auto[1] |
865 |
1 |
|
|
T6 |
11 |
|
T3 |
11 |
|
T25 |
8 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
878 |
1 |
|
|
T6 |
10 |
|
T3 |
13 |
|
T25 |
13 |
| auto[1] |
862 |
1 |
|
|
T6 |
10 |
|
T3 |
7 |
|
T25 |
7 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
875 |
1 |
|
|
T6 |
8 |
|
T3 |
9 |
|
T25 |
9 |
| auto[1] |
865 |
1 |
|
|
T6 |
12 |
|
T3 |
11 |
|
T25 |
11 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
873 |
1 |
|
|
T6 |
11 |
|
T3 |
13 |
|
T25 |
8 |
| auto[1] |
867 |
1 |
|
|
T6 |
9 |
|
T3 |
7 |
|
T25 |
12 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
845 |
1 |
|
|
T6 |
9 |
|
T3 |
12 |
|
T25 |
11 |
| auto[1] |
895 |
1 |
|
|
T6 |
11 |
|
T3 |
8 |
|
T25 |
9 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
855 |
1 |
|
|
T6 |
8 |
|
T3 |
8 |
|
T25 |
14 |
| auto[1] |
885 |
1 |
|
|
T6 |
12 |
|
T3 |
12 |
|
T25 |
6 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
887 |
1 |
|
|
T6 |
13 |
|
T3 |
8 |
|
T25 |
10 |
| auto[1] |
853 |
1 |
|
|
T6 |
7 |
|
T3 |
12 |
|
T25 |
10 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
898 |
1 |
|
|
T6 |
9 |
|
T3 |
12 |
|
T25 |
12 |
| auto[1] |
842 |
1 |
|
|
T6 |
11 |
|
T3 |
8 |
|
T25 |
8 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
459 |
1 |
|
|
T6 |
3 |
|
T3 |
4 |
|
T25 |
6 |
| auto[0] |
auto[1] |
403 |
1 |
|
|
T6 |
6 |
|
T3 |
7 |
|
T25 |
7 |
| auto[1] |
auto[0] |
440 |
1 |
|
|
T6 |
8 |
|
T3 |
6 |
|
T25 |
2 |
| auto[1] |
auto[1] |
438 |
1 |
|
|
T6 |
3 |
|
T3 |
3 |
|
T25 |
5 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
450 |
1 |
|
|
T6 |
4 |
|
T3 |
2 |
|
T25 |
5 |
| auto[0] |
auto[1] |
433 |
1 |
|
|
T6 |
6 |
|
T3 |
7 |
|
T25 |
6 |
| auto[1] |
auto[0] |
410 |
1 |
|
|
T6 |
8 |
|
T3 |
6 |
|
T25 |
3 |
| auto[1] |
auto[1] |
447 |
1 |
|
|
T6 |
2 |
|
T3 |
5 |
|
T25 |
6 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
435 |
1 |
|
|
T6 |
3 |
|
T3 |
6 |
|
T25 |
6 |
| auto[0] |
auto[1] |
440 |
1 |
|
|
T6 |
6 |
|
T3 |
3 |
|
T25 |
6 |
| auto[1] |
auto[0] |
425 |
1 |
|
|
T6 |
7 |
|
T3 |
6 |
|
T25 |
3 |
| auto[1] |
auto[1] |
440 |
1 |
|
|
T6 |
4 |
|
T3 |
5 |
|
T25 |
5 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
425 |
1 |
|
|
T6 |
3 |
|
T3 |
7 |
|
T25 |
5 |
| auto[0] |
auto[1] |
453 |
1 |
|
|
T6 |
7 |
|
T3 |
6 |
|
T25 |
8 |
| auto[1] |
auto[0] |
412 |
1 |
|
|
T6 |
6 |
|
T3 |
3 |
|
T25 |
1 |
| auto[1] |
auto[1] |
450 |
1 |
|
|
T6 |
4 |
|
T3 |
4 |
|
T25 |
6 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
444 |
1 |
|
|
T6 |
6 |
|
T3 |
3 |
|
T25 |
3 |
| auto[0] |
auto[1] |
431 |
1 |
|
|
T6 |
2 |
|
T3 |
6 |
|
T25 |
6 |
| auto[1] |
auto[0] |
438 |
1 |
|
|
T6 |
8 |
|
T3 |
3 |
|
T25 |
5 |
| auto[1] |
auto[1] |
427 |
1 |
|
|
T6 |
4 |
|
T3 |
8 |
|
T25 |
6 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
438 |
1 |
|
|
T6 |
5 |
|
T3 |
7 |
|
T25 |
6 |
| auto[0] |
auto[1] |
435 |
1 |
|
|
T6 |
6 |
|
T3 |
6 |
|
T25 |
2 |
| auto[1] |
auto[0] |
434 |
1 |
|
|
T6 |
4 |
|
T3 |
3 |
|
T25 |
9 |
| auto[1] |
auto[1] |
433 |
1 |
|
|
T6 |
5 |
|
T3 |
4 |
|
T25 |
3 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
411 |
1 |
|
|
T6 |
3 |
|
T3 |
3 |
|
T25 |
8 |
| auto[0] |
auto[1] |
444 |
1 |
|
|
T6 |
5 |
|
T3 |
5 |
|
T25 |
6 |
| auto[1] |
auto[0] |
467 |
1 |
|
|
T6 |
6 |
|
T3 |
7 |
|
T25 |
3 |
| auto[1] |
auto[1] |
418 |
1 |
|
|
T6 |
6 |
|
T3 |
5 |
|
T25 |
3 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
423 |
1 |
|
|
T6 |
6 |
|
T3 |
5 |
|
T25 |
6 |
| auto[0] |
auto[1] |
464 |
1 |
|
|
T6 |
7 |
|
T3 |
3 |
|
T25 |
4 |
| auto[1] |
auto[0] |
447 |
1 |
|
|
T6 |
4 |
|
T3 |
9 |
|
T25 |
5 |
| auto[1] |
auto[1] |
406 |
1 |
|
|
T6 |
3 |
|
T3 |
3 |
|
T25 |
5 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
408 |
1 |
|
|
T6 |
3 |
|
T3 |
10 |
|
T25 |
3 |
| auto[0] |
auto[1] |
483 |
1 |
|
|
T6 |
6 |
|
T3 |
4 |
|
T25 |
4 |
| auto[1] |
auto[0] |
413 |
1 |
|
|
T6 |
9 |
|
T3 |
3 |
|
T25 |
4 |
| auto[1] |
auto[1] |
436 |
1 |
|
|
T6 |
2 |
|
T3 |
3 |
|
T25 |
9 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
861 |
1 |
|
|
T6 |
8 |
|
T3 |
11 |
|
T25 |
12 |
| auto[1] |
auto[1] |
879 |
1 |
|
|
T6 |
12 |
|
T3 |
9 |
|
T25 |
8 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
422 |
1 |
|
|
T6 |
5 |
|
T3 |
5 |
|
T25 |
8 |
| auto[0] |
auto[1] |
423 |
1 |
|
|
T6 |
4 |
|
T3 |
7 |
|
T25 |
3 |
| auto[1] |
auto[0] |
451 |
1 |
|
|
T6 |
5 |
|
T3 |
3 |
|
T25 |
4 |
| auto[1] |
auto[1] |
444 |
1 |
|
|
T6 |
6 |
|
T3 |
5 |
|
T25 |
5 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
898 |
1 |
|
|
T6 |
9 |
|
T3 |
12 |
|
T25 |
12 |
| auto[1] |
auto[1] |
842 |
1 |
|
|
T6 |
11 |
|
T3 |
8 |
|
T25 |
8 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
125 |
1 |
|
|
T34 |
11 |
|
T36 |
8 |
|
T274 |
10 |
| auto[1] |
155 |
1 |
|
|
T34 |
9 |
|
T36 |
12 |
|
T274 |
10 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
136 |
1 |
|
|
T34 |
11 |
|
T36 |
12 |
|
T274 |
10 |
| auto[1] |
144 |
1 |
|
|
T34 |
9 |
|
T36 |
8 |
|
T274 |
10 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
145 |
1 |
|
|
T34 |
13 |
|
T36 |
10 |
|
T274 |
13 |
| auto[1] |
135 |
1 |
|
|
T34 |
7 |
|
T36 |
10 |
|
T274 |
7 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
144 |
1 |
|
|
T34 |
10 |
|
T36 |
14 |
|
T274 |
11 |
| auto[1] |
136 |
1 |
|
|
T34 |
10 |
|
T36 |
6 |
|
T274 |
9 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
145 |
1 |
|
|
T34 |
7 |
|
T36 |
11 |
|
T274 |
9 |
| auto[1] |
135 |
1 |
|
|
T34 |
13 |
|
T36 |
9 |
|
T274 |
11 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
137 |
1 |
|
|
T34 |
12 |
|
T36 |
11 |
|
T274 |
8 |
| auto[1] |
143 |
1 |
|
|
T34 |
8 |
|
T36 |
9 |
|
T274 |
12 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
139 |
1 |
|
|
T34 |
8 |
|
T36 |
8 |
|
T274 |
13 |
| auto[1] |
141 |
1 |
|
|
T34 |
12 |
|
T36 |
12 |
|
T274 |
7 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
127 |
1 |
|
|
T34 |
11 |
|
T36 |
8 |
|
T274 |
8 |
| auto[1] |
153 |
1 |
|
|
T34 |
9 |
|
T36 |
12 |
|
T274 |
12 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
136 |
1 |
|
|
T34 |
11 |
|
T36 |
13 |
|
T274 |
7 |
| auto[1] |
144 |
1 |
|
|
T34 |
9 |
|
T36 |
7 |
|
T274 |
13 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
129 |
1 |
|
|
T34 |
10 |
|
T36 |
11 |
|
T274 |
9 |
| auto[1] |
151 |
1 |
|
|
T34 |
10 |
|
T36 |
9 |
|
T274 |
11 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
137 |
1 |
|
|
T34 |
12 |
|
T36 |
10 |
|
T274 |
8 |
| auto[1] |
143 |
1 |
|
|
T34 |
8 |
|
T36 |
10 |
|
T274 |
12 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
135 |
1 |
|
|
T34 |
11 |
|
T36 |
12 |
|
T274 |
13 |
| auto[1] |
145 |
1 |
|
|
T34 |
9 |
|
T36 |
8 |
|
T274 |
7 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
151 |
1 |
|
|
T34 |
14 |
|
T36 |
6 |
|
T274 |
14 |
| auto[1] |
129 |
1 |
|
|
T34 |
6 |
|
T36 |
14 |
|
T274 |
6 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
136 |
1 |
|
|
T34 |
11 |
|
T36 |
12 |
|
T274 |
10 |
| auto[1] |
144 |
1 |
|
|
T34 |
9 |
|
T36 |
8 |
|
T274 |
10 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
150 |
1 |
|
|
T34 |
13 |
|
T36 |
10 |
|
T274 |
9 |
| auto[1] |
130 |
1 |
|
|
T34 |
7 |
|
T36 |
10 |
|
T274 |
11 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
141 |
1 |
|
|
T34 |
12 |
|
T36 |
6 |
|
T274 |
11 |
| auto[1] |
139 |
1 |
|
|
T34 |
8 |
|
T36 |
14 |
|
T274 |
9 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
137 |
1 |
|
|
T34 |
12 |
|
T36 |
11 |
|
T274 |
13 |
| auto[1] |
143 |
1 |
|
|
T34 |
8 |
|
T36 |
9 |
|
T274 |
7 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
143 |
1 |
|
|
T34 |
11 |
|
T36 |
9 |
|
T274 |
12 |
| auto[1] |
137 |
1 |
|
|
T34 |
9 |
|
T36 |
11 |
|
T274 |
8 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
136 |
1 |
|
|
T34 |
8 |
|
T36 |
9 |
|
T274 |
9 |
| auto[1] |
144 |
1 |
|
|
T34 |
12 |
|
T36 |
11 |
|
T274 |
11 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
134 |
1 |
|
|
T34 |
11 |
|
T36 |
11 |
|
T274 |
6 |
| auto[1] |
146 |
1 |
|
|
T34 |
9 |
|
T36 |
9 |
|
T274 |
14 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
148 |
1 |
|
|
T34 |
9 |
|
T36 |
14 |
|
T274 |
10 |
| auto[1] |
132 |
1 |
|
|
T34 |
11 |
|
T36 |
6 |
|
T274 |
10 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
147 |
1 |
|
|
T34 |
13 |
|
T36 |
9 |
|
T274 |
11 |
| auto[1] |
133 |
1 |
|
|
T34 |
7 |
|
T36 |
11 |
|
T274 |
9 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
125 |
1 |
|
|
T34 |
7 |
|
T36 |
10 |
|
T274 |
8 |
| auto[1] |
155 |
1 |
|
|
T34 |
13 |
|
T36 |
10 |
|
T274 |
12 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
135 |
1 |
|
|
T34 |
11 |
|
T36 |
12 |
|
T274 |
13 |
| auto[1] |
145 |
1 |
|
|
T34 |
9 |
|
T36 |
8 |
|
T274 |
7 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
73 |
1 |
|
|
T34 |
10 |
|
T36 |
4 |
|
T274 |
7 |
| auto[0] |
auto[1] |
77 |
1 |
|
|
T34 |
3 |
|
T36 |
6 |
|
T274 |
2 |
| auto[1] |
auto[0] |
72 |
1 |
|
|
T34 |
3 |
|
T36 |
6 |
|
T274 |
6 |
| auto[1] |
auto[1] |
58 |
1 |
|
|
T34 |
4 |
|
T36 |
4 |
|
T274 |
5 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
68 |
1 |
|
|
T34 |
8 |
|
T36 |
4 |
|
T274 |
7 |
| auto[0] |
auto[1] |
73 |
1 |
|
|
T34 |
4 |
|
T36 |
2 |
|
T274 |
4 |
| auto[1] |
auto[0] |
76 |
1 |
|
|
T34 |
2 |
|
T36 |
10 |
|
T274 |
4 |
| auto[1] |
auto[1] |
63 |
1 |
|
|
T34 |
6 |
|
T36 |
4 |
|
T274 |
5 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
76 |
1 |
|
|
T34 |
5 |
|
T36 |
8 |
|
T274 |
4 |
| auto[0] |
auto[1] |
61 |
1 |
|
|
T34 |
7 |
|
T36 |
3 |
|
T274 |
9 |
| auto[1] |
auto[0] |
69 |
1 |
|
|
T34 |
2 |
|
T36 |
3 |
|
T274 |
5 |
| auto[1] |
auto[1] |
74 |
1 |
|
|
T34 |
6 |
|
T36 |
6 |
|
T274 |
2 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
75 |
1 |
|
|
T34 |
7 |
|
T36 |
7 |
|
T274 |
3 |
| auto[0] |
auto[1] |
68 |
1 |
|
|
T34 |
4 |
|
T36 |
2 |
|
T274 |
9 |
| auto[1] |
auto[0] |
62 |
1 |
|
|
T34 |
5 |
|
T36 |
4 |
|
T274 |
5 |
| auto[1] |
auto[1] |
75 |
1 |
|
|
T34 |
4 |
|
T36 |
7 |
|
T274 |
3 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
66 |
1 |
|
|
T34 |
4 |
|
T36 |
4 |
|
T274 |
6 |
| auto[0] |
auto[1] |
70 |
1 |
|
|
T34 |
4 |
|
T36 |
5 |
|
T274 |
3 |
| auto[1] |
auto[0] |
73 |
1 |
|
|
T34 |
4 |
|
T36 |
4 |
|
T274 |
7 |
| auto[1] |
auto[1] |
71 |
1 |
|
|
T34 |
8 |
|
T36 |
7 |
|
T274 |
4 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
59 |
1 |
|
|
T34 |
7 |
|
T36 |
5 |
|
T274 |
2 |
| auto[0] |
auto[1] |
75 |
1 |
|
|
T34 |
4 |
|
T36 |
6 |
|
T274 |
4 |
| auto[1] |
auto[0] |
68 |
1 |
|
|
T34 |
4 |
|
T36 |
3 |
|
T274 |
6 |
| auto[1] |
auto[1] |
78 |
1 |
|
|
T34 |
5 |
|
T36 |
6 |
|
T274 |
8 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
66 |
1 |
|
|
T34 |
8 |
|
T36 |
3 |
|
T274 |
5 |
| auto[0] |
auto[1] |
81 |
1 |
|
|
T34 |
5 |
|
T36 |
6 |
|
T274 |
6 |
| auto[1] |
auto[0] |
63 |
1 |
|
|
T34 |
2 |
|
T36 |
8 |
|
T274 |
4 |
| auto[1] |
auto[1] |
70 |
1 |
|
|
T34 |
5 |
|
T36 |
3 |
|
T274 |
5 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
59 |
1 |
|
|
T34 |
6 |
|
T36 |
3 |
|
T274 |
3 |
| auto[0] |
auto[1] |
66 |
1 |
|
|
T34 |
1 |
|
T36 |
7 |
|
T274 |
5 |
| auto[1] |
auto[0] |
78 |
1 |
|
|
T34 |
6 |
|
T36 |
7 |
|
T274 |
5 |
| auto[1] |
auto[1] |
77 |
1 |
|
|
T34 |
7 |
|
T36 |
3 |
|
T274 |
7 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
73 |
1 |
|
|
T34 |
7 |
|
T36 |
3 |
|
T274 |
7 |
| auto[0] |
auto[1] |
78 |
1 |
|
|
T34 |
7 |
|
T36 |
3 |
|
T274 |
7 |
| auto[1] |
auto[0] |
52 |
1 |
|
|
T34 |
4 |
|
T36 |
5 |
|
T274 |
3 |
| auto[1] |
auto[1] |
77 |
1 |
|
|
T34 |
2 |
|
T36 |
9 |
|
T274 |
3 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
136 |
1 |
|
|
T34 |
11 |
|
T36 |
12 |
|
T274 |
10 |
| auto[1] |
auto[1] |
144 |
1 |
|
|
T34 |
9 |
|
T36 |
8 |
|
T274 |
10 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
69 |
1 |
|
|
T34 |
2 |
|
T36 |
10 |
|
T274 |
4 |
| auto[0] |
auto[1] |
79 |
1 |
|
|
T34 |
7 |
|
T36 |
4 |
|
T274 |
6 |
| auto[1] |
auto[0] |
67 |
1 |
|
|
T34 |
9 |
|
T36 |
3 |
|
T274 |
3 |
| auto[1] |
auto[1] |
65 |
1 |
|
|
T34 |
2 |
|
T36 |
3 |
|
T274 |
7 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
135 |
1 |
|
|
T34 |
11 |
|
T36 |
12 |
|
T274 |
13 |
| auto[1] |
auto[1] |
145 |
1 |
|
|
T34 |
9 |
|
T36 |
8 |
|
T274 |
7 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
75 |
1 |
|
|
T157 |
14 |
|
T180 |
9 |
|
T141 |
13 |
| auto[1] |
65 |
1 |
|
|
T157 |
6 |
|
T180 |
11 |
|
T141 |
7 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
64 |
1 |
|
|
T157 |
12 |
|
T180 |
10 |
|
T141 |
7 |
| auto[1] |
76 |
1 |
|
|
T157 |
8 |
|
T180 |
10 |
|
T141 |
13 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
68 |
1 |
|
|
T157 |
6 |
|
T180 |
10 |
|
T141 |
10 |
| auto[1] |
72 |
1 |
|
|
T157 |
14 |
|
T180 |
10 |
|
T141 |
10 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
75 |
1 |
|
|
T157 |
10 |
|
T180 |
15 |
|
T141 |
11 |
| auto[1] |
65 |
1 |
|
|
T157 |
10 |
|
T180 |
5 |
|
T141 |
9 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
70 |
1 |
|
|
T157 |
11 |
|
T180 |
9 |
|
T141 |
11 |
| auto[1] |
70 |
1 |
|
|
T157 |
9 |
|
T180 |
11 |
|
T141 |
9 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
72 |
1 |
|
|
T157 |
10 |
|
T180 |
8 |
|
T141 |
14 |
| auto[1] |
68 |
1 |
|
|
T157 |
10 |
|
T180 |
12 |
|
T141 |
6 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
61 |
1 |
|
|
T157 |
11 |
|
T180 |
9 |
|
T141 |
3 |
| auto[1] |
79 |
1 |
|
|
T157 |
9 |
|
T180 |
11 |
|
T141 |
17 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
68 |
1 |
|
|
T157 |
9 |
|
T180 |
8 |
|
T141 |
11 |
| auto[1] |
72 |
1 |
|
|
T157 |
11 |
|
T180 |
12 |
|
T141 |
9 |