Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.89 99.37 96.71 100.00 96.79 98.85 99.42 94.05


Total tests in report: 908
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
66.58 66.58 82.46 82.46 73.23 73.23 94.29 94.29 31.41 31.41 84.36 84.36 71.58 71.58 28.69 28.69 /workspace/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.471335777
74.39 7.81 89.85 7.39 82.84 9.61 96.12 1.83 44.23 12.82 90.24 5.88 81.31 9.73 36.12 7.43 /workspace/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.64057311
80.13 5.74 92.70 2.86 86.22 3.39 96.35 0.23 71.15 26.92 93.23 2.99 84.87 3.56 36.37 0.25 /workspace/coverage/default/0.sysrst_ctrl_feature_disable.1211214908
83.80 3.67 92.82 0.11 86.27 0.05 96.35 0.00 72.44 1.28 93.38 0.15 85.07 0.19 60.31 23.93 /workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.801464072
87.37 3.56 95.15 2.33 89.41 3.13 96.80 0.46 76.28 3.85 95.42 2.03 90.37 5.30 68.14 7.83 /workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.1140216598
89.98 2.62 96.49 1.34 90.87 1.47 96.80 0.00 85.26 8.97 96.30 0.89 93.55 3.18 70.61 2.48 /workspace/coverage/default/49.sysrst_ctrl_stress_all.73160168
91.80 1.82 98.06 1.57 92.95 2.07 97.49 0.68 89.10 3.85 97.45 1.15 96.72 3.18 70.86 0.25 /workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.458597528
93.10 1.30 98.38 0.32 93.28 0.33 97.49 0.00 91.03 1.92 97.74 0.30 97.59 0.87 76.21 5.35 /workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.1703315679
94.24 1.14 98.45 0.07 94.51 1.24 98.17 0.68 91.03 0.00 97.86 0.11 97.59 0.00 82.06 5.85 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.3371952678
94.80 0.56 98.54 0.09 94.57 0.05 98.17 0.00 91.67 0.64 97.97 0.11 97.78 0.19 84.89 2.82 /workspace/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.1767205274
95.16 0.36 98.66 0.11 94.97 0.40 98.17 0.00 93.59 1.92 98.08 0.11 97.78 0.00 84.89 0.00 /workspace/coverage/default/1.sysrst_ctrl_feature_disable.2526566762
95.51 0.35 98.77 0.11 95.07 0.10 98.17 0.00 94.87 1.28 98.23 0.15 98.07 0.29 85.38 0.50 /workspace/coverage/default/26.sysrst_ctrl_stress_all.1600323077
95.78 0.27 98.86 0.09 95.07 0.00 98.17 0.00 94.87 0.00 98.23 0.00 98.07 0.00 87.17 1.78 /workspace/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.1122076697
96.01 0.24 98.92 0.06 95.15 0.08 99.54 1.37 94.87 0.00 98.23 0.00 98.07 0.00 87.31 0.15 /workspace/coverage/default/1.sysrst_ctrl_alert_test.2104986566
96.22 0.20 98.97 0.06 95.20 0.05 99.54 0.00 95.51 0.64 98.30 0.07 98.17 0.10 87.81 0.50 /workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.2402919289
96.37 0.15 98.97 0.00 96.16 0.96 99.54 0.00 95.51 0.00 98.30 0.00 98.17 0.00 87.91 0.10 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.2406653084
96.51 0.14 99.01 0.04 96.18 0.03 99.54 0.00 96.15 0.64 98.34 0.04 98.27 0.10 88.06 0.15 /workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.3596411857
96.64 0.14 99.09 0.07 96.21 0.03 99.54 0.00 96.79 0.64 98.45 0.11 98.36 0.10 88.06 0.00 /workspace/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.1402870906
96.77 0.13 99.09 0.00 96.21 0.00 99.54 0.00 96.79 0.00 98.45 0.00 99.13 0.77 88.21 0.15 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.1086099692
96.90 0.13 99.14 0.06 96.21 0.00 99.54 0.00 96.79 0.00 98.45 0.00 99.13 0.00 89.05 0.84 /workspace/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.4106613967
97.02 0.12 99.14 0.00 96.21 0.00 99.54 0.00 96.79 0.00 98.45 0.00 99.13 0.00 89.89 0.84 /workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.1016431201
97.12 0.10 99.14 0.00 96.23 0.03 100.00 0.46 96.79 0.00 98.45 0.00 99.23 0.10 89.99 0.10 /workspace/coverage/default/0.sysrst_ctrl_sec_cm.2301997309
97.21 0.09 99.16 0.02 96.23 0.00 100.00 0.00 96.79 0.00 98.45 0.00 99.23 0.00 90.63 0.64 /workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.3589452543
97.31 0.09 99.18 0.02 96.23 0.00 100.00 0.00 96.79 0.00 98.48 0.04 99.23 0.00 91.23 0.59 /workspace/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.849240044
97.38 0.07 99.18 0.00 96.23 0.00 100.00 0.00 96.79 0.00 98.48 0.00 99.23 0.00 91.72 0.50 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.3192939854
97.43 0.05 99.22 0.04 96.49 0.25 100.00 0.00 96.79 0.00 98.56 0.07 99.23 0.00 91.72 0.00 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.3011650713
97.48 0.05 99.22 0.00 96.49 0.00 100.00 0.00 96.79 0.00 98.56 0.00 99.23 0.00 92.07 0.35 /workspace/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.4017957660
97.52 0.04 99.22 0.00 96.49 0.00 100.00 0.00 96.79 0.00 98.56 0.00 99.23 0.00 92.37 0.30 /workspace/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.1726819374
97.56 0.04 99.22 0.00 96.49 0.00 100.00 0.00 96.79 0.00 98.56 0.00 99.23 0.00 92.67 0.30 /workspace/coverage/default/7.sysrst_ctrl_combo_detect.3200996148
97.59 0.02 99.22 0.00 96.49 0.00 100.00 0.00 96.79 0.00 98.56 0.00 99.23 0.00 92.81 0.15 /workspace/coverage/default/1.sysrst_ctrl_combo_detect.3387025169
97.61 0.02 99.22 0.00 96.49 0.00 100.00 0.00 96.79 0.00 98.56 0.00 99.23 0.00 92.96 0.15 /workspace/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.2881914668
97.63 0.02 99.22 0.00 96.49 0.00 100.00 0.00 96.79 0.00 98.56 0.00 99.23 0.00 93.11 0.15 /workspace/coverage/default/30.sysrst_ctrl_pin_override_test.3190939582
97.65 0.02 99.22 0.00 96.49 0.00 100.00 0.00 96.79 0.00 98.56 0.00 99.23 0.00 93.26 0.15 /workspace/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.777105239
97.67 0.02 99.22 0.00 96.49 0.00 100.00 0.00 96.79 0.00 98.56 0.00 99.23 0.00 93.41 0.15 /workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.915477604
97.69 0.02 99.22 0.00 96.51 0.03 100.00 0.00 96.79 0.00 98.56 0.00 99.33 0.10 93.41 0.00 /workspace/coverage/default/47.sysrst_ctrl_edge_detect.2782630760
97.71 0.02 99.22 0.00 96.54 0.03 100.00 0.00 96.79 0.00 98.56 0.00 99.42 0.10 93.41 0.00 /workspace/coverage/default/9.sysrst_ctrl_edge_detect.3250871370
97.72 0.02 99.25 0.04 96.54 0.00 100.00 0.00 96.79 0.00 98.63 0.07 99.42 0.00 93.41 0.00 /workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.2091608289
97.74 0.02 99.29 0.04 96.54 0.00 100.00 0.00 96.79 0.00 98.71 0.07 99.42 0.00 93.41 0.00 /workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.710456806
97.75 0.01 99.29 0.00 96.54 0.00 100.00 0.00 96.79 0.00 98.71 0.00 99.42 0.00 93.51 0.10 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.2095527871
97.77 0.01 99.29 0.00 96.54 0.00 100.00 0.00 96.79 0.00 98.71 0.00 99.42 0.00 93.61 0.10 /workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.1008739222
97.78 0.01 99.29 0.00 96.54 0.00 100.00 0.00 96.79 0.00 98.71 0.00 99.42 0.00 93.71 0.10 /workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.1796673980
97.79 0.01 99.29 0.00 96.61 0.08 100.00 0.00 96.79 0.00 98.71 0.00 99.42 0.00 93.71 0.00 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.3932912237
97.80 0.01 99.31 0.02 96.61 0.00 100.00 0.00 96.79 0.00 98.74 0.04 99.42 0.00 93.71 0.00 /workspace/coverage/default/15.sysrst_ctrl_stress_all.1512832220
97.81 0.01 99.33 0.02 96.61 0.00 100.00 0.00 96.79 0.00 98.78 0.04 99.42 0.00 93.71 0.00 /workspace/coverage/default/23.sysrst_ctrl_edge_detect.3325104460
97.81 0.01 99.35 0.02 96.61 0.00 100.00 0.00 96.79 0.00 98.82 0.04 99.42 0.00 93.71 0.00 /workspace/coverage/default/44.sysrst_ctrl_edge_detect.1778590504
97.82 0.01 99.37 0.02 96.61 0.00 100.00 0.00 96.79 0.00 98.85 0.04 99.42 0.00 93.71 0.00 /workspace/coverage/default/46.sysrst_ctrl_edge_detect.2977822842
97.83 0.01 99.37 0.00 96.61 0.00 100.00 0.00 96.79 0.00 98.85 0.00 99.42 0.00 93.76 0.05 /workspace/coverage/default/12.sysrst_ctrl_stress_all.1226898963
97.84 0.01 99.37 0.00 96.61 0.00 100.00 0.00 96.79 0.00 98.85 0.00 99.42 0.00 93.81 0.05 /workspace/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.3468024186
97.84 0.01 99.37 0.00 96.61 0.00 100.00 0.00 96.79 0.00 98.85 0.00 99.42 0.00 93.86 0.05 /workspace/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.2939788441
97.85 0.01 99.37 0.00 96.61 0.00 100.00 0.00 96.79 0.00 98.85 0.00 99.42 0.00 93.90 0.05 /workspace/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.1997628306
97.86 0.01 99.37 0.00 96.61 0.00 100.00 0.00 96.79 0.00 98.85 0.00 99.42 0.00 93.95 0.05 /workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.558933232
97.86 0.01 99.37 0.00 96.61 0.00 100.00 0.00 96.79 0.00 98.85 0.00 99.42 0.00 94.00 0.05 /workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.1250954466
97.87 0.01 99.37 0.00 96.61 0.00 100.00 0.00 96.79 0.00 98.85 0.00 99.42 0.00 94.05 0.05 /workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.2524946930
97.88 0.01 99.37 0.00 96.64 0.03 100.00 0.00 96.79 0.00 98.85 0.00 99.42 0.00 94.05 0.00 /workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.5322290
97.88 0.01 99.37 0.00 96.66 0.03 100.00 0.00 96.79 0.00 98.85 0.00 99.42 0.00 94.05 0.00 /workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.4201025688
97.88 0.01 99.37 0.00 96.69 0.03 100.00 0.00 96.79 0.00 98.85 0.00 99.42 0.00 94.05 0.00 /workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.1516368370

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.163224990
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.2983430264
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.3587347321
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.2206671800
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.2970906508
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.1803385289
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.425504580
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.2135714818
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.168402852
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.2986191451
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.846073598
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.2091186604
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.1866546914
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.2631911993
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.987384086
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.2650431665
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.4266958174
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.2288572757
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.3799700838
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.3381590184
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.2716655627
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.2350502352
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.1978918179
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.1419497156
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.402841503
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.443881738
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.2695193246
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.137589404
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.96901609
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.2358786724
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.2081657114
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.1837804137
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.4111808756
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.1947398132
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.529282236
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.2693595993
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.2748371198
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.1603288624
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.928749617
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.1999909887
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.1568484220
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.2270174280
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.232480243
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.3383321723
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.3534658492
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.3639197064
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.60479595
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.312859312
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.3988919954
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.4062164539
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.3356103675
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.3294296257
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.1785121041
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.3418199787
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.683555476
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.358418724
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.2170936126
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.875787545
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.3795568200
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.3156399612
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.218842467
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.3722714822
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.2933016894
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.2663028475
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.3547102229
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.518896687
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.860317173
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.4263915300
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.4060480102
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.1809361263
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.1773461334
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.1590971083
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.2318129754
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.710662394
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.3197088124
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.1243325199
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.1916453785
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.3760559015
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.67229018
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.686873158
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.4176524613
/workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.1545375806
/workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.3708716665
/workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.4050757789
/workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.3462853094
/workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.3719001060
/workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.3692054334
/workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.3085475740
/workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.481882763
/workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.1921419836
/workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.714099173
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.551022111
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.4156899342
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.3510413283
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.1734347283
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.569931306
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.3934615458
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.3953533807
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.1760936318
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.3543177361
/workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.3403896094
/workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.2257148664
/workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.3675450710
/workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.4177685108
/workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.335053987
/workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.1507585064
/workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.400307921
/workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.2676299791
/workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.852632608
/workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.2497303030
/workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.578542237
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/workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.2658716603
/workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.3873530699
/workspace/coverage/default/43.sysrst_ctrl_pin_access_test.1095730029
/workspace/coverage/default/43.sysrst_ctrl_pin_override_test.2042939908
/workspace/coverage/default/43.sysrst_ctrl_smoke.2392624120
/workspace/coverage/default/43.sysrst_ctrl_stress_all.3205074887
/workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.3055328018
/workspace/coverage/default/44.sysrst_ctrl_alert_test.752385169
/workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.3788875534
/workspace/coverage/default/44.sysrst_ctrl_combo_detect.808458921
/workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.1780295506
/workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.1384005617
/workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.4187777644
/workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.3308144516
/workspace/coverage/default/44.sysrst_ctrl_pin_access_test.4020671491
/workspace/coverage/default/44.sysrst_ctrl_pin_override_test.3331576857
/workspace/coverage/default/44.sysrst_ctrl_smoke.1264702164
/workspace/coverage/default/44.sysrst_ctrl_stress_all.2084115933
/workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.3185788383
/workspace/coverage/default/45.sysrst_ctrl_alert_test.2706722587
/workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.3741931243
/workspace/coverage/default/45.sysrst_ctrl_combo_detect.3372133503
/workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.1999025912
/workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.648509968
/workspace/coverage/default/45.sysrst_ctrl_edge_detect.629256187
/workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.4129929971
/workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.3998147529
/workspace/coverage/default/45.sysrst_ctrl_pin_access_test.4226792733
/workspace/coverage/default/45.sysrst_ctrl_pin_override_test.3333268745
/workspace/coverage/default/45.sysrst_ctrl_smoke.685462561
/workspace/coverage/default/45.sysrst_ctrl_stress_all.249983406
/workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.4202262087
/workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.2525699147
/workspace/coverage/default/46.sysrst_ctrl_alert_test.498248674
/workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.977019416
/workspace/coverage/default/46.sysrst_ctrl_combo_detect.4036927542
/workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.2459989972
/workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.2271359347
/workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.2624148581
/workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.3262288806
/workspace/coverage/default/46.sysrst_ctrl_pin_access_test.1989505322
/workspace/coverage/default/46.sysrst_ctrl_pin_override_test.2434658823
/workspace/coverage/default/46.sysrst_ctrl_smoke.34735350
/workspace/coverage/default/46.sysrst_ctrl_stress_all.3329501073
/workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.3237059268
/workspace/coverage/default/47.sysrst_ctrl_alert_test.1876025430
/workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.3763246096
/workspace/coverage/default/47.sysrst_ctrl_combo_detect.3466949262
/workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.1230008518
/workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.2479831703
/workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.2314689767
/workspace/coverage/default/47.sysrst_ctrl_pin_access_test.3023991020
/workspace/coverage/default/47.sysrst_ctrl_pin_override_test.1185506731
/workspace/coverage/default/47.sysrst_ctrl_smoke.1930809728
/workspace/coverage/default/47.sysrst_ctrl_stress_all.3512616332
/workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.1142733688
/workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.1898781650
/workspace/coverage/default/48.sysrst_ctrl_alert_test.638411328
/workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.1850727137
/workspace/coverage/default/48.sysrst_ctrl_combo_detect.951328538
/workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.3633197962
/workspace/coverage/default/48.sysrst_ctrl_edge_detect.3501193338
/workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.3171205680
/workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.651215538
/workspace/coverage/default/48.sysrst_ctrl_pin_access_test.485598245
/workspace/coverage/default/48.sysrst_ctrl_pin_override_test.3239451085
/workspace/coverage/default/48.sysrst_ctrl_smoke.320692526
/workspace/coverage/default/48.sysrst_ctrl_stress_all.3435098189
/workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.3515747295
/workspace/coverage/default/49.sysrst_ctrl_alert_test.2646213210
/workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.1427751367
/workspace/coverage/default/49.sysrst_ctrl_combo_detect.1865320528
/workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.1799334186
/workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.1420150911
/workspace/coverage/default/49.sysrst_ctrl_edge_detect.329152124
/workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.3417191958
/workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.627507371
/workspace/coverage/default/49.sysrst_ctrl_pin_access_test.480284715
/workspace/coverage/default/49.sysrst_ctrl_pin_override_test.1027218058
/workspace/coverage/default/49.sysrst_ctrl_smoke.3250425851
/workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.3836258771
/workspace/coverage/default/5.sysrst_ctrl_alert_test.2856744199
/workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.412137491
/workspace/coverage/default/5.sysrst_ctrl_combo_detect.65824527
/workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.1381100419
/workspace/coverage/default/5.sysrst_ctrl_edge_detect.2071467580
/workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.1656973425
/workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.3435500366
/workspace/coverage/default/5.sysrst_ctrl_pin_access_test.2295253251
/workspace/coverage/default/5.sysrst_ctrl_pin_override_test.1195324788
/workspace/coverage/default/5.sysrst_ctrl_smoke.1842448640
/workspace/coverage/default/5.sysrst_ctrl_stress_all.912656460
/workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.2361877586
/workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.2336076480
/workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.2192066425
/workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.2219106413
/workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.4174396239
/workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.34137104
/workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.2567652120
/workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.2164121702
/workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.3062579738
/workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.76533970
/workspace/coverage/default/6.sysrst_ctrl_alert_test.2044481409
/workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.1244867046
/workspace/coverage/default/6.sysrst_ctrl_combo_detect.471644934
/workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.1906709239
/workspace/coverage/default/6.sysrst_ctrl_edge_detect.107600677
/workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.2513154935
/workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.1222891868
/workspace/coverage/default/6.sysrst_ctrl_pin_access_test.4007384681
/workspace/coverage/default/6.sysrst_ctrl_pin_override_test.1180634612
/workspace/coverage/default/6.sysrst_ctrl_smoke.4117966045
/workspace/coverage/default/6.sysrst_ctrl_stress_all.625088788
/workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.792573466
/workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.2083660169
/workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.568685043
/workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.987135505
/workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.3490938
/workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.1273720926
/workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.2840142106
/workspace/coverage/default/7.sysrst_ctrl_alert_test.2752676658
/workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.3263916950
/workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.3840305919
/workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.500878815
/workspace/coverage/default/7.sysrst_ctrl_edge_detect.2658344643
/workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.923831238
/workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.794811285
/workspace/coverage/default/7.sysrst_ctrl_pin_access_test.649304783
/workspace/coverage/default/7.sysrst_ctrl_pin_override_test.303690269
/workspace/coverage/default/7.sysrst_ctrl_smoke.1031548849
/workspace/coverage/default/7.sysrst_ctrl_stress_all.4293872293
/workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.1262860910
/workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.2537860703
/workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.80008801
/workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.3102731594
/workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.3184810410
/workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.516329124
/workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.2583663201
/workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.1940205952
/workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.4164124618
/workspace/coverage/default/8.sysrst_ctrl_alert_test.1285091832
/workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.1152065225
/workspace/coverage/default/8.sysrst_ctrl_combo_detect.1583573735
/workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.4149335197
/workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.1523431964
/workspace/coverage/default/8.sysrst_ctrl_edge_detect.598020860
/workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.928128698
/workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.719687532
/workspace/coverage/default/8.sysrst_ctrl_pin_access_test.2875683451
/workspace/coverage/default/8.sysrst_ctrl_pin_override_test.3007829650
/workspace/coverage/default/8.sysrst_ctrl_smoke.2506487015
/workspace/coverage/default/8.sysrst_ctrl_stress_all.3425499549
/workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.4130756467
/workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.130818829
/workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.1179348595
/workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.3540596006
/workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.3326994283
/workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.1184017198
/workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.388031390
/workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.3015288455
/workspace/coverage/default/9.sysrst_ctrl_alert_test.1056645517
/workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.2309583285
/workspace/coverage/default/9.sysrst_ctrl_combo_detect.2083552208
/workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.2393709364
/workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.2058361384
/workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.1575413538
/workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.1209317199
/workspace/coverage/default/9.sysrst_ctrl_pin_access_test.1953213267
/workspace/coverage/default/9.sysrst_ctrl_pin_override_test.2746045421
/workspace/coverage/default/9.sysrst_ctrl_smoke.1251619729
/workspace/coverage/default/9.sysrst_ctrl_stress_all.2726689477
/workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.1408362665
/workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.2538220963
/workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.3120776198
/workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.1731742249
/workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.627982692
/workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.2830984323
/workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.878469671
/workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.290872547
/workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.3766224949
/workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.3967478681
/workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.3783942511



Total test records in report: 908
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T4 /workspace/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.974637620 Apr 02 01:04:42 PM PDT 24 Apr 02 01:06:42 PM PDT 24 46762400103 ps
T5 /workspace/coverage/default/17.sysrst_ctrl_alert_test.1062004209 Apr 02 01:03:47 PM PDT 24 Apr 02 01:03:50 PM PDT 24 2034253105 ps
T6 /workspace/coverage/default/21.sysrst_ctrl_in_out_inverted.3132346032 Apr 02 01:03:56 PM PDT 24 Apr 02 01:03:59 PM PDT 24 2503659615 ps
T19 /workspace/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.3653632445 Apr 02 01:04:46 PM PDT 24 Apr 02 01:04:54 PM PDT 24 2609992968 ps
T20 /workspace/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.908541955 Apr 02 01:03:54 PM PDT 24 Apr 02 01:03:57 PM PDT 24 3213616524 ps
T1 /workspace/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.471335777 Apr 02 01:03:52 PM PDT 24 Apr 02 01:07:34 PM PDT 24 87049469633 ps
T14 /workspace/coverage/default/16.sysrst_ctrl_alert_test.3794189525 Apr 02 01:03:43 PM PDT 24 Apr 02 01:03:49 PM PDT 24 2010948368 ps
T15 /workspace/coverage/default/13.sysrst_ctrl_alert_test.4180679624 Apr 02 01:03:32 PM PDT 24 Apr 02 01:03:34 PM PDT 24 2027785885 ps
T2 /workspace/coverage/default/48.sysrst_ctrl_edge_detect.3501193338 Apr 02 01:05:36 PM PDT 24 Apr 02 01:05:39 PM PDT 24 2626377334 ps
T16 /workspace/coverage/default/39.sysrst_ctrl_alert_test.330388907 Apr 02 01:05:07 PM PDT 24 Apr 02 01:05:09 PM PDT 24 2040509551 ps
T3 /workspace/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.1767205274 Apr 02 01:04:22 PM PDT 24 Apr 02 01:06:59 PM PDT 24 208566788872 ps
T7 /workspace/coverage/default/12.sysrst_ctrl_ultra_low_pwr.2201937857 Apr 02 01:03:22 PM PDT 24 Apr 02 01:03:24 PM PDT 24 7744058903 ps
T8 /workspace/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.64057311 Apr 02 01:04:09 PM PDT 24 Apr 02 01:05:44 PM PDT 24 136919410656 ps
T17 /workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.2479831703 Apr 02 01:05:30 PM PDT 24 Apr 02 01:05:38 PM PDT 24 2612327532 ps
T18 /workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.1427751367 Apr 02 01:05:39 PM PDT 24 Apr 02 01:18:41 PM PDT 24 307690607566 ps
T52 /workspace/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.1218002971 Apr 02 01:04:24 PM PDT 24 Apr 02 01:04:32 PM PDT 24 2611236455 ps
T9 /workspace/coverage/default/17.sysrst_ctrl_combo_detect.318917690 Apr 02 01:03:47 PM PDT 24 Apr 02 01:05:11 PM PDT 24 119504741817 ps
T25 /workspace/coverage/default/31.sysrst_ctrl_in_out_inverted.1180831967 Apr 02 01:04:34 PM PDT 24 Apr 02 01:04:40 PM PDT 24 2431036084 ps
T53 /workspace/coverage/default/35.sysrst_ctrl_pin_override_test.1842859653 Apr 02 01:05:01 PM PDT 24 Apr 02 01:05:04 PM PDT 24 2533590176 ps
T10 /workspace/coverage/default/30.sysrst_ctrl_edge_detect.3266636816 Apr 02 01:04:37 PM PDT 24 Apr 02 01:04:43 PM PDT 24 3322343517 ps
T54 /workspace/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.1330484564 Apr 02 01:03:26 PM PDT 24 Apr 02 01:03:33 PM PDT 24 2612634927 ps
T57 /workspace/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.3989805639 Apr 02 01:03:44 PM PDT 24 Apr 02 01:03:52 PM PDT 24 3037292566 ps
T11 /workspace/coverage/default/5.sysrst_ctrl_combo_detect.65824527 Apr 02 01:02:59 PM PDT 24 Apr 02 01:04:07 PM PDT 24 97906877489 ps
T12 /workspace/coverage/default/20.sysrst_ctrl_ultra_low_pwr.415617415 Apr 02 01:03:57 PM PDT 24 Apr 02 01:04:05 PM PDT 24 4514913721 ps
T13 /workspace/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.4106613967 Apr 02 01:04:51 PM PDT 24 Apr 02 01:05:43 PM PDT 24 85653546365 ps
T253 /workspace/coverage/default/21.sysrst_ctrl_smoke.1580027447 Apr 02 01:03:53 PM PDT 24 Apr 02 01:03:59 PM PDT 24 2110332409 ps
T69 /workspace/coverage/default/6.sysrst_ctrl_pin_override_test.1180634612 Apr 02 01:03:07 PM PDT 24 Apr 02 01:03:14 PM PDT 24 2510596532 ps
T24 /workspace/coverage/default/19.sysrst_ctrl_ultra_low_pwr.679264577 Apr 02 01:03:48 PM PDT 24 Apr 02 01:03:51 PM PDT 24 5575470694 ps
T43 /workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.3741931243 Apr 02 01:05:22 PM PDT 24 Apr 02 01:05:24 PM PDT 24 3454530424 ps
T135 /workspace/coverage/default/8.sysrst_ctrl_alert_test.1285091832 Apr 02 01:03:16 PM PDT 24 Apr 02 01:03:22 PM PDT 24 2011768367 ps
T44 /workspace/coverage/default/1.sysrst_ctrl_auto_blk_key_output.1552561028 Apr 02 01:02:37 PM PDT 24 Apr 02 01:02:46 PM PDT 24 3136464893 ps
T70 /workspace/coverage/default/40.sysrst_ctrl_pin_override_test.1834834111 Apr 02 01:05:15 PM PDT 24 Apr 02 01:05:17 PM PDT 24 2529687214 ps
T136 /workspace/coverage/default/47.sysrst_ctrl_pin_override_test.1185506731 Apr 02 01:05:29 PM PDT 24 Apr 02 01:05:33 PM PDT 24 2518878128 ps
T63 /workspace/coverage/default/41.sysrst_ctrl_stress_all.2610257940 Apr 02 01:05:12 PM PDT 24 Apr 02 01:05:32 PM PDT 24 7088975327 ps
T45 /workspace/coverage/default/39.sysrst_ctrl_combo_detect.4251244810 Apr 02 01:05:02 PM PDT 24 Apr 02 01:11:47 PM PDT 24 161477728293 ps
T26 /workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.3184810410 Apr 02 01:05:49 PM PDT 24 Apr 02 01:07:07 PM PDT 24 113500875313 ps
T46 /workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.2164121702 Apr 02 01:05:43 PM PDT 24 Apr 02 01:07:10 PM PDT 24 32331787120 ps
T116 /workspace/coverage/default/30.sysrst_ctrl_pin_override_test.3190939582 Apr 02 01:04:35 PM PDT 24 Apr 02 01:04:40 PM PDT 24 2516335938 ps
T117 /workspace/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.1090265615 Apr 02 01:02:31 PM PDT 24 Apr 02 01:02:32 PM PDT 24 2798694071 ps
T64 /workspace/coverage/default/35.sysrst_ctrl_stress_all.2846396345 Apr 02 01:04:51 PM PDT 24 Apr 02 01:05:19 PM PDT 24 12340109645 ps
T118 /workspace/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.1682447627 Apr 02 01:05:01 PM PDT 24 Apr 02 01:05:03 PM PDT 24 2679263576 ps
T119 /workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.4129929971 Apr 02 01:05:24 PM PDT 24 Apr 02 01:05:32 PM PDT 24 2611350514 ps
T58 /workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.2083660169 Apr 02 01:03:04 PM PDT 24 Apr 02 01:03:48 PM PDT 24 1562861282815 ps
T56 /workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.458597528 Apr 02 01:05:25 PM PDT 24 Apr 02 01:10:36 PM PDT 24 3881373248967 ps
T120 /workspace/coverage/default/48.sysrst_ctrl_smoke.320692526 Apr 02 01:05:28 PM PDT 24 Apr 02 01:05:34 PM PDT 24 2111590251 ps
T65 /workspace/coverage/default/4.sysrst_ctrl_in_out_inverted.4156580916 Apr 02 01:02:46 PM PDT 24 Apr 02 01:02:54 PM PDT 24 2463993679 ps
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T30 /workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.5322290 Apr 02 01:05:41 PM PDT 24 Apr 02 01:07:15 PM PDT 24 35067159186 ps
T59 /workspace/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.374331945 Apr 02 01:04:38 PM PDT 24 Apr 02 01:05:27 PM PDT 24 18239178629 ps
T47 /workspace/coverage/default/28.sysrst_ctrl_auto_blk_key_output.2974741496 Apr 02 01:04:23 PM PDT 24 Apr 02 01:04:26 PM PDT 24 3537843473 ps
T152 /workspace/coverage/default/27.sysrst_ctrl_pin_access_test.141193267 Apr 02 01:04:25 PM PDT 24 Apr 02 01:04:28 PM PDT 24 2210789390 ps
T32 /workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.2538220963 Apr 02 01:05:49 PM PDT 24 Apr 02 01:09:59 PM PDT 24 90545353020 ps
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T48 /workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.3062579738 Apr 02 01:05:46 PM PDT 24 Apr 02 01:06:05 PM PDT 24 25097763839 ps
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T60 /workspace/coverage/default/14.sysrst_ctrl_ultra_low_pwr.4241606797 Apr 02 01:03:29 PM PDT 24 Apr 02 01:03:31 PM PDT 24 6543092212 ps
T49 /workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.2460836497 Apr 02 01:05:17 PM PDT 24 Apr 02 01:06:32 PM PDT 24 29334255170 ps
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T218 /workspace/coverage/default/37.sysrst_ctrl_pin_access_test.3623812427 Apr 02 01:04:59 PM PDT 24 Apr 02 01:05:03 PM PDT 24 2060715394 ps
T219 /workspace/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.1080713949 Apr 02 01:03:49 PM PDT 24 Apr 02 01:03:52 PM PDT 24 2633182170 ps
T40 /workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.4130756467 Apr 02 01:03:08 PM PDT 24 Apr 02 01:04:01 PM PDT 24 41272420676 ps
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T33 /workspace/coverage/default/49.sysrst_ctrl_stress_all.73160168 Apr 02 01:05:43 PM PDT 24 Apr 02 01:06:43 PM PDT 24 98112467191 ps
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T164 /workspace/coverage/default/2.sysrst_ctrl_ultra_low_pwr.3981983291 Apr 02 01:02:40 PM PDT 24 Apr 02 01:02:43 PM PDT 24 4509518084 ps
T353 /workspace/coverage/default/11.sysrst_ctrl_pin_access_test.3210851667 Apr 02 01:03:16 PM PDT 24 Apr 02 01:03:22 PM PDT 24 2071112161 ps
T72 /workspace/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.3766630946 Apr 02 01:04:17 PM PDT 24 Apr 02 01:04:57 PM PDT 24 61102064305 ps
T51 /workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.1152065225 Apr 02 01:03:09 PM PDT 24 Apr 02 01:03:19 PM PDT 24 3372228491 ps
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T106 /workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.2393709364 Apr 02 01:03:15 PM PDT 24 Apr 02 01:03:47 PM PDT 24 51082448288 ps
T355 /workspace/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.1769541597 Apr 02 01:04:41 PM PDT 24 Apr 02 01:04:45 PM PDT 24 2617624660 ps
T351 /workspace/coverage/default/44.sysrst_ctrl_pin_override_test.3331576857 Apr 02 01:05:19 PM PDT 24 Apr 02 01:05:22 PM PDT 24 2525029112 ps
T73 /workspace/coverage/default/11.sysrst_ctrl_ultra_low_pwr.1248468029 Apr 02 01:03:18 PM PDT 24 Apr 02 01:03:20 PM PDT 24 4728027239 ps
T143 /workspace/coverage/default/34.sysrst_ctrl_pin_override_test.1295440898 Apr 02 01:04:41 PM PDT 24 Apr 02 01:04:46 PM PDT 24 2519048362 ps
T121 /workspace/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.3697322781 Apr 02 01:02:34 PM PDT 24 Apr 02 01:06:26 PM PDT 24 79909942770 ps
T107 /workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.516329124 Apr 02 01:05:46 PM PDT 24 Apr 02 01:06:50 PM PDT 24 23577489581 ps
T144 /workspace/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.4029358203 Apr 02 01:02:43 PM PDT 24 Apr 02 01:03:40 PM PDT 24 81188754558 ps
T39 /workspace/coverage/default/28.sysrst_ctrl_edge_detect.2828991781 Apr 02 01:04:23 PM PDT 24 Apr 02 01:04:34 PM PDT 24 5197516358 ps
T74 /workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.3515747295 Apr 02 01:05:33 PM PDT 24 Apr 02 01:05:42 PM PDT 24 5475522526 ps
T122 /workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.2830984323 Apr 02 01:05:53 PM PDT 24 Apr 02 01:06:25 PM PDT 24 45939146019 ps
T71 /workspace/coverage/default/19.sysrst_ctrl_stress_all.3752122982 Apr 02 01:03:56 PM PDT 24 Apr 02 01:04:19 PM PDT 24 18569963730 ps
T145 /workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.3171205680 Apr 02 01:05:31 PM PDT 24 Apr 02 01:05:34 PM PDT 24 2628940982 ps
T356 /workspace/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.2349731572 Apr 02 01:04:23 PM PDT 24 Apr 02 01:04:25 PM PDT 24 2674983582 ps
T357 /workspace/coverage/default/25.sysrst_ctrl_pin_override_test.2023722741 Apr 02 01:04:12 PM PDT 24 Apr 02 01:04:16 PM PDT 24 2520357682 ps
T75 /workspace/coverage/default/0.sysrst_ctrl_feature_disable.1211214908 Apr 02 01:02:31 PM PDT 24 Apr 02 01:02:38 PM PDT 24 41843878643 ps
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T41 /workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.1140216598 Apr 02 01:03:06 PM PDT 24 Apr 02 01:04:07 PM PDT 24 84802051303 ps
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T108 /workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.2192066425 Apr 02 01:05:41 PM PDT 24 Apr 02 01:09:28 PM PDT 24 83927499133 ps
T109 /workspace/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.3703206894 Apr 02 01:03:18 PM PDT 24 Apr 02 01:03:59 PM PDT 24 91773643809 ps
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T188 /workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.3417191958 Apr 02 01:05:39 PM PDT 24 Apr 02 01:05:48 PM PDT 24 2612587362 ps
T189 /workspace/coverage/default/3.sysrst_ctrl_combo_detect.1641163654 Apr 02 01:02:42 PM PDT 24 Apr 02 01:05:31 PM PDT 24 129938286208 ps
T105 /workspace/coverage/default/38.sysrst_ctrl_stress_all.567790840 Apr 02 01:05:06 PM PDT 24 Apr 02 01:08:39 PM PDT 24 874948641359 ps
T34 /workspace/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.849240044 Apr 02 01:03:42 PM PDT 24 Apr 02 01:04:27 PM PDT 24 69577669715 ps
T213 /workspace/coverage/default/49.sysrst_ctrl_smoke.3250425851 Apr 02 01:05:40 PM PDT 24 Apr 02 01:05:42 PM PDT 24 2132841570 ps
T214 /workspace/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.598253365 Apr 02 01:03:43 PM PDT 24 Apr 02 01:06:33 PM PDT 24 66769488996 ps
T99 /workspace/coverage/default/31.sysrst_ctrl_stress_all.3226543903 Apr 02 01:04:35 PM PDT 24 Apr 02 01:04:52 PM PDT 24 9144986267 ps
T215 /workspace/coverage/default/18.sysrst_ctrl_in_out_inverted.166503084 Apr 02 01:03:44 PM PDT 24 Apr 02 01:03:47 PM PDT 24 2477056918 ps
T216 /workspace/coverage/default/21.sysrst_ctrl_combo_detect.4162548780 Apr 02 01:04:00 PM PDT 24 Apr 02 01:04:15 PM PDT 24 75782244991 ps
T361 /workspace/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.2108689420 Apr 02 01:04:50 PM PDT 24 Apr 02 01:04:53 PM PDT 24 2694730181 ps
T238 /workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.2567652120 Apr 02 01:05:44 PM PDT 24 Apr 02 01:06:27 PM PDT 24 23338042428 ps
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T364 /workspace/coverage/default/1.sysrst_ctrl_alert_test.2104986566 Apr 02 01:02:36 PM PDT 24 Apr 02 01:02:40 PM PDT 24 2025560775 ps
T296 /workspace/coverage/default/29.sysrst_ctrl_auto_blk_key_output.3221898756 Apr 02 01:04:35 PM PDT 24 Apr 02 01:04:45 PM PDT 24 3394304883 ps
T365 /workspace/coverage/default/42.sysrst_ctrl_pin_override_test.56904452 Apr 02 01:05:15 PM PDT 24 Apr 02 01:05:17 PM PDT 24 2520682786 ps
T366 /workspace/coverage/default/3.sysrst_ctrl_auto_blk_key_output.124621101 Apr 02 01:02:47 PM PDT 24 Apr 02 01:02:52 PM PDT 24 3407683967 ps
T367 /workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.651215538 Apr 02 01:05:29 PM PDT 24 Apr 02 01:05:33 PM PDT 24 2482535582 ps
T271 /workspace/coverage/default/32.sysrst_ctrl_pin_override_test.3499646930 Apr 02 01:04:39 PM PDT 24 Apr 02 01:04:42 PM PDT 24 2541443525 ps
T272 /workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.346534288 Apr 02 01:05:11 PM PDT 24 Apr 02 01:05:17 PM PDT 24 4553695545 ps
T266 /workspace/coverage/default/22.sysrst_ctrl_auto_blk_key_output.2534092110 Apr 02 01:04:02 PM PDT 24 Apr 02 01:04:10 PM PDT 24 3041220762 ps
T190 /workspace/coverage/default/24.sysrst_ctrl_edge_detect.2545936255 Apr 02 01:04:12 PM PDT 24 Apr 02 01:04:17 PM PDT 24 2784570180 ps
T368 /workspace/coverage/default/45.sysrst_ctrl_alert_test.2706722587 Apr 02 01:05:23 PM PDT 24 Apr 02 01:05:24 PM PDT 24 2068323623 ps
T369 /workspace/coverage/default/32.sysrst_ctrl_smoke.652110939 Apr 02 01:04:35 PM PDT 24 Apr 02 01:04:39 PM PDT 24 2128372089 ps
T370 /workspace/coverage/default/10.sysrst_ctrl_pin_access_test.1495208362 Apr 02 01:03:14 PM PDT 24 Apr 02 01:03:16 PM PDT 24 2184882966 ps
T96 /workspace/coverage/default/9.sysrst_ctrl_edge_detect.3250871370 Apr 02 01:03:15 PM PDT 24 Apr 02 01:03:17 PM PDT 24 4037253847 ps
T203 /workspace/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.1122076697 Apr 02 01:03:16 PM PDT 24 Apr 02 01:04:50 PM PDT 24 128711396170 ps
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T205 /workspace/coverage/default/24.sysrst_ctrl_alert_test.605937733 Apr 02 01:04:13 PM PDT 24 Apr 02 01:04:19 PM PDT 24 2016672502 ps
T206 /workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.3263916950 Apr 02 01:03:17 PM PDT 24 Apr 02 01:03:19 PM PDT 24 3743152082 ps
T207 /workspace/coverage/default/3.sysrst_ctrl_smoke.2247752428 Apr 02 01:02:38 PM PDT 24 Apr 02 01:02:42 PM PDT 24 2115653737 ps
T208 /workspace/coverage/default/39.sysrst_ctrl_pin_access_test.2706717943 Apr 02 01:05:02 PM PDT 24 Apr 02 01:05:08 PM PDT 24 2083646376 ps
T36 /workspace/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.2952259606 Apr 02 01:03:26 PM PDT 24 Apr 02 01:03:49 PM PDT 24 36367154400 ps
T209 /workspace/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.1845524113 Apr 02 01:03:52 PM PDT 24 Apr 02 01:03:55 PM PDT 24 2637690764 ps
T210 /workspace/coverage/default/40.sysrst_ctrl_combo_detect.3425042051 Apr 02 01:05:08 PM PDT 24 Apr 02 01:07:05 PM PDT 24 193519264766 ps
T240 /workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.34137104 Apr 02 01:05:44 PM PDT 24 Apr 02 01:06:57 PM PDT 24 97344664261 ps
T126 /workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.2744393103 Apr 02 01:05:07 PM PDT 24 Apr 02 01:05:10 PM PDT 24 3301420942 ps
T182 /workspace/coverage/default/18.sysrst_ctrl_edge_detect.331349179 Apr 02 01:03:50 PM PDT 24 Apr 02 01:03:57 PM PDT 24 2375541284 ps
T237 /workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.568685043 Apr 02 01:05:44 PM PDT 24 Apr 02 01:06:18 PM PDT 24 54869483534 ps
T339 /workspace/coverage/default/20.sysrst_ctrl_stress_all.3516138224 Apr 02 01:03:54 PM PDT 24 Apr 02 01:04:14 PM PDT 24 15687189568 ps
T309 /workspace/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.3373258321 Apr 02 01:04:19 PM PDT 24 Apr 02 01:06:54 PM PDT 24 61287498696 ps
T371 /workspace/coverage/default/48.sysrst_ctrl_pin_override_test.3239451085 Apr 02 01:05:33 PM PDT 24 Apr 02 01:05:36 PM PDT 24 2534437148 ps
T273 /workspace/coverage/default/22.sysrst_ctrl_ultra_low_pwr.931776728 Apr 02 01:04:07 PM PDT 24 Apr 02 01:04:11 PM PDT 24 4770337689 ps
T372 /workspace/coverage/default/5.sysrst_ctrl_alert_test.2856744199 Apr 02 01:03:05 PM PDT 24 Apr 02 01:03:09 PM PDT 24 2022910560 ps
T149 /workspace/coverage/default/32.sysrst_ctrl_edge_detect.1591888741 Apr 02 01:04:47 PM PDT 24 Apr 02 01:04:51 PM PDT 24 5293690483 ps
T373 /workspace/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.2729860573 Apr 02 01:03:45 PM PDT 24 Apr 02 01:03:48 PM PDT 24 2636379341 ps
T374 /workspace/coverage/default/3.sysrst_ctrl_in_out_inverted.1747084766 Apr 02 01:02:38 PM PDT 24 Apr 02 01:02:40 PM PDT 24 2484606263 ps
T375 /workspace/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.3201981453 Apr 02 01:04:24 PM PDT 24 Apr 02 01:04:26 PM PDT 24 3648570494 ps
T376 /workspace/coverage/default/33.sysrst_ctrl_ultra_low_pwr.2997144184 Apr 02 01:04:43 PM PDT 24 Apr 02 01:04:47 PM PDT 24 2779205098 ps
T146 /workspace/coverage/default/5.sysrst_ctrl_edge_detect.2071467580 Apr 02 01:02:56 PM PDT 24 Apr 02 01:03:04 PM PDT 24 4031372133 ps
T377 /workspace/coverage/default/25.sysrst_ctrl_in_out_inverted.3515481749 Apr 02 01:04:14 PM PDT 24 Apr 02 01:04:22 PM PDT 24 2477496257 ps
T79 /workspace/coverage/default/2.sysrst_ctrl_sec_cm.2565448573 Apr 02 01:02:40 PM PDT 24 Apr 02 01:03:10 PM PDT 24 22017433428 ps
T259 /workspace/coverage/default/45.sysrst_ctrl_combo_detect.3372133503 Apr 02 01:05:21 PM PDT 24 Apr 02 01:06:58 PM PDT 24 151219710722 ps
T260 /workspace/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.813639488 Apr 02 01:04:07 PM PDT 24 Apr 02 01:04:10 PM PDT 24 3440225941 ps
T261 /workspace/coverage/default/23.sysrst_ctrl_auto_blk_key_output.2862733472 Apr 02 01:04:10 PM PDT 24 Apr 02 01:10:44 PM PDT 24 290748012753 ps
T100 /workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.1262860910 Apr 02 01:03:04 PM PDT 24 Apr 02 01:03:13 PM PDT 24 8425259190 ps
T262 /workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.928128698 Apr 02 01:03:05 PM PDT 24 Apr 02 01:03:07 PM PDT 24 2620965841 ps
T254 /workspace/coverage/default/41.sysrst_ctrl_combo_detect.673367614 Apr 02 01:05:12 PM PDT 24 Apr 02 01:08:08 PM PDT 24 73966669653 ps
T101 /workspace/coverage/default/2.sysrst_ctrl_edge_detect.1153123358 Apr 02 01:02:50 PM PDT 24 Apr 02 01:02:54 PM PDT 24 2500068127 ps
T263 /workspace/coverage/default/37.sysrst_ctrl_combo_detect.3960997520 Apr 02 01:04:59 PM PDT 24 Apr 02 01:07:30 PM PDT 24 113378447658 ps
T264 /workspace/coverage/default/18.sysrst_ctrl_auto_blk_key_output.1954250648 Apr 02 01:03:45 PM PDT 24 Apr 02 01:07:59 PM PDT 24 206212048090 ps
T125 /workspace/coverage/default/32.sysrst_ctrl_ultra_low_pwr.1553655488 Apr 02 01:04:39 PM PDT 24 Apr 02 01:04:46 PM PDT 24 45318957685 ps
T378 /workspace/coverage/default/13.sysrst_ctrl_in_out_inverted.3068175098 Apr 02 01:03:27 PM PDT 24 Apr 02 01:03:35 PM PDT 24 2453364900 ps
T379 /workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.1235523814 Apr 02 01:05:10 PM PDT 24 Apr 02 01:05:12 PM PDT 24 2676747529 ps
T380 /workspace/coverage/default/28.sysrst_ctrl_pin_access_test.3179794210 Apr 02 01:04:26 PM PDT 24 Apr 02 01:04:34 PM PDT 24 2122308170 ps
T381 /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.117336621 Apr 02 01:02:29 PM PDT 24 Apr 02 01:02:31 PM PDT 24 2558281841 ps
T297 /workspace/coverage/default/23.sysrst_ctrl_combo_detect.3895750784 Apr 02 01:04:07 PM PDT 24 Apr 02 01:06:50 PM PDT 24 120730164632 ps
T382 /workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.2361877586 Apr 02 01:02:59 PM PDT 24 Apr 02 01:03:04 PM PDT 24 12501854365 ps
T383 /workspace/coverage/default/15.sysrst_ctrl_smoke.64267495 Apr 02 01:03:33 PM PDT 24 Apr 02 01:03:37 PM PDT 24 2120829855 ps
T310 /workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.388031390 Apr 02 01:05:48 PM PDT 24 Apr 02 01:08:14 PM PDT 24 56907887887 ps
T384 /workspace/coverage/default/26.sysrst_ctrl_pin_override_test.708033430 Apr 02 01:04:23 PM PDT 24 Apr 02 01:04:31 PM PDT 24 2509943435 ps
T385 /workspace/coverage/default/14.sysrst_ctrl_pin_override_test.1147177208 Apr 02 01:03:30 PM PDT 24 Apr 02 01:03:33 PM PDT 24 2528336429 ps
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T239 /workspace/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.79201223 Apr 02 01:02:50 PM PDT 24 Apr 02 01:03:43 PM PDT 24 36314776409 ps
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T421 /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.2801665755 Apr 02 01:02:47 PM PDT 24 Apr 02 01:02:50 PM PDT 24 2246718389 ps
T422 /workspace/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.3659071255 Apr 02 01:03:18 PM PDT 24 Apr 02 01:03:20 PM PDT 24 2636474261 ps
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T423 /workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.878469671 Apr 02 01:05:49 PM PDT 24 Apr 02 01:06:51 PM PDT 24 22078770748 ps
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