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Summary for Variable cp_pwrb_out

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_pwrb_out

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 159 1 T61 9 T287 10 T288 9
auto[1] 181 1 T61 11 T287 10 T288 11


Summary for Variable cp_z3_wakeup

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_z3_wakeup

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 170 1 T61 10 T287 12 T288 12
auto[1] 170 1 T61 10 T287 8 T288 8


Summary for Cross key0_inXval

Samples crossed: cp_key0_in cfg.vif.key0_in
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for key0_inXval

Bins
cp_key0_incfg.vif.key0_inCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 80 1 T61 4 T287 5 T288 5
auto[0] auto[1] 90 1 T61 3 T287 6 T288 7
auto[1] auto[0] 90 1 T61 7 T287 4 T288 5
auto[1] auto[1] 80 1 T61 6 T287 5 T288 3


Summary for Cross key0_outXval

Samples crossed: cp_key0_out cfg.vif.key0_out
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for key0_outXval

Bins
cp_key0_outcfg.vif.key0_outCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 82 1 T61 3 T287 5 T288 3
auto[0] auto[1] 88 1 T61 3 T287 3 T288 9
auto[1] auto[0] 92 1 T61 7 T287 7 T288 3
auto[1] auto[1] 78 1 T61 7 T287 5 T288 5


Summary for Cross key1_inXval

Samples crossed: cp_key1_in cfg.vif.key1_in
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for key1_inXval

Bins
cp_key1_incfg.vif.key1_inCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 85 1 T61 3 T287 4 T288 4
auto[0] auto[1] 84 1 T61 7 T287 10 T288 5
auto[1] auto[0] 80 1 T61 6 T287 3 T288 5
auto[1] auto[1] 91 1 T61 4 T287 3 T288 6


Summary for Cross key1_outXval

Samples crossed: cp_key1_out cfg.vif.key1_out
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for key1_outXval

Bins
cp_key1_outcfg.vif.key1_outCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 94 1 T61 2 T287 3 T288 3
auto[0] auto[1] 93 1 T61 9 T287 7 T288 5
auto[1] auto[0] 71 1 T61 4 T287 6 T288 5
auto[1] auto[1] 82 1 T61 5 T287 4 T288 7


Summary for Cross key2_inXval

Samples crossed: cp_key2_in cfg.vif.key2_in
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for key2_inXval

Bins
cp_key2_incfg.vif.key2_inCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 91 1 T61 8 T287 5 T288 5
auto[0] auto[1] 71 1 T61 4 T287 4 T288 5
auto[1] auto[0] 91 1 T61 4 T287 3 T288 6
auto[1] auto[1] 87 1 T61 4 T287 8 T288 4


Summary for Cross key2_outXval

Samples crossed: cp_key2_out cfg.vif.key2_out
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for key2_outXval

Bins
cp_key2_outcfg.vif.key2_outCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 89 1 T61 8 T287 6 T288 3
auto[0] auto[1] 79 1 T61 4 T287 4 T288 6
auto[1] auto[0] 83 1 T61 4 T287 3 T288 5
auto[1] auto[1] 89 1 T61 4 T287 7 T288 6


Summary for Cross pwrb_inXval

Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for pwrb_inXval

Bins
cp_pwrb_incfg.vif.pwrb_inCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 91 1 T61 6 T287 5 T288 7
auto[0] auto[1] 84 1 T61 5 T287 9 T288 8
auto[1] auto[0] 74 1 T61 2 T287 2 T288 1
auto[1] auto[1] 91 1 T61 7 T287 4 T288 4


Summary for Cross pwrb_outXval

Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for pwrb_outXval

Bins
cp_pwrb_outcfg.vif.pwrb_outCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 87 1 T61 6 T287 4 T288 5
auto[0] auto[1] 72 1 T61 3 T287 6 T288 4
auto[1] auto[0] 86 1 T61 4 T287 5 T288 5
auto[1] auto[1] 95 1 T61 7 T287 5 T288 6


Summary for Cross ac_presentXval

Samples crossed: cp_ac_present cfg.vif.ac_present
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for ac_presentXval

Bins
cp_ac_presentcfg.vif.ac_presentCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 102 1 T61 8 T287 7 T288 5
auto[0] auto[1] 85 1 T61 2 T287 7 T288 7
auto[1] auto[0] 83 1 T61 4 T287 4 T288 3
auto[1] auto[1] 70 1 T61 6 T287 2 T288 5


Summary for Cross bat_disableXval

Samples crossed: cp_bat_disable cfg.vif.bat_disable
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 2 0 2 100.00
Automatically Generated Cross Bins 2 0 2 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for bat_disableXval

Bins
cp_bat_disablecfg.vif.bat_disableCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 175 1 T61 13 T287 7 T288 10
auto[1] auto[1] 165 1 T61 7 T287 13 T288 10


User Defined Cross Bins for bat_disableXval

Excluded/Illegal bins
NAMECOUNTSTATUS
invalid0 0 Excluded
invalid1 0 Excluded


Summary for Cross lid_openXval

Samples crossed: cp_lid_open cfg.vif.lid_open
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for lid_openXval

Bins
cp_lid_opencfg.vif.lid_openCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 77 1 T61 7 T287 2 T288 4
auto[0] auto[1] 88 1 T61 3 T287 10 T288 3
auto[1] auto[0] 80 1 T61 7 T287 3 T288 7
auto[1] auto[1] 95 1 T61 3 T287 5 T288 6


Summary for Cross z3_wakeupXval

Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 2 0 2 100.00
Automatically Generated Cross Bins 2 0 2 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for z3_wakeupXval

Bins
cp_z3_wakeupcfg.vif.z3_wakeupCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 170 1 T61 10 T287 12 T288 12
auto[1] auto[1] 170 1 T61 10 T287 8 T288 8


User Defined Cross Bins for z3_wakeupXval

Excluded/Illegal bins
NAMECOUNTSTATUS
invalid0 0 Excluded
invalid1 0 Excluded

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