Unified Coverage Report :: Group Instance : sysrst_ctrl_combo_intr_status_cg

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1310

1

T1

7

T2

14

T3

7

auto[1]

1925

1

T1

26

T3

15

T6

6

---

Summary for Variable cp_combo0_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo0_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2696

1

T1

20

T2

10

T3

20

auto[1]

539

1

T1

13

T2

4

T3

2

---

Summary for Variable cp_combo1_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo1_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3143

1

T1

33

T2

14

T3

22

auto[1]

92

1

T12

1

T28

1

T29

2

---

Summary for Variable cp_combo2_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo2_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3090

1

T1

33

T2

14

T3

20

auto[1]

145

1

T3

2

T30

4

T31

9

---

Summary for Variable cp_combo3_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo3_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3030

1

T1

20

T2

14

T3

22

auto[1]

205

1

T1

13

T6

2

T12

1

---

Summary for Variable cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_interrupt

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2057

1

T1

33

T2

9

T3

22

auto[1]

1178

1

T2

5

T6

8

T7

9

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1310

1

T1

13

T2

3

T3

7

auto[1]

1925

1

T1

20

T2

11

T3

15

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1373

1

T1

10

T2

14

T3

12

auto[1]

1862

1

T1

23

T3

10

T6

9

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1361

1

T1

11

T2

14

T3

11

auto[1]

1874

1

T1

22

T3

11

T6

5

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1347

1

T1

8

T2

4

T3

7

auto[1]

1888

1

T1

25

T2

10

T3

15

---

Summary for Cross cross_combo0

Samples crossed: cp_combo0_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	0	96	100.00
Automatically Generated Cross Bins	96	0	96	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo0

Bins

cp_combo0_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

48

1

T2

2

T7

1

T64

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

20

1

T185

1

T76

1

T233

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

53

1

T1

1

T7

1

T38

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

17

1

T87

1

T192

2

T97

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

45

1

T2

1

T3

1

T64

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

12

1

T41

1

T31

1

T233

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

43

1

T1

1

T3

1

T69

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

21

1

T29

3

T76

1

T87

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

48

1

T3

1

T64

1

T30

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

11

1

T159

1

T181

1

T223

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

49

1

T7

2

T12

1

T28

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

17

1

T29

1

T34

1

T192

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

52

1

T6

1

T7

1

T12

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

21

1

T6

1

T185

1

T76

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

38

1

T3

2

T64

1

T138

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

24

1

T7

5

T29

2

T185

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

47

1

T215

1

T216

1

T138

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

16

1

T41

1

T29

1

T87

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

50

1

T1

1

T12

1

T69

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

25

1

T41

1

T76

4

T233

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

48

1

T1

1

T6

1

T30

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

19

1

T41

1

T29

1

T228

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

39

1

T12

1

T30

1

T76

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

28

1

T29

1

T87

1

T192

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

44

1

T12

1

T30

1

T216

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

17

1

T41

1

T29

1

T185

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

39

1

T3

1

T12

1

T64

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

37

1

T76

3

T87

2

T233

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

63

1

T1

1

T30

1

T215

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

32

1

T29

1

T76

2

T31

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

73

1

T64

1

T69

9

T212

8

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

35

1

T12

9

T185

1

T228

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

64

1

T2

2

T6

1

T41

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

10

1

T233

1

T296

1

T297

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

39

1

T64

1

T216

1

T217

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

18

1

T41

1

T185

1

T128

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

49

1

T2

4

T3

1

T6

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

18

1

T2

1

T41

3

T31

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

66

1

T3

1

T30

1

T216

7

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

20

1

T41

1

T38

1

T185

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

37

1

T6

1

T38

1

T64

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

21

1

T29

1

T185

3

T233

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

68

1

T1

1

T3

2

T219

9

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

31

1

T41

1

T228

1

T194

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

46

1

T6

1

T64

1

T215

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

25

1

T6

1

T29

1

T228

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

103

1

T1

1

T3

2

T28

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

60

1

T38

8

T29

1

T185

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

43

1

T3

2

T6

1

T28

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

17

1

T41

1

T185

1

T87

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

70

1

T3

1

T38

1

T64

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

29

1

T6

1

T185

1

T76

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

41

1

T3

1

T6

1

T64

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

14

1

T41

1

T87

1

T80

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

92

1

T3

2

T89

5

T198

6

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

43

1

T6

4

T29

1

T31

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

55

1

T28

6

T64

1

T30

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

24

1

T41

2

T29

1

T228

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

42

1

T69

3

T34

1

T138

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

44

1

T41

1

T29

1

T76

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

72

1

T64

1

T138

2

T298

6

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

34

1

T41

3

T215

9

T31

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

253

1

T1

13

T3

2

T29

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

17

1

T185

1

T34

1

T128

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

5

1

T233

1

T97

1

T299

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

6

1

T185

1

T31

1

T228

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

5

1

T76

1

T228

1

T204

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

9

1

T185

1

T97

1

T98

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

8

1

T31

1

T228

2

T194

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

6

1

T300

1

T301

1

T302

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

5

1

T181

1

T296

1

T301

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

10

1

T7

4

T31

1

T228

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

4

1

T29

1

T80

1

T181

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

9

1

T31

1

T296

1

T222

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

4

1

T159

1

T192

1

T303

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

15

1

T304

1

T296

3

T303

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

6

1

T192

1

T296

1

T201

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

6

1

T228

1

T233

1

T305

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

13

1

T87

1

T296

1

T306

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

9

1

T228

1

T192

1

T201

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

7

1

T31

1

T307

1

T296

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

8

1

T31

2

T228

1

T275

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

10

1

T2

4

T31

1

T228

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

4

1

T128

1

T181

1

T308

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

9

1

T228

1

T192

1

T307

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

6

1

T194

3

T297

1

T301

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

12

1

T31

1

T233

2

T192

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

8

1

T192

1

T97

1

T181

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

12

1

T228

1

T192

2

T296

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

7

1

T6

1

T185

1

T97

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

9

1

T185

1

T31

1

T233

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

6

1

T233

2

T181

1

T309

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

7

1

T97

2

T223

1

T303

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

15

1

T76

1

T192

1

T307

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

10

1

T181

1

T297

1

T222

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

151

1

T29

1

T185

5

T76

1

User Defined Cross Bins for cross_combo0

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo1

Samples crossed: cp_combo1_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	30	66	68.75	30
Automatically Generated Cross Bins	96	30	66	68.75	30
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo1

Element holes

cp_combo1_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[0]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[0]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_combo1_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_combo1_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

52

1

T2

2

T7

1

T64

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

25

1

T185

1

T76

1

T233

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

58

1

T1

1

T7

1

T38

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

23

1

T185

1

T31

1

T228

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

46

1

T2

1

T3

1

T64

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

17

1

T41

1

T76

1

T31

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

45

1

T1

3

T3

1

T69

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

30

1

T29

3

T185

1

T76

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

50

1

T3

1

T64

1

T30

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

19

1

T31

1

T228

2

T159

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

54

1

T7

2

T12

1

T28

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

23

1

T29

1

T34

1

T192

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

56

1

T1

1

T3

1

T6

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

26

1

T6

1

T185

1

T76

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

41

1

T1

1

T3

2

T64

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

34

1

T7

9

T29

2

T185

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

52

1

T215

1

T216

1

T138

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

20

1

T41

1

T29

2

T87

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

56

1

T1

2

T12

1

T30

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

34

1

T41

1

T76

4

T31

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

57

1

T1

2

T6

1

T30

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

23

1

T41

1

T29

1

T228

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

40

1

T1

1

T30

1

T76

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

42

1

T29

1

T87

1

T192

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

46

1

T12

1

T30

1

T216

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

23

1

T41

1

T29

1

T185

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

42

1

T1

1

T3

1

T12

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

43

1

T76

3

T228

1

T87

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

63

1

T1

1

T30

1

T215

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

45

1

T29

1

T76

2

T31

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

75

1

T64

1

T69

9

T128

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

44

1

T12

9

T185

1

T228

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

69

1

T2

2

T6

1

T41

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

17

1

T31

1

T233

1

T307

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

45

1

T64

1

T216

1

T217

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

26

1

T41

1

T185

1

T31

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

51

1

T2

4

T3

1

T6

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

28

1

T2

5

T41

3

T31

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

69

1

T1

1

T3

1

T30

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

24

1

T41

1

T38

1

T185

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

40

1

T6

1

T38

1

T64

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

30

1

T29

1

T185

3

T228

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

67

1

T1

1

T3

2

T219

9

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

37

1

T41

1

T228

1

T194

6

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

51

1

T1

1

T6

1

T64

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

37

1

T6

1

T29

1

T31

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

102

1

T1

1

T3

2

T28

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

68

1

T38

8

T29

1

T185

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

46

1

T1

1

T3

2

T6

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

29

1

T41

1

T185

1

T228

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

69

1

T3

1

T38

1

T64

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

36

1

T6

2

T185

2

T76

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

45

1

T3

1

T6

1

T64

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

23

1

T41

1

T185

1

T31

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

93

1

T3

3

T128

1

T89

5

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

49

1

T6

4

T29

1

T31

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

62

1

T1

1

T28

6

T64

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

31

1

T41

2

T29

1

T228

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

45

1

T1

1

T69

3

T34

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

59

1

T41

1

T29

1

T76

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

79

1

T64

1

T138

2

T128

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

44

1

T41

3

T215

9

T31

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

209

1

T1

13

T3

2

T30

8

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

159

1

T29

1

T185

6

T76

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

1

1

T310

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

9

1

T303

1

T300

2

T302

1

User Defined Cross Bins for cross_combo1

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo2

Samples crossed: cp_combo2_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	31	65	67.71	31
Automatically Generated Cross Bins	96	31	65	67.71	31
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo2

Element holes

cp_combo2_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	*	*	*	*	[auto[1]]	--	--	16
[auto[1]]	[auto[1]]	[auto[0]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_combo2_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_combo2_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

52

1

T2

2

T7

1

T64

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

25

1

T185

1

T76

1

T233

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

58

1

T1

1

T7

1

T38

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

23

1

T185

1

T31

1

T228

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

46

1

T2

1

T3

1

T64

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

17

1

T41

1

T76

1

T31

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

46

1

T1

3

T3

1

T69

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

30

1

T29

3

T185

1

T76

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

49

1

T3

1

T64

1

T30

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

19

1

T31

1

T228

2

T159

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

52

1

T7

2

T12

1

T28

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

23

1

T29

1

T34

1

T192

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

55

1

T1

1

T3

1

T6

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

26

1

T6

1

T185

1

T76

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

41

1

T1

1

T3

2

T64

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

34

1

T7

9

T29

2

T185

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

52

1

T215

1

T216

1

T138

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

20

1

T41

1

T29

2

T87

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

56

1

T1

2

T12

1

T30

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

34

1

T41

1

T76

4

T31

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

57

1

T1

2

T6

1

T30

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

23

1

T41

1

T29

1

T228

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

38

1

T1

1

T12

1

T30

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

43

1

T29

1

T87

1

T192

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

45

1

T12

1

T30

1

T216

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

23

1

T41

1

T29

1

T185

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

38

1

T1

1

T3

1

T12

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

43

1

T76

3

T228

1

T87

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

63

1

T1

1

T30

1

T215

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

45

1

T29

1

T76

2

T31

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

75

1

T64

1

T69

9

T128

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

44

1

T12

9

T185

1

T228

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

70

1

T2

2

T6

1

T41

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

17

1

T31

1

T233

1

T307

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

47

1

T64

1

T216

1

T217

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

26

1

T41

1

T185

1

T31

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

52

1

T2

4

T3

1

T6

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

28

1

T2

5

T41

3

T31

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

69

1

T1

1

T3

1

T30

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

24

1

T41

1

T38

1

T185

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

40

1

T6

1

T38

1

T64

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

30

1

T29

1

T185

3

T228

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

70

1

T1

1

T3

2

T219

9

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

37

1

T41

1

T228

1

T194

6

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

47

1

T1

1

T6

1

T64

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

37

1

T6

1

T29

1

T31

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

100

1

T1

1

T3

2

T28

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

68

1

T38

8

T29

1

T185

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

47

1

T1

1

T3

2

T6

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

29

1

T41

1

T185

1

T228

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

75

1

T3

1

T38

1

T64

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

36

1

T6

2

T185

2

T76

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

45

1

T3

1

T6

1

T64

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

23

1

T41

1

T185

1

T31

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

94

1

T3

3

T128

1

T89

5

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

49

1

T6

4

T29

1

T31

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

63

1

T1

1

T28

6

T64

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

31

1

T41

2

T29

1

T228

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

48

1

T1

1

T69

3

T34

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

59

1

T41

1

T29

1

T76

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

81

1

T64

1

T138

2

T128

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

44

1

T41

3

T215

9

T31

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

160

1

T1

13

T29

2

T30

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

149

1

T29

1

T185

6

T76

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

19

1

T31

1

T228

2

T233

5

User Defined Cross Bins for cross_combo2

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo3

Samples crossed: cp_combo3_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	30	66	68.75	30
Automatically Generated Cross Bins	96	30	66	68.75	30
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo3

Element holes

cp_combo3_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	*	*	*	*	[auto[1]]	--	--	16
[auto[1]]	[auto[1]]	[auto[0]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	*	[auto[0]]	[auto[1]]	--	--	2

Covered bins

cp_combo3_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

52

1

T2

2

T7

1

T64

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

25

1

T185

1

T76

1

T233

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

58

1

T1

1

T7

1

T38

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

23

1

T185

1

T31

1

T228

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

46

1

T2

1

T3

1

T64

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

17

1

T41

1

T76

1

T31

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

46

1

T1

3

T3

1

T69

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

30

1

T29

3

T185

1

T76

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

49

1

T3

1

T64

1

T30

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

19

1

T31

1

T228

2

T159

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

53

1

T7

2

T12

1

T28

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

23

1

T29

1

T34

1

T192

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

54

1

T1

1

T3

1

T6

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

26

1

T6

1

T185

1

T76

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

39

1

T1

1

T3

2

T64

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

34

1

T7

9

T29

2

T185

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

51

1

T215

1

T216

1

T138

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

20

1

T41

1

T29

2

T87

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

55

1

T1

2

T12

1

T30

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

34

1

T41

1

T76

4

T31

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

52

1

T1

2

T6

1

T30

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

23

1

T41

1

T29

1

T228

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

41

1

T1

1

T30

1

T76

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

43

1

T29

1

T87

1

T192

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

47

1

T12

1

T30

1

T216

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

23

1

T41

1

T29

1

T185

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

38

1

T1

1

T3

1

T12

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

43

1

T76

3

T228

1

T87

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

56

1

T1

1

T30

1

T215

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

45

1

T29

1

T76

2

T31

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

71

1

T64

1

T69

7

T128

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

44

1

T12

9

T185

1

T228

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

69

1

T2

2

T6

1

T41

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

17

1

T31

1

T233

1

T307

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

47

1

T64

1

T216

1

T217

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

26

1

T41

1

T185

1

T31

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

51

1

T2

4

T3

1

T6

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

28

1

T2

5

T41

3

T31

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

68

1

T1

1

T3

1

T30

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

24

1

T41

1

T38

1

T185

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

40

1

T6

1

T38

1

T64

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

30

1

T29

1

T185

3

T228

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

66

1

T1

1

T3

2

T219

9

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

37

1

T41

1

T228

1

T194

6

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

50

1

T1

1

T64

1

T30

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

37

1

T6

1

T29

1

T31

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

103

1

T1

1

T3

2

T28

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

68

1

T38

8

T29

1

T185

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

47

1

T1

1

T3

2

T6

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

29

1

T41

1

T185

1

T228

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

71

1

T3

1

T38

1

T64

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

36

1

T6

2

T185

2

T76

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

44

1

T3

1

T6

1

T64

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

23

1

T41

1

T185

1

T31

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

92

1

T3

3

T128

1

T89

5

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

49

1

T6

4

T29

1

T31

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

63

1

T1

1

T28

6

T64

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

31

1

T41

2

T29

1

T228

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

47

1

T1

1

T69

3

T34

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

57

1

T41

1

T29

1

T76

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

78

1

T64

1

T138

2

T128

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

44

1

T41

3

T215

9

T31

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

138

1

T3

2

T185

1

T76

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

140

1

T29

1

T185

6

T76

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

2

1

T311

2

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

28

1

T31

2

T233

2

T192

4

User Defined Cross Bins for cross_combo3

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded